Lines Matching +full:aux +full:- +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pinctrl/pinconf-generic.h>
40 struct drm_dp_aux aux; member
48 struct tegra_output *output; member
66 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux) in to_dpaux() argument
68 return container_of(aux, struct tegra_dpaux, aux); in to_dpaux()
79 u32 value = readl(dpaux->regs + (offset << 2)); in tegra_dpaux_readl()
81 trace_dpaux_readl(dpaux->dev, offset, value); in tegra_dpaux_readl()
89 trace_dpaux_writel(dpaux->dev, offset, value); in tegra_dpaux_writel()
90 writel(value, dpaux->regs + (offset << 2)); in tegra_dpaux_writel()
99 size_t num = min_t(size_t, size - i * 4, 4); in tegra_dpaux_write_fifo()
115 size_t num = min_t(size_t, size - i * 4, 4); in tegra_dpaux_read_fifo()
125 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux, in tegra_dpaux_transfer() argument
129 struct tegra_dpaux *dpaux = to_dpaux(aux); in tegra_dpaux_transfer()
135 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */ in tegra_dpaux_transfer()
136 if (msg->size > 16) in tegra_dpaux_transfer()
137 return -EINVAL; in tegra_dpaux_transfer()
140 * Allow zero-sized messages only for I2C, in which case they specify in tegra_dpaux_transfer()
141 * address-only transactions. in tegra_dpaux_transfer()
143 if (msg->size < 1) { in tegra_dpaux_transfer()
144 switch (msg->request & ~DP_AUX_I2C_MOT) { in tegra_dpaux_transfer()
152 return -EINVAL; in tegra_dpaux_transfer()
155 /* For non-zero-sized messages, set the CMDLEN field. */ in tegra_dpaux_transfer()
156 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1); in tegra_dpaux_transfer()
159 switch (msg->request & ~DP_AUX_I2C_MOT) { in tegra_dpaux_transfer()
161 if (msg->request & DP_AUX_I2C_MOT) in tegra_dpaux_transfer()
169 if (msg->request & DP_AUX_I2C_MOT) in tegra_dpaux_transfer()
177 if (msg->request & DP_AUX_I2C_MOT) in tegra_dpaux_transfer()
193 return -EINVAL; in tegra_dpaux_transfer()
196 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR); in tegra_dpaux_transfer()
199 if ((msg->request & DP_AUX_I2C_READ) == 0) { in tegra_dpaux_transfer()
200 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size); in tegra_dpaux_transfer()
201 ret = msg->size; in tegra_dpaux_transfer()
209 status = wait_for_completion_timeout(&dpaux->complete, timeout); in tegra_dpaux_transfer()
211 return -ETIMEDOUT; in tegra_dpaux_transfer()
218 return -ETIMEDOUT; in tegra_dpaux_transfer()
223 return -EIO; in tegra_dpaux_transfer()
247 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) { in tegra_dpaux_transfer()
248 if (msg->request & DP_AUX_I2C_READ) { in tegra_dpaux_transfer()
254 * an -EBUSY return value, simply reuse that instead. in tegra_dpaux_transfer()
256 if (count != msg->size) { in tegra_dpaux_transfer()
257 ret = -EBUSY; in tegra_dpaux_transfer()
261 tegra_dpaux_read_fifo(dpaux, msg->buffer, count); in tegra_dpaux_transfer()
266 msg->reply = reply; in tegra_dpaux_transfer()
276 if (dpaux->output) in tegra_dpaux_hotplug()
277 drm_helper_hpd_irq_event(dpaux->output->connector.dev); in tegra_dpaux_hotplug()
290 schedule_work(&dpaux->work); in tegra_dpaux_irq()
297 complete(&dpaux->complete); in tegra_dpaux_irq()
332 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) | in tegra_dpaux_pad_config()
333 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) | in tegra_dpaux_pad_config()
334 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) | in tegra_dpaux_pad_config()
342 DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) | in tegra_dpaux_pad_config()
343 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) | in tegra_dpaux_pad_config()
344 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) | in tegra_dpaux_pad_config()
353 return -ENOTSUPP; in tegra_dpaux_pad_config()
371 "dpaux-io",
375 "aux",
453 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); in tegra_dpaux_probe()
455 return -ENOMEM; in tegra_dpaux_probe()
457 dpaux->soc = of_device_get_match_data(&pdev->dev); in tegra_dpaux_probe()
458 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug); in tegra_dpaux_probe()
459 init_completion(&dpaux->complete); in tegra_dpaux_probe()
460 INIT_LIST_HEAD(&dpaux->list); in tegra_dpaux_probe()
461 dpaux->dev = &pdev->dev; in tegra_dpaux_probe()
463 dpaux->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dpaux_probe()
464 if (IS_ERR(dpaux->regs)) in tegra_dpaux_probe()
465 return PTR_ERR(dpaux->regs); in tegra_dpaux_probe()
467 dpaux->irq = platform_get_irq(pdev, 0); in tegra_dpaux_probe()
468 if (dpaux->irq < 0) in tegra_dpaux_probe()
469 return dpaux->irq; in tegra_dpaux_probe()
471 if (!pdev->dev.pm_domain) { in tegra_dpaux_probe()
472 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); in tegra_dpaux_probe()
473 if (IS_ERR(dpaux->rst)) { in tegra_dpaux_probe()
474 dev_err(&pdev->dev, in tegra_dpaux_probe()
476 PTR_ERR(dpaux->rst)); in tegra_dpaux_probe()
477 return PTR_ERR(dpaux->rst); in tegra_dpaux_probe()
481 dpaux->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dpaux_probe()
482 if (IS_ERR(dpaux->clk)) { in tegra_dpaux_probe()
483 dev_err(&pdev->dev, "failed to get module clock: %ld\n", in tegra_dpaux_probe()
484 PTR_ERR(dpaux->clk)); in tegra_dpaux_probe()
485 return PTR_ERR(dpaux->clk); in tegra_dpaux_probe()
488 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_dpaux_probe()
489 if (IS_ERR(dpaux->clk_parent)) { in tegra_dpaux_probe()
490 dev_err(&pdev->dev, "failed to get parent clock: %ld\n", in tegra_dpaux_probe()
491 PTR_ERR(dpaux->clk_parent)); in tegra_dpaux_probe()
492 return PTR_ERR(dpaux->clk_parent); in tegra_dpaux_probe()
495 err = clk_set_rate(dpaux->clk_parent, 270000000); in tegra_dpaux_probe()
497 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", in tegra_dpaux_probe()
502 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd"); in tegra_dpaux_probe()
503 if (IS_ERR(dpaux->vdd)) { in tegra_dpaux_probe()
504 if (PTR_ERR(dpaux->vdd) != -ENODEV) { in tegra_dpaux_probe()
505 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER) in tegra_dpaux_probe()
506 dev_err(&pdev->dev, in tegra_dpaux_probe()
508 PTR_ERR(dpaux->vdd)); in tegra_dpaux_probe()
510 return PTR_ERR(dpaux->vdd); in tegra_dpaux_probe()
513 dpaux->vdd = NULL; in tegra_dpaux_probe()
517 pm_runtime_enable(&pdev->dev); in tegra_dpaux_probe()
518 pm_runtime_get_sync(&pdev->dev); in tegra_dpaux_probe()
520 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, in tegra_dpaux_probe()
521 dev_name(dpaux->dev), dpaux); in tegra_dpaux_probe()
523 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", in tegra_dpaux_probe()
524 dpaux->irq, err); in tegra_dpaux_probe()
528 disable_irq(dpaux->irq); in tegra_dpaux_probe()
530 dpaux->aux.transfer = tegra_dpaux_transfer; in tegra_dpaux_probe()
531 dpaux->aux.dev = &pdev->dev; in tegra_dpaux_probe()
533 drm_dp_aux_init(&dpaux->aux); in tegra_dpaux_probe()
539 * The DPAUX code paths reconfigure the pads in AUX mode, but there in tegra_dpaux_probe()
548 dpaux->desc.name = dev_name(&pdev->dev); in tegra_dpaux_probe()
549 dpaux->desc.pins = tegra_dpaux_pins; in tegra_dpaux_probe()
550 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins); in tegra_dpaux_probe()
551 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops; in tegra_dpaux_probe()
552 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops; in tegra_dpaux_probe()
553 dpaux->desc.owner = THIS_MODULE; in tegra_dpaux_probe()
555 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux); in tegra_dpaux_probe()
556 if (IS_ERR(dpaux->pinctrl)) { in tegra_dpaux_probe()
557 dev_err(&pdev->dev, "failed to register pincontrol\n"); in tegra_dpaux_probe()
558 err = PTR_ERR(dpaux->pinctrl); in tegra_dpaux_probe()
562 /* enable and clear all interrupts */ in tegra_dpaux_probe()
569 list_add_tail(&dpaux->list, &dpaux_list); in tegra_dpaux_probe()
572 err = devm_of_dp_aux_populate_ep_devices(&dpaux->aux); in tegra_dpaux_probe()
574 dev_err(dpaux->dev, "failed to populate AUX bus: %d\n", err); in tegra_dpaux_probe()
581 pm_runtime_put_sync(&pdev->dev); in tegra_dpaux_probe()
582 pm_runtime_disable(&pdev->dev); in tegra_dpaux_probe()
590 cancel_work_sync(&dpaux->work); in tegra_dpaux_remove()
595 pm_runtime_put_sync(&pdev->dev); in tegra_dpaux_remove()
596 pm_runtime_disable(&pdev->dev); in tegra_dpaux_remove()
599 list_del(&dpaux->list); in tegra_dpaux_remove()
608 if (dpaux->rst) { in tegra_dpaux_suspend()
609 err = reset_control_assert(dpaux->rst); in tegra_dpaux_suspend()
618 clk_disable_unprepare(dpaux->clk_parent); in tegra_dpaux_suspend()
619 clk_disable_unprepare(dpaux->clk); in tegra_dpaux_suspend()
629 err = clk_prepare_enable(dpaux->clk); in tegra_dpaux_resume()
631 dev_err(dev, "failed to enable clock: %d\n", err); in tegra_dpaux_resume()
635 err = clk_prepare_enable(dpaux->clk_parent); in tegra_dpaux_resume()
637 dev_err(dev, "failed to enable parent clock: %d\n", err); in tegra_dpaux_resume()
643 if (dpaux->rst) { in tegra_dpaux_resume()
644 err = reset_control_deassert(dpaux->rst); in tegra_dpaux_resume()
656 clk_disable_unprepare(dpaux->clk_parent); in tegra_dpaux_resume()
658 clk_disable_unprepare(dpaux->clk); in tegra_dpaux_resume()
685 { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
686 { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
687 { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
688 { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
695 .name = "tegra-dpaux",
710 if (np == dpaux->dev->of_node) { in drm_dp_aux_find_by_of_node()
712 return &dpaux->aux; in drm_dp_aux_find_by_of_node()
720 int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output) in drm_dp_aux_attach() argument
722 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_attach()
726 aux->drm_dev = output->connector.dev; in drm_dp_aux_attach()
727 err = drm_dp_aux_register(aux); in drm_dp_aux_attach()
731 output->connector.polled = DRM_CONNECTOR_POLL_HPD; in drm_dp_aux_attach()
732 dpaux->output = output; in drm_dp_aux_attach()
734 if (output->panel) { in drm_dp_aux_attach()
737 if (dpaux->vdd) { in drm_dp_aux_attach()
738 err = regulator_enable(dpaux->vdd); in drm_dp_aux_attach()
746 status = drm_dp_aux_detect(aux); in drm_dp_aux_attach()
755 return -ETIMEDOUT; in drm_dp_aux_attach()
758 enable_irq(dpaux->irq); in drm_dp_aux_attach()
762 int drm_dp_aux_detach(struct drm_dp_aux *aux) in drm_dp_aux_detach() argument
764 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_detach()
768 drm_dp_aux_unregister(aux); in drm_dp_aux_detach()
769 disable_irq(dpaux->irq); in drm_dp_aux_detach()
771 if (dpaux->output->panel) { in drm_dp_aux_detach()
774 if (dpaux->vdd) { in drm_dp_aux_detach()
775 err = regulator_disable(dpaux->vdd); in drm_dp_aux_detach()
783 status = drm_dp_aux_detect(aux); in drm_dp_aux_detach()
792 return -ETIMEDOUT; in drm_dp_aux_detach()
794 dpaux->output = NULL; in drm_dp_aux_detach()
800 enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux) in drm_dp_aux_detect() argument
802 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_detect()
813 int drm_dp_aux_enable(struct drm_dp_aux *aux) in drm_dp_aux_enable() argument
815 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_enable()
820 int drm_dp_aux_disable(struct drm_dp_aux *aux) in drm_dp_aux_disable() argument
822 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_disable()