56 	value = tegra_dc_readl(dc, offset);  in tegra_dc_readl_active()
88 	return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));  in tegra_plane_readl()
959 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in __tegra_cursor_atomic_update()
963 	value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);  in __tegra_cursor_atomic_update()
1024 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);  in tegra_cursor_atomic_disable()
1086 		(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);  in tegra_cursor_atomic_async_update()
1090 		(void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);  in tegra_cursor_atomic_async_update()
1664 			   offset, tegra_dc_readl(dc, offset));  in tegra_dc_show_regs()
1693 	value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);  in tegra_dc_show_crc()
1788 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);  in tegra_dc_enable_vblank()
1800 	value = tegra_dc_readl(dc, DC_CMD_INT_MASK);  in tegra_dc_disable_vblank()
1968 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_dc_stop()
2130 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_disable()
2257 		value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);  in tegra_crtc_atomic_enable()
2262 	value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);  in tegra_crtc_atomic_enable()
2268 		value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);  in tegra_crtc_atomic_enable()
2323 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
2327 	value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);  in tegra_crtc_atomic_flush()
2540 	status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);  in tegra_dc_irq()