Lines Matching full:dc
33 #include "dc.h"
51 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
55 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
56 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
57 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
80 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
88 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
94 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
97 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
99 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
122 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
124 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
125 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
318 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering() local
323 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
333 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering() local
338 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
341 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
351 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window() local
428 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
534 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
630 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); in tegra_plane_atomic_check() local
654 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
665 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
805 struct tegra_dc *dc) in tegra_primary_plane_create() argument
822 plane->dc = dc; in tegra_primary_plane_create()
824 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
825 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
826 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
852 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
908 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in __tegra_cursor_atomic_update() local
911 u64 dma_mask = *dc->dev->dma_mask; in __tegra_cursor_atomic_update()
924 if (!dc->soc->has_nvdisplay) in __tegra_cursor_atomic_update()
951 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in __tegra_cursor_atomic_update()
955 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in __tegra_cursor_atomic_update()
959 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in __tegra_cursor_atomic_update()
961 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in __tegra_cursor_atomic_update()
963 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in __tegra_cursor_atomic_update()
967 if (dc->soc->has_nvdisplay) in __tegra_cursor_atomic_update()
975 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in __tegra_cursor_atomic_update()
978 if (dc->soc->has_nvdisplay) { in __tegra_cursor_atomic_update()
987 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); in __tegra_cursor_atomic_update()
991 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); in __tegra_cursor_atomic_update()
999 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in __tegra_cursor_atomic_update()
1015 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
1022 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
1024 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1026 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
1071 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); in tegra_cursor_atomic_async_update() local
1085 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1086 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1089 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1090 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_cursor_atomic_async_update()
1110 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
1130 plane->dc = dc; in tegra_dc_cursor_plane_create()
1132 if (!dc->soc->has_nvdisplay) { in tegra_dc_cursor_plane_create()
1255 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
1272 plane->dc = dc; in tegra_dc_overlay_plane_create()
1274 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1275 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1307 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1314 struct tegra_dc *dc) in tegra_dc_add_shared_planes() argument
1319 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1320 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1322 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1332 plane = tegra_shared_plane_create(drm, dc, in tegra_dc_add_shared_planes()
1352 struct tegra_dc *dc) in tegra_dc_add_planes() argument
1359 primary = tegra_primary_plane_create(drm, dc); in tegra_dc_add_planes()
1363 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1369 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, in tegra_dc_add_planes()
1649 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1653 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1655 if (!dc->base.state->active) { in tegra_dc_show_regs()
1664 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1668 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1675 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc() local
1679 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1681 if (!dc->base.state->active) { in tegra_dc_show_crc()
1687 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1688 tegra_dc_commit(dc); in tegra_dc_show_crc()
1690 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1691 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1693 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1696 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1699 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1706 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats() local
1708 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1709 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1710 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1711 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1713 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); in tegra_dc_show_stats()
1714 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); in tegra_dc_show_stats()
1715 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); in tegra_dc_show_stats()
1716 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); in tegra_dc_show_stats()
1732 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_late_register() local
1740 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1742 if (!dc->debugfs_files) in tegra_dc_late_register()
1746 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1748 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1757 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_early_unregister() local
1766 drm_debugfs_remove_files(dc->debugfs_files, count, root, minor); in tegra_dc_early_unregister()
1767 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1768 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1773 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_get_vblank_counter() local
1776 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1777 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1780 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1785 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_enable_vblank() local
1788 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1790 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1797 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_disable_vblank() local
1800 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1802 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1819 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1826 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1827 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1830 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1835 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1839 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1843 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1846 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1854 * @dc: display controller
1863 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1870 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1880 static void tegra_dc_update_voltage_state(struct tegra_dc *dc, in tegra_dc_update_voltage_state() argument
1887 if (!dc->has_opp_table) in tegra_dc_update_voltage_state()
1891 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); in tegra_dc_update_voltage_state()
1894 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); in tegra_dc_update_voltage_state()
1902 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); in tegra_dc_update_voltage_state()
1905 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", in tegra_dc_update_voltage_state()
1920 err = dev_pm_genpd_set_performance_state(dc->dev, pstate); in tegra_dc_update_voltage_state()
1922 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", in tegra_dc_update_voltage_state()
1926 static void tegra_dc_set_clock_rate(struct tegra_dc *dc, in tegra_dc_set_clock_rate() argument
1931 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_set_clock_rate()
1933 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_set_clock_rate()
1946 dev_err(dc->dev, in tegra_dc_set_clock_rate()
1950 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_set_clock_rate()
1952 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_set_clock_rate()
1953 dc->clk, state->pclk, err); in tegra_dc_set_clock_rate()
1956 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_set_clock_rate()
1960 tegra_dc_update_voltage_state(dc, state); in tegra_dc_set_clock_rate()
1963 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1968 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1970 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1972 tegra_dc_commit(dc); in tegra_dc_stop()
1975 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1979 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1984 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1989 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1995 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
2009 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_update_memory_bandwidth() local
2013 if (dc->soc->has_nvdisplay) in tegra_crtc_update_memory_bandwidth()
2048 if (tegra->dc != dc) in tegra_crtc_update_memory_bandwidth()
2074 * freq should go high before the DC changes are committed in tegra_crtc_update_memory_bandwidth()
2099 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_disable() local
2103 if (!tegra_dc_idle(dc)) { in tegra_crtc_atomic_disable()
2104 tegra_dc_stop(dc); in tegra_crtc_atomic_disable()
2110 tegra_dc_wait_idle(dc, 100); in tegra_crtc_atomic_disable()
2129 if (dc->rgb) { in tegra_crtc_atomic_disable()
2130 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
2133 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
2136 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
2148 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
2150 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
2152 if (dc->has_opp_table) { in tegra_crtc_atomic_disable()
2153 err = dev_pm_genpd_set_performance_state(dc->dev, 0); in tegra_crtc_atomic_disable()
2155 dev_err(dc->dev, in tegra_crtc_atomic_disable()
2165 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_enable() local
2170 tegra_dc_set_clock_rate(dc, crtc_state); in tegra_crtc_atomic_enable()
2172 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
2174 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
2179 if (dc->syncpt) { in tegra_crtc_atomic_enable()
2180 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
2182 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
2188 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_atomic_enable()
2191 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_atomic_enable()
2194 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2197 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2204 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
2208 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
2211 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2213 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_crtc_atomic_enable()
2217 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
2221 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
2226 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_atomic_enable()
2230 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_atomic_enable()
2234 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
2238 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
2241 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
2242 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); in tegra_crtc_atomic_enable()
2244 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_crtc_atomic_enable()
2247 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2249 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_crtc_atomic_enable()
2253 tegra_dc_set_timings(dc, mode); in tegra_crtc_atomic_enable()
2256 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
2257 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
2259 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
2262 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
2265 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
2267 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2268 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
2271 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
2275 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
2277 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); in tegra_crtc_atomic_enable()
2280 if (dc->rgb) { in tegra_crtc_atomic_enable()
2283 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); in tegra_crtc_atomic_enable()
2286 tegra_dc_commit(dc); in tegra_crtc_atomic_enable()
2318 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
2322 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2323 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2326 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2327 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
2400 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_calculate_memory_bandwidth() local
2411 if (dc->soc->has_nvdisplay) in tegra_crtc_calculate_memory_bandwidth()
2445 * overlapping planes, where "simultaneously" means areas where DC in tegra_crtc_calculate_memory_bandwidth()
2537 struct tegra_dc *dc = data; in tegra_dc_irq() local
2540 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
2541 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
2545 dev_dbg(dc->dev, "%s(): frame end\n", __func__); in tegra_dc_irq()
2547 dc->stats.frames_total++; in tegra_dc_irq()
2548 dc->stats.frames++; in tegra_dc_irq()
2553 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); in tegra_dc_irq()
2555 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
2556 dc->stats.vblank_total++; in tegra_dc_irq()
2557 dc->stats.vblank++; in tegra_dc_irq()
2562 dev_dbg(dc->dev, "%s(): underflow\n", __func__); in tegra_dc_irq()
2564 dc->stats.underflow_total++; in tegra_dc_irq()
2565 dc->stats.underflow++; in tegra_dc_irq()
2570 dev_dbg(dc->dev, "%s(): overflow\n", __func__); in tegra_dc_irq()
2572 dc->stats.overflow_total++; in tegra_dc_irq()
2573 dc->stats.overflow++; in tegra_dc_irq()
2577 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2578 dc->stats.underflow_total++; in tegra_dc_irq()
2579 dc->stats.underflow++; in tegra_dc_irq()
2585 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) in tegra_dc_has_window_groups() argument
2589 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2592 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2593 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2595 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2616 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
2623 * DC has been reset by now, so VBLANK syncpoint can be released in tegra_dc_init()
2626 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); in tegra_dc_init()
2633 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_init()
2642 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2645 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2646 if (!dc->syncpt) in tegra_dc_init()
2647 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2655 if (dc->soc->wgrps) in tegra_dc_init()
2656 primary = tegra_dc_add_shared_planes(drm, dc); in tegra_dc_init()
2658 primary = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
2665 if (dc->soc->supports_cursor) { in tegra_dc_init()
2666 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
2673 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); in tegra_dc_init()
2680 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2685 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2691 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2692 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2695 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2700 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
2702 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2706 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2707 dev_name(dc->dev), dc); in tegra_dc_init()
2709 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2730 host1x_syncpt_put(dc->syncpt); in tegra_dc_init()
2737 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
2740 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_exit()
2746 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2748 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
2750 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2755 host1x_syncpt_put(dc->syncpt); in tegra_dc_exit()
2772 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_suspend() local
2776 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2782 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2783 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2785 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2793 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_resume() local
2803 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2804 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2805 dc->rst); in tegra_dc_runtime_resume()
2811 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2817 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2827 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
2960 .dc = 0,
2965 .dc = 1,
2970 .dc = 1,
2975 .dc = 2,
2980 .dc = 2,
2985 .dc = 2,
3011 .dc = 0,
3016 .dc = 1,
3021 .dc = 1,
3026 .dc = 2,
3031 .dc = 2,
3036 .dc = 2,
3061 .compatible = "nvidia,tegra194-dc",
3064 .compatible = "nvidia,tegra186-dc",
3067 .compatible = "nvidia,tegra210-dc",
3070 .compatible = "nvidia,tegra124-dc",
3073 .compatible = "nvidia,tegra114-dc",
3076 .compatible = "nvidia,tegra30-dc",
3079 .compatible = "nvidia,tegra20-dc",
3087 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
3093 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
3095 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
3110 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
3119 dc->pipe = value; in tegra_dc_parse_dt()
3126 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_match_by_pipe() local
3129 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
3132 static int tegra_dc_couple(struct tegra_dc *dc) in tegra_dc_couple() argument
3139 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
3143 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, in tegra_dc_couple()
3149 dc->client.parent = &parent->client; in tegra_dc_couple()
3151 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); in tegra_dc_couple()
3158 static int tegra_dc_init_opp_table(struct tegra_dc *dc) in tegra_dc_init_opp_table() argument
3163 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); in tegra_dc_init_opp_table()
3168 dc->has_opp_table = false; in tegra_dc_init_opp_table()
3170 dc->has_opp_table = true; in tegra_dc_init_opp_table()
3178 struct tegra_dc *dc; in tegra_dc_probe() local
3187 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
3188 if (!dc) in tegra_dc_probe()
3191 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
3193 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
3194 dc->dev = &pdev->dev; in tegra_dc_probe()
3196 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
3200 err = tegra_dc_couple(dc); in tegra_dc_probe()
3204 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
3205 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
3207 return PTR_ERR(dc->clk); in tegra_dc_probe()
3210 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
3211 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
3213 return PTR_ERR(dc->rst); in tegra_dc_probe()
3217 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
3223 err = reset_control_assert(dc->rst); in tegra_dc_probe()
3225 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
3231 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
3233 if (dc->soc->has_powergate) { in tegra_dc_probe()
3234 if (dc->pipe == 0) in tegra_dc_probe()
3235 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
3237 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
3239 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
3242 err = tegra_dc_init_opp_table(dc); in tegra_dc_probe()
3246 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
3247 if (IS_ERR(dc->regs)) in tegra_dc_probe()
3248 return PTR_ERR(dc->regs); in tegra_dc_probe()
3250 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
3251 if (dc->irq < 0) in tegra_dc_probe()
3254 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
3259 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
3262 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
3263 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
3264 dc->client.dev = &pdev->dev; in tegra_dc_probe()
3266 err = host1x_client_register(&dc->client); in tegra_dc_probe()
3277 tegra_dc_rgb_remove(dc); in tegra_dc_probe()
3284 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
3286 host1x_client_unregister(&dc->client); in tegra_dc_remove()
3288 tegra_dc_rgb_remove(dc); in tegra_dc_remove()
3295 .name = "tegra-dc",