Lines Matching full:phy
127 static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_set_polarity() argument
138 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_set_polarity()
147 struct sun8i_hdmi_phy *phy = data; in sun8i_a83t_hdmi_phy_config() local
149 sun8i_hdmi_phy_set_polarity(phy, mode); in sun8i_a83t_hdmi_phy_config()
151 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_a83t_hdmi_phy_config()
211 struct sun8i_hdmi_phy *phy = data; in sun8i_a83t_hdmi_phy_disable() local
216 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun8i_a83t_hdmi_phy_disable()
233 struct sun8i_hdmi_phy *phy = data; in sun8i_h3_hdmi_phy_config() local
242 if (phy->variant->has_phy_clk) in sun8i_h3_hdmi_phy_config()
243 clk_set_rate(phy->clk_phy, clk_rate); in sun8i_h3_hdmi_phy_config()
245 sun8i_hdmi_phy_set_polarity(phy, mode); in sun8i_h3_hdmi_phy_config()
304 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal); in sun8i_h3_hdmi_phy_config()
314 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal); in sun8i_h3_hdmi_phy_config()
340 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_h3_hdmi_phy_config()
344 * NOTE: We have to be careful not to overwrite PHY parent in sun8i_h3_hdmi_phy_config()
347 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_h3_hdmi_phy_config()
350 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, in sun8i_h3_hdmi_phy_config()
354 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG, in sun8i_h3_hdmi_phy_config()
356 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_h3_hdmi_phy_config()
362 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); in sun8i_h3_hdmi_phy_config()
367 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_h3_hdmi_phy_config()
372 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_h3_hdmi_phy_config()
376 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end); in sun8i_h3_hdmi_phy_config()
377 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init); in sun8i_h3_hdmi_phy_config()
378 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init); in sun8i_h3_hdmi_phy_config()
385 struct sun8i_hdmi_phy *phy = data; in sun8i_h3_hdmi_phy_disable() local
387 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_h3_hdmi_phy_disable()
391 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0); in sun8i_h3_hdmi_phy_disable()
402 static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_unlock() argument
405 regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG, in sun8i_hdmi_phy_unlock()
409 regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG, in sun8i_hdmi_phy_unlock()
413 static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy) in sun50i_hdmi_phy_init_h6() argument
415 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun50i_hdmi_phy_init_h6()
419 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, in sun50i_hdmi_phy_init_h6()
423 static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init_a83t() argument
425 sun8i_hdmi_phy_unlock(phy); in sun8i_hdmi_phy_init_a83t()
427 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_init_a83t()
432 * Set PHY I2C address. It must match to the address set by in sun8i_hdmi_phy_init_a83t()
435 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, in sun8i_hdmi_phy_init_a83t()
440 static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init_h3() argument
444 sun8i_hdmi_phy_unlock(phy); in sun8i_hdmi_phy_init_h3()
446 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0); in sun8i_hdmi_phy_init_h3()
447 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
451 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
454 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
458 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
462 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
466 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
470 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
473 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
482 regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val, in sun8i_hdmi_phy_init_h3()
486 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
489 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, in sun8i_hdmi_phy_init_h3()
500 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, in sun8i_hdmi_phy_init_h3()
506 /* reset PHY PLL clock parent */ in sun8i_hdmi_phy_init_h3()
507 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, in sun8i_hdmi_phy_init_h3()
511 regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0); in sun8i_hdmi_phy_init_h3()
514 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); in sun8i_hdmi_phy_init_h3()
515 phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2; in sun8i_hdmi_phy_init_h3()
518 int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_init() argument
522 ret = reset_control_deassert(phy->rst_phy); in sun8i_hdmi_phy_init()
524 dev_err(phy->dev, "Cannot deassert phy reset control: %d\n", ret); in sun8i_hdmi_phy_init()
528 ret = clk_prepare_enable(phy->clk_bus); in sun8i_hdmi_phy_init()
530 dev_err(phy->dev, "Cannot enable bus clock: %d\n", ret); in sun8i_hdmi_phy_init()
534 ret = clk_prepare_enable(phy->clk_mod); in sun8i_hdmi_phy_init()
536 dev_err(phy->dev, "Cannot enable mod clock: %d\n", ret); in sun8i_hdmi_phy_init()
540 if (phy->variant->has_phy_clk) { in sun8i_hdmi_phy_init()
541 ret = sun8i_phy_clk_create(phy, phy->dev, in sun8i_hdmi_phy_init()
542 phy->variant->has_second_pll); in sun8i_hdmi_phy_init()
544 dev_err(phy->dev, "Couldn't create the PHY clock\n"); in sun8i_hdmi_phy_init()
548 clk_prepare_enable(phy->clk_phy); in sun8i_hdmi_phy_init()
551 phy->variant->phy_init(phy); in sun8i_hdmi_phy_init()
556 clk_disable_unprepare(phy->clk_mod); in sun8i_hdmi_phy_init()
558 clk_disable_unprepare(phy->clk_bus); in sun8i_hdmi_phy_init()
560 reset_control_assert(phy->rst_phy); in sun8i_hdmi_phy_init()
565 void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy) in sun8i_hdmi_phy_deinit() argument
567 clk_disable_unprepare(phy->clk_mod); in sun8i_hdmi_phy_deinit()
568 clk_disable_unprepare(phy->clk_bus); in sun8i_hdmi_phy_deinit()
569 clk_disable_unprepare(phy->clk_phy); in sun8i_hdmi_phy_deinit()
571 reset_control_assert(phy->rst_phy); in sun8i_hdmi_phy_deinit()
574 void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, in sun8i_hdmi_phy_set_ops() argument
577 const struct sun8i_hdmi_phy_variant *variant = phy->variant; in sun8i_hdmi_phy_set_ops()
582 plat_data->phy_data = phy; in sun8i_hdmi_phy_set_ops()
595 .name = "phy"
631 .compatible = "allwinner,sun8i-a83t-hdmi-phy",
635 .compatible = "allwinner,sun8i-h3-hdmi-phy",
639 .compatible = "allwinner,sun8i-r40-hdmi-phy",
643 .compatible = "allwinner,sun50i-a64-hdmi-phy",
647 .compatible = "allwinner,sun50i-h6-hdmi-phy",
656 struct sun8i_hdmi_phy *phy; in sun8i_hdmi_phy_get() local
661 phy = platform_get_drvdata(pdev); in sun8i_hdmi_phy_get()
662 if (!phy) { in sun8i_hdmi_phy_get()
667 hdmi->phy = phy; in sun8i_hdmi_phy_get()
677 struct sun8i_hdmi_phy *phy; in sun8i_hdmi_phy_probe() local
680 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); in sun8i_hdmi_phy_probe()
681 if (!phy) in sun8i_hdmi_phy_probe()
684 phy->variant = of_device_get_match_data(dev); in sun8i_hdmi_phy_probe()
685 phy->dev = dev; in sun8i_hdmi_phy_probe()
690 "Couldn't map the HDMI PHY registers\n"); in sun8i_hdmi_phy_probe()
692 phy->regs = devm_regmap_init_mmio(dev, regs, in sun8i_hdmi_phy_probe()
694 if (IS_ERR(phy->regs)) in sun8i_hdmi_phy_probe()
695 return dev_err_probe(dev, PTR_ERR(phy->regs), in sun8i_hdmi_phy_probe()
696 "Couldn't create the HDMI PHY regmap\n"); in sun8i_hdmi_phy_probe()
698 phy->clk_bus = devm_clk_get(dev, "bus"); in sun8i_hdmi_phy_probe()
699 if (IS_ERR(phy->clk_bus)) in sun8i_hdmi_phy_probe()
700 return dev_err_probe(dev, PTR_ERR(phy->clk_bus), in sun8i_hdmi_phy_probe()
703 phy->clk_mod = devm_clk_get(dev, "mod"); in sun8i_hdmi_phy_probe()
704 if (IS_ERR(phy->clk_mod)) in sun8i_hdmi_phy_probe()
705 return dev_err_probe(dev, PTR_ERR(phy->clk_mod), in sun8i_hdmi_phy_probe()
708 if (phy->variant->has_phy_clk) { in sun8i_hdmi_phy_probe()
709 phy->clk_pll0 = devm_clk_get(dev, "pll-0"); in sun8i_hdmi_phy_probe()
710 if (IS_ERR(phy->clk_pll0)) in sun8i_hdmi_phy_probe()
711 return dev_err_probe(dev, PTR_ERR(phy->clk_pll0), in sun8i_hdmi_phy_probe()
714 if (phy->variant->has_second_pll) { in sun8i_hdmi_phy_probe()
715 phy->clk_pll1 = devm_clk_get(dev, "pll-1"); in sun8i_hdmi_phy_probe()
716 if (IS_ERR(phy->clk_pll1)) in sun8i_hdmi_phy_probe()
717 return dev_err_probe(dev, PTR_ERR(phy->clk_pll1), in sun8i_hdmi_phy_probe()
722 phy->rst_phy = devm_reset_control_get_shared(dev, "phy"); in sun8i_hdmi_phy_probe()
723 if (IS_ERR(phy->rst_phy)) in sun8i_hdmi_phy_probe()
724 return dev_err_probe(dev, PTR_ERR(phy->rst_phy), in sun8i_hdmi_phy_probe()
725 "Could not get phy reset control\n"); in sun8i_hdmi_phy_probe()
727 platform_set_drvdata(pdev, phy); in sun8i_hdmi_phy_probe()
735 .name = "sun8i-hdmi-phy",