Lines Matching +full:io +full:- +full:backends
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
11 #include <linux/media-bus-format.h>
48 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
50 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
66 return -EINVAL; in sun4i_tcon_get_pixel_depth()
68 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
69 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
70 return -EINVAL; in sun4i_tcon_get_pixel_depth()
72 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
81 return -EINVAL; in sun4i_tcon_get_pixel_depth()
91 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
92 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
95 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
98 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
99 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
102 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
121 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
130 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
134 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
137 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
147 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
154 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
159 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
168 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
178 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
181 if (tcon->quirks->setup_lvds_phy) in sun4i_tcon_lvds_set_status()
182 tcon->quirks->setup_lvds_phy(tcon, encoder); in sun4i_tcon_lvds_set_status()
184 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
196 switch (encoder->encoder_type) { in sun4i_tcon_set_status()
216 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon_set_status()
239 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); in sun4i_tcon_enable_vblank()
251 struct sun4i_drv *drv = drm->dev_private; in sun4i_get_tcon0()
254 list_for_each_entry(tcon, &drv->tcon_list, list) in sun4i_get_tcon0()
255 if (tcon->id == 0) in sun4i_get_tcon0()
258 dev_warn(drm->dev, in sun4i_get_tcon0()
267 int ret = -ENOTSUPP; in sun4i_tcon_set_mux()
269 if (tcon->quirks->set_mux) in sun4i_tcon_set_mux()
270 ret = tcon->quirks->set_mux(tcon, encoder); in sun4i_tcon_set_mux()
273 encoder->name, encoder->crtc->name, ret); in sun4i_tcon_set_mux()
279 int delay = mode->vtotal - mode->vdisplay; in sun4i_tcon_get_clk_delay()
281 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in sun4i_tcon_get_clk_delay()
285 delay -= 2; in sun4i_tcon_get_clk_delay()
310 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
311 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
312 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
313 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
314 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
315 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
316 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); in sun4i_tcon0_mode_set_dithering()
317 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); in sun4i_tcon0_mode_set_dithering()
318 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); in sun4i_tcon0_mode_set_dithering()
319 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); in sun4i_tcon0_mode_set_dithering()
322 if (connector->display_info.bpc == 6) in sun4i_tcon0_mode_set_dithering()
325 if (connector->display_info.num_bus_formats == 1) in sun4i_tcon0_mode_set_dithering()
326 bus_format = connector->display_info.bus_formats[0]; in sun4i_tcon0_mode_set_dithering()
343 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); in sun4i_tcon0_mode_set_dithering()
352 struct mipi_dsi_device *device = dsi->device; in sun4i_tcon0_mode_set_cpu()
353 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); in sun4i_tcon0_mode_set_cpu()
354 u8 lanes = device->lanes; in sun4i_tcon0_mode_set_cpu()
359 * dclk is required to run at 1/4 the DSI per-lane bit rate. in sun4i_tcon0_mode_set_cpu()
361 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
362 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
363 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes) in sun4i_tcon0_mode_set_cpu()
367 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_cpu()
368 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon0_mode_set_cpu()
369 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon0_mode_set_cpu()
374 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_cpu()
378 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, in sun4i_tcon0_mode_set_cpu()
381 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, in sun4i_tcon0_mode_set_cpu()
393 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); in sun4i_tcon0_mode_set_cpu()
395 block_space = mode->htotal * bpp / (tcon_div * lanes); in sun4i_tcon0_mode_set_cpu()
396 block_space -= mode->hdisplay + 40; in sun4i_tcon0_mode_set_cpu()
398 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, in sun4i_tcon0_mode_set_cpu()
400 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay)); in sun4i_tcon0_mode_set_cpu()
402 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, in sun4i_tcon0_mode_set_cpu()
403 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay)); in sun4i_tcon0_mode_set_cpu()
405 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1); in sun4i_tcon0_mode_set_cpu()
406 start_delay = start_delay * mode->crtc_htotal * 149; in sun4i_tcon0_mode_set_cpu()
407 start_delay = start_delay / (mode->crtc_clock / 1000) / 8; in sun4i_tcon0_mode_set_cpu()
408 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, in sun4i_tcon0_mode_set_cpu()
416 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, in sun4i_tcon0_mode_set_cpu()
421 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, in sun4i_tcon0_mode_set_cpu()
433 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_lvds()
435 tcon->dclk_min_div = 7; in sun4i_tcon0_mode_set_lvds()
436 tcon->dclk_max_div = 7; in sun4i_tcon0_mode_set_lvds()
437 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_lvds()
440 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_lvds()
441 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon0_mode_set_lvds()
442 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon0_mode_set_lvds()
449 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_lvds()
457 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_lvds()
459 mode->crtc_htotal, bp); in sun4i_tcon0_mode_set_lvds()
462 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_lvds()
463 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) | in sun4i_tcon0_mode_set_lvds()
470 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_lvds()
472 mode->crtc_vtotal, bp); in sun4i_tcon0_mode_set_lvds()
475 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_lvds()
476 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | in sun4i_tcon0_mode_set_lvds()
485 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); in sun4i_tcon0_mode_set_lvds()
488 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) in sun4i_tcon0_mode_set_lvds()
491 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) in sun4i_tcon0_mode_set_lvds()
494 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon0_mode_set_lvds()
497 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_lvds()
502 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); in sun4i_tcon0_mode_set_lvds()
510 const struct drm_display_info *info = &connector->display_info; in sun4i_tcon0_mode_set_rgb()
515 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_rgb()
517 tcon->dclk_min_div = tcon->quirks->dclk_min_div; in sun4i_tcon0_mode_set_rgb()
518 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_rgb()
519 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_rgb()
522 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_rgb()
523 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon0_mode_set_rgb()
524 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon0_mode_set_rgb()
531 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_rgb()
539 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
541 mode->crtc_htotal, bp); in sun4i_tcon0_mode_set_rgb()
544 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_rgb()
545 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | in sun4i_tcon0_mode_set_rgb()
552 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_rgb()
554 mode->crtc_vtotal, bp); in sun4i_tcon0_mode_set_rgb()
557 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_rgb()
558 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | in sun4i_tcon0_mode_set_rgb()
562 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
563 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_rgb()
565 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, in sun4i_tcon0_mode_set_rgb()
570 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon0_mode_set_rgb()
573 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon0_mode_set_rgb()
576 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) in sun4i_tcon0_mode_set_rgb()
579 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) in sun4i_tcon0_mode_set_rgb()
582 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, in sun4i_tcon0_mode_set_rgb()
590 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_rgb()
595 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); in sun4i_tcon0_mode_set_rgb()
605 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon1_mode_set()
608 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); in sun4i_tcon1_mode_set()
612 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
617 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in sun4i_tcon1_mode_set()
621 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
626 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, in sun4i_tcon1_mode_set()
627 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
628 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
631 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, in sun4i_tcon1_mode_set()
632 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
633 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
636 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, in sun4i_tcon1_mode_set()
637 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
638 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
641 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
643 mode->htotal, bp); in sun4i_tcon1_mode_set()
644 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, in sun4i_tcon1_mode_set()
645 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | in sun4i_tcon1_mode_set()
648 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon1_mode_set()
650 mode->crtc_vtotal, bp); in sun4i_tcon1_mode_set()
665 vtotal = mode->vtotal; in sun4i_tcon1_mode_set()
666 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) in sun4i_tcon1_mode_set()
670 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, in sun4i_tcon1_mode_set()
675 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
676 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; in sun4i_tcon1_mode_set()
678 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, in sun4i_tcon1_mode_set()
683 if (tcon->quirks->polarity_in_ch0) { in sun4i_tcon1_mode_set()
686 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon1_mode_set()
689 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon1_mode_set()
692 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon1_mode_set()
697 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon1_mode_set()
700 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon1_mode_set()
703 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val); in sun4i_tcon1_mode_set()
707 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon1_mode_set()
716 switch (encoder->encoder_type) { in sun4i_tcon_mode_set()
744 spin_lock_irqsave(&dev->event_lock, flags); in sun4i_tcon_finish_page_flip()
745 if (scrtc->event) { in sun4i_tcon_finish_page_flip()
746 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event); in sun4i_tcon_finish_page_flip()
747 drm_crtc_vblank_put(&scrtc->crtc); in sun4i_tcon_finish_page_flip()
748 scrtc->event = NULL; in sun4i_tcon_finish_page_flip()
750 spin_unlock_irqrestore(&dev->event_lock, flags); in sun4i_tcon_finish_page_flip()
756 struct drm_device *drm = tcon->drm; in sun4i_tcon_handler()
757 struct sun4i_crtc *scrtc = tcon->crtc; in sun4i_tcon_handler()
758 struct sunxi_engine *engine = scrtc->engine; in sun4i_tcon_handler()
761 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); in sun4i_tcon_handler()
768 drm_crtc_handle_vblank(&scrtc->crtc); in sun4i_tcon_handler()
772 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, in sun4i_tcon_handler()
778 if (engine->ops->vblank_quirk) in sun4i_tcon_handler()
779 engine->ops->vblank_quirk(engine); in sun4i_tcon_handler()
787 tcon->clk = devm_clk_get_enabled(dev, "ahb"); in sun4i_tcon_init_clocks()
788 if (IS_ERR(tcon->clk)) { in sun4i_tcon_init_clocks()
790 return PTR_ERR(tcon->clk); in sun4i_tcon_init_clocks()
793 if (tcon->quirks->has_channel_0) { in sun4i_tcon_init_clocks()
794 tcon->sclk0 = devm_clk_get_enabled(dev, "tcon-ch0"); in sun4i_tcon_init_clocks()
795 if (IS_ERR(tcon->sclk0)) { in sun4i_tcon_init_clocks()
797 return PTR_ERR(tcon->sclk0); in sun4i_tcon_init_clocks()
801 if (tcon->quirks->has_channel_1) { in sun4i_tcon_init_clocks()
802 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); in sun4i_tcon_init_clocks()
803 if (IS_ERR(tcon->sclk1)) { in sun4i_tcon_init_clocks()
805 return PTR_ERR(tcon->sclk1); in sun4i_tcon_init_clocks()
849 tcon->regs = devm_regmap_init_mmio(dev, regs, in sun4i_tcon_init_regmap()
851 if (IS_ERR(tcon->regs)) { in sun4i_tcon_init_regmap()
853 return PTR_ERR(tcon->regs); in sun4i_tcon_init_regmap()
857 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); in sun4i_tcon_init_regmap()
858 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); in sun4i_tcon_init_regmap()
859 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); in sun4i_tcon_init_regmap()
861 /* Disable IO lines and set them to tristate */ in sun4i_tcon_init_regmap()
862 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
863 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
874 * We can either identify backends from their compatible strings, which
877 * list of registered backends and compare the device node.
879 * As the structures now store engines instead of backends, here this
889 struct sunxi_engine *engine = ERR_PTR(-EINVAL); in sun4i_tcon_find_engine_traverse()
894 return ERR_PTR(-EINVAL); in sun4i_tcon_find_engine_traverse()
918 list_for_each_entry(engine, &drv->engine_list, list) in sun4i_tcon_find_engine_traverse()
919 if (remote == engine->node) in sun4i_tcon_find_engine_traverse()
933 reg -= 1; in sun4i_tcon_find_engine_traverse()
961 int ret = -EINVAL; in sun4i_tcon_of_get_id_from_port()
992 list_for_each_entry(engine, &drv->engine_list, list) in sun4i_tcon_get_engine_by_id()
993 if (engine->id == id) in sun4i_tcon_get_engine_by_id()
996 return ERR_PTR(-EINVAL); in sun4i_tcon_get_engine_by_id()
1004 remote = of_graph_get_remote_node(node, 0, -1); in sun4i_tcon_connected_to_tcon_top()
1024 list_for_each(pos, &drv->tcon_list) in sun4i_tcon_get_index()
1071 return ERR_PTR(-EINVAL); in sun4i_tcon_find_engine()
1082 * are represented by frontends/backends (DE1) or mixers (DE2), in sun4i_tcon_find_engine()
1085 * TCONs than engines (R40) or TCONs with non-consecutive ids. in sun4i_tcon_find_engine()
1113 struct sun4i_drv *drv = drm->dev_private; in sun4i_tcon_bind()
1121 engine = sun4i_tcon_find_engine(drv, dev->of_node); in sun4i_tcon_bind()
1124 return -EPROBE_DEFER; in sun4i_tcon_bind()
1129 return -ENOMEM; in sun4i_tcon_bind()
1131 tcon->drm = drm; in sun4i_tcon_bind()
1132 tcon->dev = dev; in sun4i_tcon_bind()
1133 tcon->id = engine->id; in sun4i_tcon_bind()
1134 tcon->quirks = of_device_get_match_data(dev); in sun4i_tcon_bind()
1136 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); in sun4i_tcon_bind()
1137 if (IS_ERR(tcon->lcd_rst)) { in sun4i_tcon_bind()
1139 return PTR_ERR(tcon->lcd_rst); in sun4i_tcon_bind()
1142 if (tcon->quirks->needs_edp_reset) { in sun4i_tcon_bind()
1157 ret = reset_control_reset(tcon->lcd_rst); in sun4i_tcon_bind()
1163 if (tcon->quirks->supports_lvds) { in sun4i_tcon_bind()
1171 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); in sun4i_tcon_bind()
1172 if (IS_ERR(tcon->lvds_rst)) { in sun4i_tcon_bind()
1174 return PTR_ERR(tcon->lvds_rst); in sun4i_tcon_bind()
1175 } else if (tcon->lvds_rst) { in sun4i_tcon_bind()
1177 reset_control_reset(tcon->lvds_rst); in sun4i_tcon_bind()
1189 if (tcon->quirks->has_lvds_alt) { in sun4i_tcon_bind()
1190 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); in sun4i_tcon_bind()
1191 if (IS_ERR(tcon->lvds_pll)) { in sun4i_tcon_bind()
1192 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { in sun4i_tcon_bind()
1196 return PTR_ERR(tcon->lvds_pll); in sun4i_tcon_bind()
1204 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { in sun4i_tcon_bind()
1227 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1241 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); in sun4i_tcon_bind()
1242 if (IS_ERR(tcon->crtc)) { in sun4i_tcon_bind()
1244 ret = PTR_ERR(tcon->crtc); in sun4i_tcon_bind()
1248 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1254 remote = of_graph_get_remote_node(dev->of_node, 1, 0); in sun4i_tcon_bind()
1255 if (of_device_is_compatible(remote, "panel-lvds")) in sun4i_tcon_bind()
1259 ret = -EINVAL; in sun4i_tcon_bind()
1268 if (tcon->quirks->needs_de_be_mux) { in sun4i_tcon_bind()
1270 * We assume there is no dynamic muxing of backends in sun4i_tcon_bind()
1275 * tied to the backends, this means, we will need to in sun4i_tcon_bind()
1279 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_bind()
1281 tcon->id); in sun4i_tcon_bind()
1282 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_bind()
1284 tcon->id); in sun4i_tcon_bind()
1287 list_add_tail(&tcon->list, &drv->tcon_list); in sun4i_tcon_bind()
1292 if (tcon->quirks->has_channel_0) in sun4i_tcon_bind()
1295 reset_control_assert(tcon->lcd_rst); in sun4i_tcon_bind()
1304 list_del(&tcon->list); in sun4i_tcon_unbind()
1305 if (tcon->quirks->has_channel_0) in sun4i_tcon_unbind()
1316 struct device_node *node = pdev->dev.of_node; in sun4i_tcon_probe()
1322 quirks = of_device_get_match_data(&pdev->dev); in sun4i_tcon_probe()
1325 if (quirks->has_channel_0) { in sun4i_tcon_probe()
1327 if (ret == -EPROBE_DEFER) in sun4i_tcon_probe()
1331 return component_add(&pdev->dev, &sun4i_tcon_ops); in sun4i_tcon_probe()
1336 component_del(&pdev->dev, &sun4i_tcon_ops); in sun4i_tcon_remove()
1343 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); in sun4i_a10_tcon_set_mux()
1347 return -EINVAL; in sun4i_a10_tcon_set_mux()
1349 switch (encoder->encoder_type) { in sun4i_a10_tcon_set_mux()
1355 return -EINVAL; in sun4i_a10_tcon_set_mux()
1358 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, in sun4i_a10_tcon_set_mux()
1359 0x3 << shift, tcon->id << shift); in sun4i_a10_tcon_set_mux()
1369 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) in sun5i_a13_tcon_set_mux()
1377 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); in sun5i_a13_tcon_set_mux()
1383 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); in sun6i_tcon_set_mux()
1387 return -EINVAL; in sun6i_tcon_set_mux()
1389 switch (encoder->encoder_type) { in sun6i_tcon_set_mux()
1396 return -EINVAL; in sun6i_tcon_set_mux()
1399 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, in sun6i_tcon_set_mux()
1400 0x3 << shift, tcon->id << shift); in sun6i_tcon_set_mux()
1414 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); in sun8i_r40_tcon_tv_set_mux()
1416 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1421 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); in sun8i_r40_tcon_tv_set_mux()
1423 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1428 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1431 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) { in sun8i_r40_tcon_tv_set_mux()
1432 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id); in sun8i_r40_tcon_tv_set_mux()
1434 put_device(&pdev->dev); in sun8i_r40_tcon_tv_set_mux()
1440 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); in sun8i_r40_tcon_tv_set_mux()
1442 put_device(&pdev->dev); in sun8i_r40_tcon_tv_set_mux()
1547 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1548 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1549 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1550 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1551 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1552 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks },
1553 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks },
1554 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1555 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1556 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1557 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1558 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1559 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1560 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1561 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1562 { .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
1563 { .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
1573 .name = "sun4i-tcon",
1579 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");