Lines Matching +full:background +full:- +full:layer
1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/media-bus-format.h>
46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
61 #define LAY_OFS (ldev->caps.layer_ofs)
65 #define LTDC_LCR 0x0004 /* Layer Count */
75 #define LTDC_BCCR 0x002C /* Background Color Configuration */
86 /* Layer register offsets */
87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
91 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
92 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
93 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */
94 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */
95 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */
96 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */
97 #define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */
98 #define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */
99 #define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */
100 #define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */
101 #define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */
102 #define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */
103 #define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */
104 #define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */
105 #define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */
106 #define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */
107 #define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */
108 #define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */
109 #define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */
110 #define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */
111 #define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */
129 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
130 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
131 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
132 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
141 #define GC1R_BCP BIT(22) /* Background Colour Programmable */
142 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */
153 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
154 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
161 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */
162 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
163 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
164 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
165 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
188 #define LXCR_LEN BIT(0) /* Layer ENable */
190 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
215 #define LXCR_C1R_YSPA BIT(1) /* Ycbcr 420 Semi-Planar Ability */
216 #define LXCR_C1R_YFPA BIT(2) /* Ycbcr 420 Full-Planar Ability */
225 #define YCM_SP 0x1 /* Semi-Planar 420 */
226 #define YCM_FP 0x2 /* Full-Planar 420 */
227 #define LxPCR_YCEN BIT(3) /* YCbCr-to-RGB Conversion Enable */
238 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
239 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
368 /* Layer register offsets */
489 return (struct ltdc_device *)crtc->dev->dev_private; in crtc_to_ltdc()
494 return (struct ltdc_device *)plane->dev->dev_private; in plane_to_ltdc()
553 u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE; in ltdc_set_flexible_pixel_format()
593 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs, in ltdc_set_flexible_pixel_format()
596 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs, in ltdc_set_flexible_pixel_format()
604 * All non-alpha color formats derived from native alpha color formats are
615 struct drm_plane_state *state = plane->state; in ltdc_set_ycbcr_config()
616 u32 lofs = plane->index * LAY_OFS; in ltdc_set_ycbcr_config()
649 if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) in ltdc_set_ycbcr_config()
655 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val); in ltdc_set_ycbcr_config()
661 struct drm_plane_state *state = plane->state; in ltdc_set_ycbcr_coeffs()
662 enum drm_color_encoding enc = state->color_encoding; in ltdc_set_ycbcr_coeffs()
663 enum drm_color_range ran = state->color_range; in ltdc_set_ycbcr_coeffs()
664 u32 lofs = plane->index * LAY_OFS; in ltdc_set_ycbcr_coeffs()
679 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, in ltdc_set_ycbcr_coeffs()
681 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, in ltdc_set_ycbcr_coeffs()
691 if (ldev->crc_skip_count < CRC_SKIP_FRAMES) { in ltdc_irq_crc_handle()
692 ldev->crc_skip_count++; in ltdc_irq_crc_handle()
697 ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc); in ltdc_irq_crc_handle()
708 struct ltdc_device *ldev = ddev->dev_private; in ltdc_irq_thread()
712 if (ldev->irq_status & ISR_LIF) { in ltdc_irq_thread()
716 if (ldev->crc_active) in ltdc_irq_thread()
720 mutex_lock(&ldev->err_lock); in ltdc_irq_thread()
721 if (ldev->irq_status & ISR_TERRIF) in ltdc_irq_thread()
722 ldev->transfer_err++; in ltdc_irq_thread()
723 if (ldev->irq_status & ISR_FUEIF) in ltdc_irq_thread()
724 ldev->fifo_err++; in ltdc_irq_thread()
725 if (ldev->irq_status & ISR_FUWIF) in ltdc_irq_thread()
726 ldev->fifo_warn++; in ltdc_irq_thread()
727 mutex_unlock(&ldev->err_lock); in ltdc_irq_thread()
735 struct ltdc_device *ldev = ddev->dev_private; in ltdc_irq()
742 ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR); in ltdc_irq()
743 writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR); in ltdc_irq()
759 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) in ltdc_crtc_update_clut()
762 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; in ltdc_crtc_update_clut()
765 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | in ltdc_crtc_update_clut()
766 (lut->blue >> 8) | (i << 24); in ltdc_crtc_update_clut()
767 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val); in ltdc_crtc_update_clut()
775 struct drm_device *ddev = crtc->dev; in ltdc_crtc_atomic_enable()
779 pm_runtime_get_sync(ddev->dev); in ltdc_crtc_atomic_enable()
781 /* Sets the background color value */ in ltdc_crtc_atomic_enable()
782 regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK); in ltdc_crtc_atomic_enable()
785 regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE); in ltdc_crtc_atomic_enable()
788 if (!ldev->caps.plane_reg_shadow) in ltdc_crtc_atomic_enable()
789 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); in ltdc_crtc_atomic_enable()
798 struct drm_device *ddev = crtc->dev; in ltdc_crtc_atomic_disable()
806 for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) in ltdc_crtc_atomic_disable()
807 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS, LXCR_MASK, 0); in ltdc_crtc_atomic_disable()
810 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_TERRIE); in ltdc_crtc_atomic_disable()
813 if (!ldev->caps.plane_reg_shadow) in ltdc_crtc_atomic_disable()
814 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR); in ltdc_crtc_atomic_disable()
816 pm_runtime_put_sync(ddev->dev); in ltdc_crtc_atomic_disable()
819 mutex_lock(&ldev->err_lock); in ltdc_crtc_atomic_disable()
820 ldev->transfer_err = 0; in ltdc_crtc_atomic_disable()
821 ldev->fifo_err = 0; in ltdc_crtc_atomic_disable()
822 ldev->fifo_warn = 0; in ltdc_crtc_atomic_disable()
823 mutex_unlock(&ldev->err_lock); in ltdc_crtc_atomic_disable()
833 int target = mode->clock * 1000; in ltdc_crtc_mode_valid()
834 int target_min = target - CLK_TOLERANCE_HZ; in ltdc_crtc_mode_valid()
838 result = clk_round_rate(ldev->pixel_clk, target); in ltdc_crtc_mode_valid()
843 if (result > ldev->caps.pad_max_freq_hz) in ltdc_crtc_mode_valid()
848 * - this is important for panels because panel clock tolerances are in ltdc_crtc_mode_valid()
851 * - the hdmi preferred mode will be accepted too, but userland will in ltdc_crtc_mode_valid()
854 if (mode->type & DRM_MODE_TYPE_PREFERRED) in ltdc_crtc_mode_valid()
872 int rate = mode->clock * 1000; in ltdc_crtc_mode_fixup()
874 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { in ltdc_crtc_mode_fixup()
879 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; in ltdc_crtc_mode_fixup()
882 mode->clock, adjusted_mode->clock); in ltdc_crtc_mode_fixup()
890 struct drm_device *ddev = crtc->dev; in ltdc_crtc_mode_set_nofb()
895 struct drm_display_mode *mode = &crtc->state->adjusted_mode; in ltdc_crtc_mode_set_nofb()
905 if (en_iter->crtc == crtc) { in ltdc_crtc_mode_set_nofb()
912 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node) in ltdc_crtc_mode_set_nofb()
913 if (br_iter->encoder == encoder) { in ltdc_crtc_mode_set_nofb()
921 if (connector->encoder == encoder) in ltdc_crtc_mode_set_nofb()
926 if (bridge && bridge->timings) { in ltdc_crtc_mode_set_nofb()
927 bus_flags = bridge->timings->input_bus_flags; in ltdc_crtc_mode_set_nofb()
929 bus_flags = connector->display_info.bus_flags; in ltdc_crtc_mode_set_nofb()
930 if (connector->display_info.num_bus_formats) in ltdc_crtc_mode_set_nofb()
931 bus_formats = connector->display_info.bus_formats[0]; in ltdc_crtc_mode_set_nofb()
934 if (!pm_runtime_active(ddev->dev)) { in ltdc_crtc_mode_set_nofb()
935 ret = pm_runtime_get_sync(ddev->dev); in ltdc_crtc_mode_set_nofb()
942 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); in ltdc_crtc_mode_set_nofb()
943 DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay); in ltdc_crtc_mode_set_nofb()
945 mode->hsync_start - mode->hdisplay, in ltdc_crtc_mode_set_nofb()
946 mode->htotal - mode->hsync_end, in ltdc_crtc_mode_set_nofb()
947 mode->hsync_end - mode->hsync_start, in ltdc_crtc_mode_set_nofb()
948 mode->vsync_start - mode->vdisplay, in ltdc_crtc_mode_set_nofb()
949 mode->vtotal - mode->vsync_end, in ltdc_crtc_mode_set_nofb()
950 mode->vsync_end - mode->vsync_start); in ltdc_crtc_mode_set_nofb()
953 hsync = mode->hsync_end - mode->hsync_start - 1; in ltdc_crtc_mode_set_nofb()
954 vsync = mode->vsync_end - mode->vsync_start - 1; in ltdc_crtc_mode_set_nofb()
955 accum_hbp = mode->htotal - mode->hsync_start - 1; in ltdc_crtc_mode_set_nofb()
956 accum_vbp = mode->vtotal - mode->vsync_start - 1; in ltdc_crtc_mode_set_nofb()
957 accum_act_w = accum_hbp + mode->hdisplay; in ltdc_crtc_mode_set_nofb()
958 accum_act_h = accum_vbp + mode->vdisplay; in ltdc_crtc_mode_set_nofb()
959 total_width = mode->htotal - 1; in ltdc_crtc_mode_set_nofb()
960 total_height = mode->vtotal - 1; in ltdc_crtc_mode_set_nofb()
965 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in ltdc_crtc_mode_set_nofb()
968 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in ltdc_crtc_mode_set_nofb()
977 regmap_update_bits(ldev->regmap, LTDC_GCR, in ltdc_crtc_mode_set_nofb()
982 regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); in ltdc_crtc_mode_set_nofb()
986 regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); in ltdc_crtc_mode_set_nofb()
990 regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); in ltdc_crtc_mode_set_nofb()
994 regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); in ltdc_crtc_mode_set_nofb()
996 regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1)); in ltdc_crtc_mode_set_nofb()
999 if (ldev->caps.ycbcr_output) { in ltdc_crtc_mode_set_nofb()
1006 /* ITU-R BT.601 */ in ltdc_crtc_mode_set_nofb()
1009 /* ITU-R BT.709 */ in ltdc_crtc_mode_set_nofb()
1015 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val); in ltdc_crtc_mode_set_nofb()
1019 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val); in ltdc_crtc_mode_set_nofb()
1023 regmap_write(ldev->regmap, LTDC_EDCR, 0); in ltdc_crtc_mode_set_nofb()
1033 struct drm_device *ddev = crtc->dev; in ltdc_crtc_atomic_flush()
1034 struct drm_pending_vblank_event *event = crtc->state->event; in ltdc_crtc_atomic_flush()
1041 if (!ldev->caps.plane_reg_shadow) in ltdc_crtc_atomic_flush()
1042 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); in ltdc_crtc_atomic_flush()
1045 crtc->state->event = NULL; in ltdc_crtc_atomic_flush()
1047 spin_lock_irq(&ddev->event_lock); in ltdc_crtc_atomic_flush()
1052 spin_unlock_irq(&ddev->event_lock); in ltdc_crtc_atomic_flush()
1062 struct drm_device *ddev = crtc->dev; in ltdc_crtc_get_scanout_position()
1063 struct ltdc_device *ldev = ddev->dev_private; in ltdc_crtc_get_scanout_position()
1073 * - line < vactive_start: vpos = line - vactive_start and will be in ltdc_crtc_get_scanout_position()
1075 * - vactive_start < line < vactive_end: vpos = line - vactive_start in ltdc_crtc_get_scanout_position()
1077 * - line > vactive_end: vpos = line - vtotal - vactive_start in ltdc_crtc_get_scanout_position()
1083 if (pm_runtime_active(ddev->dev)) { in ltdc_crtc_get_scanout_position()
1084 regmap_read(ldev->regmap, LTDC_CPSR, &line); in ltdc_crtc_get_scanout_position()
1086 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start); in ltdc_crtc_get_scanout_position()
1088 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end); in ltdc_crtc_get_scanout_position()
1090 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal); in ltdc_crtc_get_scanout_position()
1094 *vpos = line - vtotal - vactive_start; in ltdc_crtc_get_scanout_position()
1096 *vpos = line - vactive_start; in ltdc_crtc_get_scanout_position()
1122 struct drm_crtc_state *state = crtc->state; in ltdc_crtc_enable_vblank()
1126 if (state->enable) in ltdc_crtc_enable_vblank()
1127 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); in ltdc_crtc_enable_vblank()
1129 return -EPERM; in ltdc_crtc_enable_vblank()
1139 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); in ltdc_crtc_disable_vblank()
1150 return -ENODEV; in ltdc_crtc_set_crc_source()
1155 ldev->crc_active = true; in ltdc_crtc_set_crc_source()
1156 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); in ltdc_crtc_set_crc_source()
1158 ldev->crc_active = false; in ltdc_crtc_set_crc_source()
1159 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); in ltdc_crtc_set_crc_source()
1161 ret = -EINVAL; in ltdc_crtc_set_crc_source()
1164 ldev->crc_skip_count = 0; in ltdc_crtc_set_crc_source()
1174 return -ENODEV; in ltdc_crtc_verify_crc_source()
1178 source, crtc->name); in ltdc_crtc_verify_crc_source()
1179 return -EINVAL; in ltdc_crtc_verify_crc_source()
1189 struct drm_crtc *crtc = state->crtc; in ltdc_crtc_atomic_print_state()
1192 drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err); in ltdc_crtc_atomic_print_state()
1193 drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err); in ltdc_crtc_atomic_print_state()
1194 drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn); in ltdc_crtc_atomic_print_state()
1195 drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold); in ltdc_crtc_atomic_print_state()
1233 struct drm_framebuffer *fb = new_plane_state->fb; in ltdc_plane_atomic_check()
1242 src_w = new_plane_state->src_w >> 16; in ltdc_plane_atomic_check()
1243 src_h = new_plane_state->src_h >> 16; in ltdc_plane_atomic_check()
1246 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { in ltdc_plane_atomic_check()
1249 return -EINVAL; in ltdc_plane_atomic_check()
1261 struct drm_framebuffer *fb = newstate->fb; in ltdc_plane_atomic_update()
1262 u32 lofs = plane->index * LAY_OFS; in ltdc_plane_atomic_update()
1263 u32 x0 = newstate->crtc_x; in ltdc_plane_atomic_update()
1264 u32 x1 = newstate->crtc_x + newstate->crtc_w - 1; in ltdc_plane_atomic_update()
1265 u32 y0 = newstate->crtc_y; in ltdc_plane_atomic_update()
1266 u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; in ltdc_plane_atomic_update()
1272 if (!newstate->crtc || !fb) { in ltdc_plane_atomic_update()
1278 src_x = newstate->src_x >> 16; in ltdc_plane_atomic_update()
1279 src_y = newstate->src_y >> 16; in ltdc_plane_atomic_update()
1280 src_w = newstate->src_w >> 16; in ltdc_plane_atomic_update()
1281 src_h = newstate->src_h >> 16; in ltdc_plane_atomic_update()
1283 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", in ltdc_plane_atomic_update()
1284 plane->base.id, fb->base.id, in ltdc_plane_atomic_update()
1286 newstate->crtc_w, newstate->crtc_h, in ltdc_plane_atomic_update()
1287 newstate->crtc_x, newstate->crtc_y); in ltdc_plane_atomic_update()
1289 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); in ltdc_plane_atomic_update()
1296 regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs, in ltdc_plane_atomic_update()
1301 regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs, in ltdc_plane_atomic_update()
1305 pf = to_ltdc_pixelformat(fb->format->format); in ltdc_plane_atomic_update()
1307 if (ldev->caps.pix_fmt_hw[val] == pf) in ltdc_plane_atomic_update()
1311 if (ldev->caps.pix_fmt_flex && val == NB_PF) in ltdc_plane_atomic_update()
1316 (char *)&fb->format->format); in ltdc_plane_atomic_update()
1319 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); in ltdc_plane_atomic_update()
1322 val = newstate->alpha >> 8; in ltdc_plane_atomic_update()
1323 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); in ltdc_plane_atomic_update()
1327 if (!fb->format->has_alpha) in ltdc_plane_atomic_update()
1330 /* Manage hw-specific capabilities */ in ltdc_plane_atomic_update()
1331 if (ldev->caps.non_alpha_only_l1 && in ltdc_plane_atomic_update()
1332 plane->type != DRM_PLANE_TYPE_PRIMARY) in ltdc_plane_atomic_update()
1335 if (ldev->caps.dynamic_zorder) { in ltdc_plane_atomic_update()
1336 val |= (newstate->normalized_zpos << 16); in ltdc_plane_atomic_update()
1337 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, in ltdc_plane_atomic_update()
1340 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, in ltdc_plane_atomic_update()
1347 if (newstate->rotation & DRM_MODE_REFLECT_X) in ltdc_plane_atomic_update()
1348 paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1; in ltdc_plane_atomic_update()
1350 if (newstate->rotation & DRM_MODE_REFLECT_Y) in ltdc_plane_atomic_update()
1351 paddr += (fb->pitches[0] * (y1 - y0)); in ltdc_plane_atomic_update()
1354 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); in ltdc_plane_atomic_update()
1357 line_length = fb->format->cpp[0] * in ltdc_plane_atomic_update()
1358 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; in ltdc_plane_atomic_update()
1360 if (newstate->rotation & DRM_MODE_REFLECT_Y) in ltdc_plane_atomic_update()
1362 pitch_in_bytes = 0x10000 - fb->pitches[0]; in ltdc_plane_atomic_update()
1364 pitch_in_bytes = fb->pitches[0]; in ltdc_plane_atomic_update()
1367 regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); in ltdc_plane_atomic_update()
1370 line_number = y1 - y0 + 1; in ltdc_plane_atomic_update()
1371 regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); in ltdc_plane_atomic_update()
1373 if (ldev->caps.ycbcr_input) { in ltdc_plane_atomic_update()
1374 if (fb->format->is_yuv) { in ltdc_plane_atomic_update()
1375 switch (fb->format->format) { in ltdc_plane_atomic_update()
1381 if (newstate->rotation & DRM_MODE_REFLECT_X) in ltdc_plane_atomic_update()
1382 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1384 if (newstate->rotation & DRM_MODE_REFLECT_Y) in ltdc_plane_atomic_update()
1385 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1387 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); in ltdc_plane_atomic_update()
1394 if (newstate->rotation & DRM_MODE_REFLECT_X) { in ltdc_plane_atomic_update()
1395 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1396 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1399 if (newstate->rotation & DRM_MODE_REFLECT_Y) { in ltdc_plane_atomic_update()
1400 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1401 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1404 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); in ltdc_plane_atomic_update()
1405 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); in ltdc_plane_atomic_update()
1412 if (newstate->rotation & DRM_MODE_REFLECT_X) { in ltdc_plane_atomic_update()
1413 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1414 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1417 if (newstate->rotation & DRM_MODE_REFLECT_Y) { in ltdc_plane_atomic_update()
1418 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1419 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1422 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); in ltdc_plane_atomic_update()
1423 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); in ltdc_plane_atomic_update()
1431 if (fb->format->num_planes > 1) { in ltdc_plane_atomic_update()
1432 if (newstate->rotation & DRM_MODE_REFLECT_Y) in ltdc_plane_atomic_update()
1437 pitch_in_bytes = 0x10000 - fb->pitches[1]; in ltdc_plane_atomic_update()
1439 pitch_in_bytes = fb->pitches[1]; in ltdc_plane_atomic_update()
1441 line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) + in ltdc_plane_atomic_update()
1442 (ldev->caps.bus_width >> 3) - 1; in ltdc_plane_atomic_update()
1446 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); in ltdc_plane_atomic_update()
1450 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); in ltdc_plane_atomic_update()
1457 ltdc_set_ycbcr_config(plane, fb->format->format); in ltdc_plane_atomic_update()
1460 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0); in ltdc_plane_atomic_update()
1464 /* Enable layer and CLUT if needed */ in ltdc_plane_atomic_update()
1465 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; in ltdc_plane_atomic_update()
1469 if (newstate->rotation & DRM_MODE_REFLECT_X) in ltdc_plane_atomic_update()
1472 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, val); in ltdc_plane_atomic_update()
1475 if (ldev->caps.plane_reg_shadow) in ltdc_plane_atomic_update()
1476 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, in ltdc_plane_atomic_update()
1479 ldev->plane_fpsi[plane->index].counter++; in ltdc_plane_atomic_update()
1481 mutex_lock(&ldev->err_lock); in ltdc_plane_atomic_update()
1482 if (ldev->transfer_err) { in ltdc_plane_atomic_update()
1483 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err); in ltdc_plane_atomic_update()
1484 ldev->transfer_err = 0; in ltdc_plane_atomic_update()
1487 if (ldev->caps.fifo_threshold) { in ltdc_plane_atomic_update()
1488 if (ldev->fifo_err) { in ltdc_plane_atomic_update()
1490 ldev->fifo_err = 0; in ltdc_plane_atomic_update()
1493 if (ldev->fifo_warn >= ldev->fifo_threshold) { in ltdc_plane_atomic_update()
1495 ldev->fifo_warn = 0; in ltdc_plane_atomic_update()
1498 mutex_unlock(&ldev->err_lock); in ltdc_plane_atomic_update()
1507 u32 lofs = plane->index * LAY_OFS; in ltdc_plane_atomic_disable()
1509 /* Disable layer */ in ltdc_plane_atomic_disable()
1510 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_MASK, 0); in ltdc_plane_atomic_disable()
1512 /* Reset the layer transparency to hide any related background color */ in ltdc_plane_atomic_disable()
1513 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, 0x00); in ltdc_plane_atomic_disable()
1516 if (ldev->caps.plane_reg_shadow) in ltdc_plane_atomic_disable()
1517 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, in ltdc_plane_atomic_disable()
1521 oldstate->crtc->base.id, plane->base.id); in ltdc_plane_atomic_disable()
1527 struct drm_plane *plane = state->plane; in ltdc_plane_atomic_print_state()
1529 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; in ltdc_plane_atomic_print_state()
1534 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); in ltdc_plane_atomic_print_state()
1537 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); in ltdc_plane_atomic_print_state()
1539 fpsi->last_timestamp = now; in ltdc_plane_atomic_print_state()
1540 fpsi->counter = 0; in ltdc_plane_atomic_print_state()
1563 struct ltdc_device *ldev = ddev->dev_private; in ltdc_plane_create()
1564 struct device *dev = ddev->dev; in ltdc_plane_create()
1574 formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb + in ltdc_plane_create()
1582 for (i = 0; i < ldev->caps.pix_fmt_nb; i++) { in ltdc_plane_create()
1583 drm_fmt = ldev->caps.pix_fmt_drm[i]; in ltdc_plane_create()
1585 /* Manage hw-specific capabilities */ in ltdc_plane_create()
1586 if (ldev->caps.non_alpha_only_l1) in ltdc_plane_create()
1587 /* XR24 & RX24 like formats supported only on primary layer */ in ltdc_plane_create()
1595 if (ldev->caps.ycbcr_input) { in ltdc_plane_create()
1596 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val); in ltdc_plane_create()
1620 if (ldev->caps.ycbcr_input) { in ltdc_plane_create()
1635 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); in ltdc_plane_create()
1642 struct ltdc_device *ldev = ddev->dev_private; in ltdc_crtc_init()
1651 return -EINVAL; in ltdc_crtc_init()
1654 if (ldev->caps.dynamic_zorder) in ltdc_crtc_init()
1655 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1); in ltdc_crtc_init()
1659 if (ldev->caps.plane_rotation) in ltdc_crtc_init()
1664 if (ldev->caps.crc) in ltdc_crtc_init()
1680 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); in ltdc_crtc_init()
1682 /* Add planes. Note : the first layer is used by primary plane */ in ltdc_crtc_init()
1683 for (i = 1; i < ldev->caps.nb_layers; i++) { in ltdc_crtc_init()
1687 return -ENOMEM; in ltdc_crtc_init()
1689 if (ldev->caps.dynamic_zorder) in ltdc_crtc_init()
1690 drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1); in ltdc_crtc_init()
1694 if (ldev->caps.plane_rotation) in ltdc_crtc_init()
1704 struct drm_device *ddev = encoder->dev; in ltdc_encoder_disable()
1705 struct ltdc_device *ldev = ddev->dev_private; in ltdc_encoder_disable()
1710 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); in ltdc_encoder_disable()
1713 pinctrl_pm_select_sleep_state(ddev->dev); in ltdc_encoder_disable()
1718 struct drm_device *ddev = encoder->dev; in ltdc_encoder_enable()
1719 struct ltdc_device *ldev = ddev->dev_private; in ltdc_encoder_enable()
1724 if (ldev->caps.fifo_threshold) in ltdc_encoder_enable()
1725 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold); in ltdc_encoder_enable()
1728 regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); in ltdc_encoder_enable()
1735 struct drm_device *ddev = encoder->dev; in ltdc_encoder_mode_set()
1744 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) in ltdc_encoder_mode_set()
1745 pinctrl_pm_select_default_state(ddev->dev); in ltdc_encoder_mode_set()
1764 encoder->possible_crtcs = CRTC_MASK; in ltdc_encoder_init()
1765 encoder->possible_clones = 0; /* No cloning support */ in ltdc_encoder_init()
1773 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); in ltdc_encoder_init()
1780 struct ltdc_device *ldev = ddev->dev_private; in ltdc_get_caps()
1784 * at least 1 layer must be managed & the number of layers in ltdc_get_caps()
1787 regmap_read(ldev->regmap, LTDC_LCR, &lcr); in ltdc_get_caps()
1789 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); in ltdc_get_caps()
1792 regmap_read(ldev->regmap, LTDC_GC2R, &gc2r); in ltdc_get_caps()
1794 ldev->caps.bus_width = 8 << bus_width_log2; in ltdc_get_caps()
1795 regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); in ltdc_get_caps()
1797 switch (ldev->caps.hw_version) { in ltdc_get_caps()
1800 ldev->caps.layer_ofs = LAY_OFS_0; in ltdc_get_caps()
1801 ldev->caps.layer_regs = ltdc_layer_regs_a0; in ltdc_get_caps()
1802 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; in ltdc_get_caps()
1803 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0; in ltdc_get_caps()
1804 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0); in ltdc_get_caps()
1805 ldev->caps.pix_fmt_flex = false; in ltdc_get_caps()
1807 * Hw older versions support non-alpha color formats derived in ltdc_get_caps()
1808 * from native alpha color formats only on the primary layer. in ltdc_get_caps()
1810 * on 2nd layer but XR24 (derived color format from AR24) in ltdc_get_caps()
1811 * does not work on 2nd layer. in ltdc_get_caps()
1813 ldev->caps.non_alpha_only_l1 = true; in ltdc_get_caps()
1814 ldev->caps.pad_max_freq_hz = 90000000; in ltdc_get_caps()
1815 if (ldev->caps.hw_version == HWVER_10200) in ltdc_get_caps()
1816 ldev->caps.pad_max_freq_hz = 65000000; in ltdc_get_caps()
1817 ldev->caps.nb_irq = 2; in ltdc_get_caps()
1818 ldev->caps.ycbcr_input = false; in ltdc_get_caps()
1819 ldev->caps.ycbcr_output = false; in ltdc_get_caps()
1820 ldev->caps.plane_reg_shadow = false; in ltdc_get_caps()
1821 ldev->caps.crc = false; in ltdc_get_caps()
1822 ldev->caps.dynamic_zorder = false; in ltdc_get_caps()
1823 ldev->caps.plane_rotation = false; in ltdc_get_caps()
1824 ldev->caps.fifo_threshold = false; in ltdc_get_caps()
1827 ldev->caps.layer_ofs = LAY_OFS_0; in ltdc_get_caps()
1828 ldev->caps.layer_regs = ltdc_layer_regs_a1; in ltdc_get_caps()
1829 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; in ltdc_get_caps()
1830 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1; in ltdc_get_caps()
1831 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1); in ltdc_get_caps()
1832 ldev->caps.pix_fmt_flex = false; in ltdc_get_caps()
1833 ldev->caps.non_alpha_only_l1 = false; in ltdc_get_caps()
1834 ldev->caps.pad_max_freq_hz = 150000000; in ltdc_get_caps()
1835 ldev->caps.nb_irq = 4; in ltdc_get_caps()
1836 ldev->caps.ycbcr_input = false; in ltdc_get_caps()
1837 ldev->caps.ycbcr_output = false; in ltdc_get_caps()
1838 ldev->caps.plane_reg_shadow = false; in ltdc_get_caps()
1839 ldev->caps.crc = false; in ltdc_get_caps()
1840 ldev->caps.dynamic_zorder = false; in ltdc_get_caps()
1841 ldev->caps.plane_rotation = false; in ltdc_get_caps()
1842 ldev->caps.fifo_threshold = false; in ltdc_get_caps()
1845 ldev->caps.layer_ofs = LAY_OFS_1; in ltdc_get_caps()
1846 ldev->caps.layer_regs = ltdc_layer_regs_a2; in ltdc_get_caps()
1847 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2; in ltdc_get_caps()
1848 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2; in ltdc_get_caps()
1849 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2); in ltdc_get_caps()
1850 ldev->caps.pix_fmt_flex = true; in ltdc_get_caps()
1851 ldev->caps.non_alpha_only_l1 = false; in ltdc_get_caps()
1852 ldev->caps.pad_max_freq_hz = 90000000; in ltdc_get_caps()
1853 ldev->caps.nb_irq = 2; in ltdc_get_caps()
1854 ldev->caps.ycbcr_input = true; in ltdc_get_caps()
1855 ldev->caps.ycbcr_output = true; in ltdc_get_caps()
1856 ldev->caps.plane_reg_shadow = true; in ltdc_get_caps()
1857 ldev->caps.crc = true; in ltdc_get_caps()
1858 ldev->caps.dynamic_zorder = true; in ltdc_get_caps()
1859 ldev->caps.plane_rotation = true; in ltdc_get_caps()
1860 ldev->caps.fifo_threshold = true; in ltdc_get_caps()
1863 return -ENODEV; in ltdc_get_caps()
1871 struct ltdc_device *ldev = ddev->dev_private; in ltdc_suspend()
1874 clk_disable_unprepare(ldev->pixel_clk); in ltdc_suspend()
1879 struct ltdc_device *ldev = ddev->dev_private; in ltdc_resume()
1884 ret = clk_prepare_enable(ldev->pixel_clk); in ltdc_resume()
1895 struct platform_device *pdev = to_platform_device(ddev->dev); in ltdc_load()
1896 struct ltdc_device *ldev = ddev->dev_private; in ltdc_load()
1897 struct device *dev = ddev->dev; in ltdc_load()
1898 struct device_node *np = dev->of_node; in ltdc_load()
1905 int ret = -ENODEV; in ltdc_load()
1912 return -ENODEV; in ltdc_load()
1914 ldev->pixel_clk = devm_clk_get(dev, "lcd"); in ltdc_load()
1915 if (IS_ERR(ldev->pixel_clk)) { in ltdc_load()
1916 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) in ltdc_load()
1918 return PTR_ERR(ldev->pixel_clk); in ltdc_load()
1921 if (clk_prepare_enable(ldev->pixel_clk)) { in ltdc_load()
1923 return -ENODEV; in ltdc_load()
1931 * If at least one endpoint is -ENODEV, continue probing, in ltdc_load()
1933 * (ie -EPROBE_DEFER) then stop probing. in ltdc_load()
1935 if (ret == -ENODEV) in ltdc_load()
1943 DRM_ERROR("panel-bridge endpoint %d\n", i); in ltdc_load()
1952 if (ret != -EPROBE_DEFER) in ltdc_load()
1961 mutex_init(&ldev->err_lock); in ltdc_load()
1970 ldev->regs = devm_ioremap_resource(dev, res); in ltdc_load()
1971 if (IS_ERR(ldev->regs)) { in ltdc_load()
1973 ret = PTR_ERR(ldev->regs); in ltdc_load()
1977 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg); in ltdc_load()
1978 if (IS_ERR(ldev->regmap)) { in ltdc_load()
1980 ret = PTR_ERR(ldev->regmap); in ltdc_load()
1987 ldev->caps.hw_version); in ltdc_load()
1992 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_MASK); in ltdc_load()
1994 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); in ltdc_load()
1997 ldev->transfer_err = 0; in ltdc_load()
1998 ldev->fifo_err = 0; in ltdc_load()
1999 ldev->fifo_warn = 0; in ltdc_load()
2000 ldev->fifo_threshold = FUT_DFT; in ltdc_load()
2002 for (i = 0; i < ldev->caps.nb_irq; i++) { in ltdc_load()
2021 ret = -ENOMEM; in ltdc_load()
2037 clk_disable_unprepare(ldev->pixel_clk); in ltdc_load()
2039 pinctrl_pm_select_sleep_state(ddev->dev); in ltdc_load()
2041 pm_runtime_enable(ddev->dev); in ltdc_load()
2045 clk_disable_unprepare(ldev->pixel_clk); in ltdc_load()
2054 pm_runtime_disable(ddev->dev); in ltdc_unload()