Lines Matching +full:pll +full:- +full:out
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
42 #define WISR_PLLLS BIT(8) /* PLL Lock Status */
49 #define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */
50 #define WRPCR_PLLEN BIT(0) /* PLL ENable */
51 #define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */
52 #define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */
53 #define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */
76 /* Sleep & timeout for regulator on/off, pll lock/unlock & fifo empty */
96 writel(val, dsi->base + reg);
101 return readl(dsi->base + reg);
157 return -EINVAL;
159 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;
160 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;
185 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -
188 delta = -delta;
213 /* Disable the DSI PLL */
230 ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_RRS,
235 /* Enable the DSI PLL & wait for its lock */
237 ret = readl_poll_timeout_atomic(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
240 DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
271 /* Get the adjusted pll out value */
286 pll_in_khz = (unsigned int)(req->best_parent_rate / 1000);
288 /* Compute best pll parameters */
293 ret = dsi_pll_get_params(dsi, pll_in_khz, req->rate / 1000,
298 /* Get the adjusted pll out value */
301 req->rate = pll_out_khz * 1000;
318 /* Compute best pll parameters */
327 /* Get the adjusted pll out value */
330 /* Set the PLL division factors */
332 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));
334 /* Compute uix4 & set the bit period in high-speed mode */
347 of_clk_del_provider(dsi->dev->of_node);
348 clk_hw_unregister(&dsi->txbyte_clk);
370 struct device_node *node = dev->of_node;
375 dsi->txbyte_clk.init = &cdata_init;
377 ret = clk_hw_register(dev, &dsi->txbyte_clk);
382 &dsi->txbyte_clk);
384 clk_hw_unregister(&dsi->txbyte_clk);
394 ret = clk_prepare_enable(dsi->txbyte_clk.clk);
414 clk_disable_unprepare(dsi->txbyte_clk.clk);
429 pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);
431 /* Compute requested pll out */
433 pll_out_khz = mode->clock * bpp / lanes;
435 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */
439 if (pll_out_khz > dsi->lane_max_kbps) {
440 pll_out_khz = dsi->lane_max_kbps;
443 if (pll_out_khz < dsi->lane_min_kbps) {
444 pll_out_khz = dsi->lane_min_kbps;
448 ret = clk_set_rate((dsi->txbyte_clk.clk), pll_out_khz * 1000);
450 DRM_DEBUG_DRIVER("ERROR Could not set rate of %d to %s clk->name",
451 pll_out_khz, clk_hw_get_name(&dsi->txbyte_clk));
481 timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps);
482 timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);
483 timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps);
484 timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);
504 /* Compute requested pll out */
505 pll_out_khz = mode->clock * bpp / lanes;
507 if (pll_out_khz > dsi->lane_max_kbps)
511 /* Add 20% to pll out to be higher than pixel bw */
514 if (pll_out_khz < dsi->lane_min_kbps)
518 /* Compute best pll parameters */
522 pll_in_khz = clk_get_rate(dsi->pllref_clk) / 1000;
534 /* Get the adjusted pll out value */
538 target_px_clock_hz = mode->clock * 1000;
543 if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ ||
550 hfp = mode->hsync_start - mode->hdisplay;
551 hsync = mode->hsync_end - mode->hsync_start;
552 hbp = mode->htotal - mode->hsync_end;
562 hbp -= dsi_short_packet_size_px;
565 hbp += hsync - dsi_short_packet_size_px;
573 * In non-burst mode DSI has to enter in LP during HFP
601 { .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
608 struct device *dev = &pdev->dev;
615 return -ENOMEM;
617 dsi->base = devm_platform_ioremap_resource(pdev, 0);
618 if (IS_ERR(dsi->base)) {
619 ret = PTR_ERR(dsi->base);
624 dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi");
625 if (IS_ERR(dsi->vdd_supply)) {
626 ret = PTR_ERR(dsi->vdd_supply);
631 ret = regulator_enable(dsi->vdd_supply);
637 dsi->pllref_clk = devm_clk_get(dev, "ref");
638 if (IS_ERR(dsi->pllref_clk)) {
639 ret = PTR_ERR(dsi->pllref_clk);
640 dev_err_probe(dev, ret, "Unable to get pll reference clock\n");
644 ret = clk_prepare_enable(dsi->pllref_clk);
650 dsi->pclk = devm_clk_get(dev, "pclk");
651 if (IS_ERR(dsi->pclk)) {
652 ret = PTR_ERR(dsi->pclk);
657 ret = clk_prepare_enable(dsi->pclk);
663 dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
664 clk_disable_unprepare(dsi->pclk);
666 if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
667 ret = -ENODEV;
673 dsi->lane_min_kbps = LANE_MIN_KBPS;
674 dsi->lane_max_kbps = LANE_MAX_KBPS;
675 if (dsi->hw_version == HWVER_131) {
676 dsi->lane_min_kbps *= 2;
677 dsi->lane_max_kbps *= 2;
680 dsi->pdata = *pdata;
681 dsi->pdata.base = dsi->base;
682 dsi->pdata.priv_data = dsi;
684 dsi->pdata.max_data_lanes = 2;
685 dsi->pdata.phy_ops = &dw_mipi_dsi_stm_phy_ops;
689 dsi->dsi = dw_mipi_dsi_probe(pdev, &dsi->pdata);
690 if (IS_ERR(dsi->dsi)) {
691 ret = PTR_ERR(dsi->dsi);
700 ret = clk_prepare_enable(dsi->pclk);
709 clk_disable_unprepare(dsi->pclk);
713 clk_disable_unprepare(dsi->pclk);
718 clk_disable_unprepare(dsi->pllref_clk);
720 regulator_disable(dsi->vdd_supply);
729 dw_mipi_dsi_remove(dsi->dsi);
730 clk_disable_unprepare(dsi->pllref_clk);
732 regulator_disable(dsi->vdd_supply);
741 clk_disable_unprepare(dsi->pllref_clk);
742 clk_disable_unprepare(dsi->pclk);
743 regulator_disable(dsi->vdd_supply);
755 ret = regulator_enable(dsi->vdd_supply);
761 ret = clk_prepare_enable(dsi->pclk);
763 regulator_disable(dsi->vdd_supply);
768 ret = clk_prepare_enable(dsi->pllref_clk);
770 clk_disable_unprepare(dsi->pclk);
771 regulator_disable(dsi->vdd_supply);
791 .name = "stm32-display-dsi",