Lines Matching refs:dvo
76 * @regs: dvo registers
77 * @clk_pix: pixel clock for dvo
78 * @clk: clock for dvo
79 * @clk_main_parent: dvo parent clock if main path used
80 * @clk_aux_parent: dvo parent clock if aux path used
82 * @panel: reference to the panel connected to the dvo
83 * @enabled: true if dvo is enabled else false
106 struct sti_dvo *dvo;
113 static int dvo_awg_generate_code(struct sti_dvo *dvo, u8 *ram_size, u32 *ram_code)
115 struct drm_display_mode *mode = &dvo->mode;
116 struct dvo_config *config = dvo->config;
145 * @dvo: pointer to DVO structure
149 static void dvo_awg_configure(struct sti_dvo *dvo, u32 *awg_ram_code, int nb)
157 dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4);
159 writel(0, dvo->regs + DVO_DIGSYNC_INSTR_I + i * 4);
161 writel(DVO_AWG_CTRL_EN, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
165 readl(dvo->regs + reg))
183 struct sti_dvo *dvo = (struct sti_dvo *)node->info_ent->data;
185 seq_printf(s, "DVO: (vaddr = 0x%p)", dvo->regs);
191 dvo_dbg_awg_microcode(s, dvo->regs + DVO_DIGSYNC_INSTR_I);
197 { "dvo", dvo_dbg_show, 0, NULL },
200 static void dvo_debugfs_init(struct sti_dvo *dvo, struct drm_minor *minor)
205 dvo_debugfs_files[i].data = dvo;
214 struct sti_dvo *dvo = bridge->driver_private;
216 if (!dvo->enabled)
221 if (dvo->config->awg_fwgen_fct)
222 writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
224 writel(0x00000000, dvo->regs + DVO_DOF_CFG);
226 drm_panel_disable(dvo->panel);
228 /* Disable/unprepare dvo clock */
229 clk_disable_unprepare(dvo->clk_pix);
230 clk_disable_unprepare(dvo->clk);
232 dvo->enabled = false;
237 struct sti_dvo *dvo = bridge->driver_private;
238 struct dvo_config *config = dvo->config;
243 if (dvo->enabled)
247 writel(0x00000000, dvo->regs + DVO_DOF_CFG);
248 writel(0x00000000, dvo->regs + DVO_AWG_DIGSYNC_CTRL);
254 if (!dvo_awg_generate_code(dvo, &nb_instr, awg_ram_code))
255 dvo_awg_configure(dvo, awg_ram_code, nb_instr);
261 if (clk_prepare_enable(dvo->clk_pix))
263 if (clk_prepare_enable(dvo->clk))
264 DRM_ERROR("Failed to prepare/enable dvo clk\n");
266 drm_panel_enable(dvo->panel);
269 writel(config->lowbyte, dvo->regs + DVO_LUT_PROG_LOW);
270 writel(config->midbyte, dvo->regs + DVO_LUT_PROG_MID);
271 writel(config->highbyte, dvo->regs + DVO_LUT_PROG_HIGH);
275 writel(val, dvo->regs + DVO_DOF_CFG);
277 dvo->enabled = true;
284 struct sti_dvo *dvo = bridge->driver_private;
285 struct sti_mixer *mixer = to_sti_mixer(dvo->encoder->crtc);
292 drm_mode_copy(&dvo->mode, mode);
294 /* According to the path used (main or aux), the dvo clocks should
297 clkp = dvo->clk_main_parent;
299 clkp = dvo->clk_aux_parent;
302 clk_set_parent(dvo->clk_pix, clkp);
303 clk_set_parent(dvo->clk, clkp);
307 ret = clk_set_rate(dvo->clk_pix, rate);
313 ret = clk_set_rate(dvo->clk, rate);
315 DRM_ERROR("Cannot set rate (%dHz) for dvo clk\n", rate);
320 dvo->config = &rgb_24bit_de_cfg;
340 struct sti_dvo *dvo = dvo_connector->dvo;
342 if (dvo->panel)
343 return drm_panel_get_modes(dvo->panel, connector);
360 struct sti_dvo *dvo = dvo_connector->dvo;
362 result = clk_round_rate(dvo->clk_pix, target);
368 DRM_DEBUG_DRIVER("dvo pixclk=%d not supported\n", target);
386 struct sti_dvo *dvo = dvo_connector->dvo;
390 if (!dvo->panel) {
391 dvo->panel = of_drm_find_panel(dvo->panel_node);
392 if (IS_ERR(dvo->panel))
393 dvo->panel = NULL;
396 if (dvo->panel)
406 struct sti_dvo *dvo = dvo_connector->dvo;
408 dvo_debugfs_init(dvo, dvo->drm_dev->primary);
437 struct sti_dvo *dvo = dev_get_drvdata(dev);
445 dvo->drm_dev = drm_dev;
455 connector->dvo = dvo;
457 dvo->bridge.driver_private = dvo;
458 dvo->bridge.of_node = dvo->dev.of_node;
459 drm_bridge_add(&dvo->bridge);
461 err = drm_bridge_attach(encoder, &dvo->bridge, NULL, 0);
466 dvo->encoder = encoder;
486 drm_bridge_remove(&dvo->bridge);
493 struct sti_dvo *dvo = dev_get_drvdata(dev);
495 drm_bridge_remove(&dvo->bridge);
506 struct sti_dvo *dvo;
511 dvo = devm_drm_bridge_alloc(dev, struct sti_dvo, bridge, &sti_dvo_bridge_funcs);
512 if (IS_ERR(dvo)) {
514 return PTR_ERR(dvo);
517 dvo->dev = pdev->dev;
518 dvo->regs = devm_platform_ioremap_resource_byname(pdev, "dvo-reg");
519 if (IS_ERR(dvo->regs))
520 return PTR_ERR(dvo->regs);
522 dvo->clk_pix = devm_clk_get(dev, "dvo_pix");
523 if (IS_ERR(dvo->clk_pix)) {
525 return PTR_ERR(dvo->clk_pix);
528 dvo->clk = devm_clk_get(dev, "dvo");
529 if (IS_ERR(dvo->clk)) {
530 DRM_ERROR("Cannot get dvo clock\n");
531 return PTR_ERR(dvo->clk);
534 dvo->clk_main_parent = devm_clk_get(dev, "main_parent");
535 if (IS_ERR(dvo->clk_main_parent)) {
537 dvo->clk_main_parent = NULL;
540 dvo->clk_aux_parent = devm_clk_get(dev, "aux_parent");
541 if (IS_ERR(dvo->clk_aux_parent)) {
543 dvo->clk_aux_parent = NULL;
546 dvo->panel_node = of_parse_phandle(np, "sti,panel", 0);
547 if (!dvo->panel_node)
548 DRM_ERROR("No panel associated to the dvo output\n");
549 of_node_put(dvo->panel_node);
551 platform_set_drvdata(pdev, dvo);
562 { .compatible = "st,stih407-dvo", },
569 .name = "sti-dvo",