Lines Matching +full:non +full:- +full:linear
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andy Yan <andy.yan@rock-chips.com>
68 DRM_FORMAT_YUV420_8BIT, /* yuv420_8bit non-Linear mode only */
69 DRM_FORMAT_YUV420_10BIT, /* yuv420_10bit non-Linear mode only */
70 DRM_FORMAT_YUYV, /* yuv422_8bit non-Linear mode only*/
71 DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */
76 * RGB: linear mode and afbc
77 * YUV: linear mode and rfbc
78 * rfbc is a rockchip defined non-linear mode, produced by
94 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
95 DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
96 DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
97 DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
98 DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
99 DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
100 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
101 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
102 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
114 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
115 DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
116 DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
117 DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
118 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
119 DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
120 DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
121 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
122 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
123 DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */
124 DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */
125 DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */
126 DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */
138 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
139 DRM_FORMAT_NV21, /* yuv420_8bit linear mode, 2 plane */
140 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
141 DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
142 DRM_FORMAT_NV61, /* yuv422_8bit linear mode, 2 plane */
143 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
144 DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
145 DRM_FORMAT_NV42, /* yuv444_8bit linear mode, 2 plane */
146 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
147 DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */
148 DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */
171 DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */
172 DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */
173 DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */
174 DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */
175 DRM_FORMAT_NV20, /* yuv422_10bit linear mode, 2 plane, no padding */
176 DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */
177 DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */
178 DRM_FORMAT_NV30, /* yuv444_10bit linear mode, 2 plane, no padding */
179 DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */
180 DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */
181 DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */
182 DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */
183 DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */
583 * Every esmart win and smart win support 4 Multi-region.
589 * * nearest-neighbor/bilinear/bicubic for scale up
590 * * nearest-neighbor/bilinear/average for scale down
593 * @TODO describe the wind like cpu-map dt nodes;
597 .name = "Smart0-win0",
612 .name = "Smart1-win0",
626 .name = "Esmart1-win0",
640 .name = "Esmart0-win0",
654 .name = "Cluster0-win0",
670 .name = "Cluster1-win0",
807 * Every esmart win support 4 Multi-region.
819 * * nearest-neighbor/bilinear/multi-phase filter for scale up
820 * * nearest-neighbor/bilinear/multi-phase filter for scale down
827 * * nearest-neighbor/bilinear/bicubic for scale up
828 * * nearest-neighbor/bilinear for scale down
854 .name = "Cluster0-win0",
871 .name = "Cluster1-win0",
888 .name = "Esmart0-win0",
904 .name = "Esmart1-win0",
920 .name = "Esmart2-win0",
936 .name = "Esmart3-win0",
1096 * Every esmart win and smart win support 4 Multi-region.
1102 * * nearest-neighbor/bilinear/bicubic for scale up
1103 * * nearest-neighbor/bilinear/average for scale down
1122 .name = "Cluster0-win0",
1141 .name = "Cluster1-win0",
1160 .name = "Cluster2-win0",
1179 .name = "Cluster3-win0",
1198 .name = "Esmart0-win0",
1215 .name = "Esmart1-win0",
1232 .name = "Esmart2-win0",
1249 .name = "Esmart3-win0",
1373 struct vop2 *vop2 = vp->vop2;
1374 struct drm_crtc *crtc = &vp->crtc;
1384 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id);
1388 regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1390 regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1395 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
1402 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
1409 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id);
1416 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1423 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id);
1430 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id);
1435 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1444 return crtc->state->adjusted_mode.crtc_clock * 1000LL;
1449 struct vop2 *vop2 = vp->vop2;
1450 struct drm_crtc *crtc = &vp->crtc;
1451 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1452 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1453 u8 port_pix_rate = vp->data->pixel_rate;
1458 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420 || adjusted_mode->crtc_clock > 600000)
1463 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1464 dclk_core_rate = adjusted_mode->crtc_clock / 2;
1466 dclk_core_rate = adjusted_mode->crtc_clock / port_pix_rate;
1468 dclk_in_rate = adjusted_mode->crtc_clock / dclk_div;
1477 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_YUV420) {
1502 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1513 ctrl |= FIELD_PREP(RK3576_DSP_IF_MUX, vp->id);
1551 struct vop2 *vop2 = vp->vop2;
1552 struct drm_crtc *crtc = &vp->crtc;
1553 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1554 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1555 int output_mode = vcstate->output_mode;
1556 unsigned long v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */
1601 drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld Hz\n",
1618 drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld Hz\n",
1637 drm_dbg(vop2->drm, "dclk: %ld, pixclk_div: %d, dclk_div: %d\n",
1671 struct vop2 *vop2 = vp->vop2;
1696 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id);
1698 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1));
1699 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5));
1708 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id);
1710 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 4, 4));
1711 regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 8, 7));
1720 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id);
1721 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 0, 0));
1730 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id);
1731 regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 3, 3));
1737 val = rk3588_get_mipi_port_mux(vp->id);
1745 val = rk3588_get_mipi_port_mux(vp->id);
1752 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP0_MUX, vp->id);
1759 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP1_MUX, vp->id);
1764 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1786 int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1;
1787 int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1;
1788 int src_color_mode = alpha_config->src_premulti_en ?
1790 int dst_color_mode = alpha_config->dst_premulti_en ?
1793 alpha->src_color_ctrl.val = 0;
1794 alpha->dst_color_ctrl.val = 0;
1795 alpha->src_alpha_ctrl.val = 0;
1796 alpha->dst_alpha_ctrl.val = 0;
1798 if (!alpha_config->src_pixel_alpha_en)
1799 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1800 else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en)
1801 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1803 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1805 alpha->src_color_ctrl.bits.alpha_en = 1;
1807 if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) {
1808 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1809 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1810 } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) {
1811 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1812 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE;
1814 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL;
1815 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1817 alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8;
1818 alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1819 alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1821 alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1822 alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1823 alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1824 alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8;
1825 alpha->dst_color_ctrl.bits.color_mode = dst_color_mode;
1826 alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1828 alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1829 alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode;
1830 alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1831 alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE;
1833 alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1834 if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
1835 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1837 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1838 alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION;
1839 alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1849 vp = &vop2->vps[i];
1850 used_layer += hweight32(vp->win_mask);
1869 bottom_win_pstate = main_win->base.state;
1871 dst_glb_alpha_val = main_win->base.state->alpha;
1873 if (!bottom_win_pstate->fb)
1886 switch (main_win->data->phys_id) {
1901 if (vop2->version <= VOP_VERSION_RK3588) {
1921 struct vop2 *vop2 = vp->vop2;
1934 if (vop2->version <= VOP_VERSION_RK3588)
1935 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
1941 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1944 if (plane->state->normalized_zpos == 0 &&
1945 !is_opaque(plane->state->alpha) &&
1953 dst_global_alpha = plane->state->alpha;
1957 if (vop2->version <= VOP_VERSION_RK3588) {
1963 src_color_ctrl_reg = RK3576_OVL_MIX0_SRC_COLOR_CTRL(vp->id);
1964 dst_color_ctrl_reg = RK3576_OVL_MIX0_DST_COLOR_CTRL(vp->id);
1965 src_alpha_ctrl_reg = RK3576_OVL_MIX0_SRC_ALPHA_CTRL(vp->id);
1966 dst_alpha_ctrl_reg = RK3576_OVL_MIX0_DST_ALPHA_CTRL(vp->id);
1969 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1971 int zpos = plane->state->normalized_zpos;
1979 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
1984 plane = &win->base;
1985 fb = plane->state->fb;
1987 pixel_alpha_en = fb->format->has_alpha;
1993 /* Cd = Cs + (1 - As) * Cd * Agd */
1996 alpha_config.src_glb_alpha_value = plane->state->alpha;
2005 /* Cd = Cs + (1 - As) * Cd */
2008 alpha_config.src_glb_alpha_value = plane->state->alpha;
2014 offset = (mixer_id + zpos - 1) * 0x10;
2022 if (vp->id == 0) {
2023 if (vop2->version <= VOP_VERSION_RK3588) {
2029 src_color_ctrl_reg = RK3576_OVL_HDR_SRC_COLOR_CTRL(vp->id);
2030 dst_color_ctrl_reg = RK3576_OVL_HDR_DST_COLOR_CTRL(vp->id);
2031 src_alpha_ctrl_reg = RK3576_OVL_HDR_SRC_ALPHA_CTRL(vp->id);
2032 dst_alpha_ctrl_reg = RK3576_OVL_HDR_DST_ALPHA_CTRL(vp->id);
2069 port_mux_sel == vop2->old_port_sel, 0, 50 * 1000);
2071 DRM_DEV_ERROR(vop2->dev, "wait port_mux done timeout: 0x%x--0x%x\n",
2072 port_mux_sel, vop2->old_port_sel);
2091 DRM_DEV_ERROR(vop2->dev, "wait layer cfg done timeout: 0x%x--0x%x\n",
2097 struct vop2 *vop2 = vp->vop2;
2110 struct vop2_video_port *vp0 = &vop2->vps[0];
2111 struct vop2_video_port *vp1 = &vop2->vps[1];
2112 struct vop2_video_port *vp2 = &vop2->vps[2];
2113 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
2115 mutex_lock(&vop2->ovl_lock);
2120 if (vcstate->yuv_overlay)
2121 ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id);
2123 ovl_ctrl &= ~RK3568_OVL_CTRL__YUV_MODE(vp->id);
2125 old_port_sel = vop2->old_port_sel;
2129 if (vp0->nlayers)
2131 vp0->nlayers - 1);
2135 if (vp1->nlayers)
2137 (vp0->nlayers + vp1->nlayers - 1));
2141 if (vp2->nlayers)
2143 (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1));
2148 if (vop2->version == VOP_VERSION_RK3588)
2152 old_layer_sel = vop2->old_layer_sel;
2156 for (i = 0; i < vp->id; i++)
2157 ofs += vop2->vps[i].nlayers;
2159 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2163 layer_id = (u8)(plane->state->normalized_zpos + ofs);
2167 for (old_layer_id = 0; old_layer_id < vop2->data->win_size; old_layer_id++) {
2169 if (layer_sel_id == win->data->layer_sel_id[vp->id])
2176 for (i = 0; i < vop2->data->win_size; i++) {
2177 old_win = &vop2->win[i];
2179 if (layer_sel_id == old_win->data->layer_sel_id[vp->id])
2183 switch (win->data->phys_id) {
2186 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id);
2190 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id);
2194 port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER2, vp->id);
2198 port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER3, vp->id);
2202 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id);
2206 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id);
2210 port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART2, vp->id);
2214 port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART3, vp->id);
2218 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id);
2222 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id);
2227 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(layer_id, win->data->layer_sel_id[vp->id]);
2234 old_win->data->layer_sel_id[vp->id]);
2237 vop2->old_layer_sel = layer_sel;
2238 vop2->old_port_sel = port_sel;
2254 ovl_ctrl |= FIELD_PREP(RK3568_OVL_CTRL__LAYERSEL_REGDONE_SEL, vp->id);
2264 rk3568_vop2_wait_for_layer_cfg_done(vop2, vop2->old_layer_sel);
2267 mutex_unlock(&vop2->ovl_lock);
2272 struct vop2 *vop2 = vp->vop2;
2277 for (i = 0; i < vop2->data->win_size; i++) {
2280 win = &vop2->win[i];
2281 dly = win->delay;
2283 switch (win->data->phys_id) {
2315 struct vop2 *vop2 = vp->vop2;
2316 struct drm_crtc *crtc = &vp->crtc;
2319 vp->win_mask = 0;
2324 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT];
2326 vp->win_mask |= BIT(win->data->phys_id);
2332 if (!vp->win_mask)
2342 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
2343 struct vop2 *vop2 = vp->vop2;
2348 ovl_ctrl = vop2_readl(vop2, RK3576_OVL_CTRL(vp->id));
2349 if (vcstate->yuv_overlay)
2354 vop2_writel(vop2, RK3576_OVL_CTRL(vp->id), ovl_ctrl);
2356 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2359 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos,
2361 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(plane->state->normalized_zpos,
2362 win->data->layer_sel_id[vp->id]);
2365 vop2_writel(vop2, RK3576_OVL_LAYER_SEL(vp->id), layer_sel);
2373 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
2381 struct vop2 *vop2 = vp->vop2;
2382 struct drm_crtc *crtc = &vp->crtc;
2385 vp->win_mask = 0;
2390 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT];
2391 vp->win_mask |= BIT(win->data->phys_id);
2397 if (!vp->win_mask)
2407 struct drm_crtc *crtc = &vp->crtc;
2408 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2409 u16 hdisplay = mode->crtc_hdisplay;
2410 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
2414 bg_dly = vp->data->pre_scan_max_dly[3];
2415 vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
2418 pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
2424 struct drm_crtc *crtc = &vp->crtc;
2425 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
2426 u16 hdisplay = mode->crtc_hdisplay;
2427 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
2431 bg_dly = vp->data->pre_scan_max_dly[VOP2_DLY_WIN] +
2432 vp->data->pre_scan_max_dly[VOP2_DLY_LAYER_MIX] +
2433 vp->data->pre_scan_max_dly[VOP2_DLY_HDR_MIX];
2435 vop2_writel(vp->vop2, RK3576_OVL_BG_MIX_CTRL(vp->id),
2438 pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
2539 .compatible = "rockchip,rk3566-vop",
2542 .compatible = "rockchip,rk3568-vop",
2545 .compatible = "rockchip,rk3576-vop",
2548 .compatible = "rockchip,rk3588-vop",
2557 struct device *dev = &pdev->dev;
2564 component_del(&pdev->dev, &vop2_component_ops);
2571 .name = "rockchip-vop2",