Lines Matching +full:1 +full:x64 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author:Mark Yao <mark.yao@rock-chips.com>
12 #include <dt-bindings/soc/rockchip,vop2.h>
25 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0)
27 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0)
28 #define VOP2_FEATURE_HAS_VO0_GRF BIT(1)
29 #define VOP2_FEATURE_HAS_VO1_GRF BIT(2)
30 #define VOP2_FEATURE_HAS_VOP_GRF BIT(3)
31 #define VOP2_FEATURE_HAS_SYS_PMU BIT(4)
33 #define WIN_FEATURE_AFBDC BIT(0)
34 #define WIN_FEATURE_CLUSTER BIT(1)
70 #define VOP2_PD_CLUSTER0 BIT(0)
71 #define VOP2_PD_CLUSTER1 BIT(1)
72 #define VOP2_PD_CLUSTER2 BIT(2)
73 #define VOP2_PD_CLUSTER3 BIT(3)
74 #define VOP2_PD_DSC_8K BIT(5)
75 #define VOP2_PD_DSC_4K BIT(6)
76 #define VOP2_PD_ESMART BIT(7)
259 * struct vop2_ops - helper operations for vop2 hardware
342 #define FS_NEW_INTR BIT(4)
343 #define ADDR_SAME_INTR BIT(5)
344 #define LINE_FLAG1_INTR BIT(6)
345 #define WIN0_EMPTY_INTR BIT(7)
346 #define WIN1_EMPTY_INTR BIT(8)
347 #define WIN2_EMPTY_INTR BIT(9)
348 #define WIN3_EMPTY_INTR BIT(10)
349 #define HWC_EMPTY_INTR BIT(11)
350 #define POST_BUF_EMPTY_INTR BIT(12)
351 #define PWM_GEN_INTR BIT(13)
352 #define DMA_FINISH_INTR BIT(14)
353 #define FS_FIELD_INTR BIT(15)
354 #define FE_INTR BIT(16)
355 #define WB_UV_FIFO_FULL_INTR BIT(17)
356 #define WB_YRGB_FIFO_FULL_INTR BIT(18)
357 #define WB_COMPLETE_INTR BIT(19)
496 #define RK3568_VP_BCSH_BCS 0x64
548 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64
581 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64
626 #define RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN BIT(15)
628 #define RK3568_VP_DSP_CTRL__STANDBY BIT(31)
629 #define RK3568_VP_DSP_CTRL__DSP_LUT_EN BIT(28)
630 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_MODE BIT(20)
632 #define RK3568_VP_DSP_CTRL__DITHER_DOWN_EN BIT(17)
633 #define RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN BIT(16)
634 #define RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y BIT(15)
635 #define RK3568_VP_DSP_CTRL__DSP_RG_SWAP BIT(10)
636 #define RK3568_VP_DSP_CTRL__DSP_RB_SWAP BIT(9)
637 #define RK3568_VP_DSP_CTRL__DSP_BG_SWAP BIT(8)
638 #define RK3568_VP_DSP_CTRL__DSP_INTERLACE BIT(7)
639 #define RK3568_VP_DSP_CTRL__DSP_FILED_POL BIT(6)
640 #define RK3568_VP_DSP_CTRL__P2I_EN BIT(5)
641 #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4)
644 #define RK3588_VP_DSP_CTRL__GAMMA_UPDATE_EN BIT(22)
647 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0)
649 #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1)
650 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0)
653 #define RK3568_SYS_DSP_INFACE_EN_LVDS1 BIT(24)
655 #define RK3568_SYS_DSP_INFACE_EN_MIPI1 BIT(20)
661 #define RK3568_SYS_DSP_INFACE_EN_LVDS0 BIT(5)
662 #define RK3568_SYS_DSP_INFACE_EN_MIPI0 BIT(4)
663 #define RK3568_SYS_DSP_INFACE_EN_EDP BIT(3)
664 #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1)
665 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0)
674 #define RK3588_SYS_DSP_INFACE_EN_MIPI1 BIT(7)
675 #define RK3588_SYS_DSP_INFACE_EN_MIPI0 BIT(6)
676 #define RK3588_SYS_DSP_INFACE_EN_HDMI1 BIT(5)
677 #define RK3588_SYS_DSP_INFACE_EN_EDP1 BIT(4)
678 #define RK3588_SYS_DSP_INFACE_EN_HDMI0 BIT(3)
679 #define RK3588_SYS_DSP_INFACE_EN_EDP0 BIT(2)
680 #define RK3588_SYS_DSP_INFACE_EN_DP1 BIT(1)
681 #define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0)
700 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5)
701 #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4)
703 #define RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN BIT(31)
705 #define RK3568_DSP_IF_POL__CFG_DONE_IMD BIT(28)
711 #define VOP2_COLOR_KEY_MASK BIT(31)
713 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28)
714 #define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp)
739 #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0)
741 #define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0)
748 #define VP_INT_DSP_HOLD_VALID BIT(6)
749 #define VP_INT_FS_FIELD BIT(5)
750 #define VP_INT_POST_BUF_EMPTY BIT(4)
751 #define VP_INT_LINE_FLAG1 BIT(3)
752 #define VP_INT_LINE_FLAG0 BIT(2)
753 #define VOP2_INT_BUS_ERRPR BIT(1)
754 #define VP_INT_FS BIT(0)
756 #define POLFLAG_DCLK_INV BIT(3)
758 #define RK3576_OVL_CTRL__YUV_MODE BIT(0)
761 #define RK3576_DSP_IF_CFG_DONE_IMD BIT(31)
762 #define RK3576_DSP_IF_DCLK_SEL_OUT BIT(21)
763 #define RK3576_DSP_IF_PCLK_DIV BIT(20)
766 #define RK3576_DSP_IF_CLK_OUT_EN BIT(1)
767 #define RK3576_DSP_IF_EN BIT(0)
780 ROCKCHIP_VOP2_PHY_ID_INVALID = -1,
787 regmap_write(vop2->map, offset, v);
792 regmap_write(vp->vop2->map, vp->data->offset + offset, v);
799 regmap_read(vop2->map, offset, &val);
808 regmap_read(vp->vop2->map, vp->data->offset + offset, &val);
815 regmap_field_write(win->reg[reg], v);
820 return win->data->feature & WIN_FEATURE_CLUSTER;