Lines Matching +full:0 +full:x65c
14 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0)
16 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0)
22 #define WIN_FEATURE_AFBDC BIT(0)
50 * should be all none zero, 0 will be treat as invalid;
52 #define VOP2_PD_CLUSTER0 BIT(0)
214 #define RK3568_GRF_VO_CON1 0x0364
216 #define RK3588_GRF_SOC_CON1 0x0304
217 #define RK3588_GRF_VOP_CON2 0x08
218 #define RK3588_GRF_VO1_CON0 0x00
221 #define RK3568_REG_CFG_DONE 0x000
222 #define RK3568_VERSION_INFO 0x004
223 #define RK3568_SYS_AUTO_GATING_CTRL 0x008
224 #define RK3568_SYS_AXI_LUT_CTRL 0x024
225 #define RK3568_DSP_IF_EN 0x028
226 #define RK3568_DSP_IF_CTRL 0x02c
227 #define RK3568_DSP_IF_POL 0x030
228 #define RK3588_SYS_PD_CTRL 0x034
229 #define RK3568_WB_CTRL 0x40
230 #define RK3568_WB_XSCAL_FACTOR 0x44
231 #define RK3568_WB_YRGB_MST 0x48
232 #define RK3568_WB_CBR_MST 0x4C
233 #define RK3568_OTP_WIN_EN 0x050
234 #define RK3568_LUT_PORT_SEL 0x058
235 #define RK3568_SYS_STATUS0 0x060
236 #define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4)
237 #define RK3568_SYS0_INT_EN 0x80
238 #define RK3568_SYS0_INT_CLR 0x84
239 #define RK3568_SYS0_INT_STATUS 0x88
240 #define RK3568_SYS1_INT_EN 0x90
241 #define RK3568_SYS1_INT_CLR 0x94
242 #define RK3568_SYS1_INT_STATUS 0x98
243 #define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10)
244 #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10)
245 #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10)
246 #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10)
249 #define RK3568_VP0_CTRL_BASE 0x0C00
250 #define RK3568_VP1_CTRL_BASE 0x0D00
251 #define RK3568_VP2_CTRL_BASE 0x0E00
252 #define RK3588_VP3_CTRL_BASE 0x0F00
253 #define RK3568_VP_DSP_CTRL 0x00
254 #define RK3568_VP_MIPI_CTRL 0x04
255 #define RK3568_VP_COLOR_BAR_CTRL 0x08
256 #define RK3588_VP_CLK_CTRL 0x0C
257 #define RK3568_VP_3D_LUT_CTRL 0x10
258 #define RK3568_VP_3D_LUT_MST 0x20
259 #define RK3568_VP_DSP_BG 0x2C
260 #define RK3568_VP_PRE_SCAN_HTIMING 0x30
261 #define RK3568_VP_POST_DSP_HACT_INFO 0x34
262 #define RK3568_VP_POST_DSP_VACT_INFO 0x38
263 #define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C
264 #define RK3568_VP_POST_SCL_CTRL 0x40
265 #define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44
266 #define RK3568_VP_DSP_HTOTAL_HS_END 0x48
267 #define RK3568_VP_DSP_HACT_ST_END 0x4C
268 #define RK3568_VP_DSP_VTOTAL_VS_END 0x50
269 #define RK3568_VP_DSP_VACT_ST_END 0x54
270 #define RK3568_VP_DSP_VS_ST_END_F1 0x58
271 #define RK3568_VP_DSP_VACT_ST_END_F1 0x5C
272 #define RK3568_VP_BCSH_CTRL 0x60
273 #define RK3568_VP_BCSH_BCS 0x64
274 #define RK3568_VP_BCSH_H 0x68
275 #define RK3568_VP_BCSH_COLOR_BAR 0x6C
278 #define RK3568_OVL_CTRL 0x600
279 #define RK3568_OVL_LAYER_SEL 0x604
280 #define RK3568_OVL_PORT_SEL 0x608
281 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610
282 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
283 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
284 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
285 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650
286 #define RK3568_MIX0_DST_COLOR_CTRL 0x654
287 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
288 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
289 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
290 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
291 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
292 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
293 #define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4)
294 #define RK3568_CLUSTER_DLY_NUM 0x6F0
295 #define RK3568_SMART_DLY_NUM 0x6F8
298 #define RK3568_CLUSTER0_CTRL_BASE 0x1000
299 #define RK3568_CLUSTER1_CTRL_BASE 0x1200
300 #define RK3588_CLUSTER2_CTRL_BASE 0x1400
301 #define RK3588_CLUSTER3_CTRL_BASE 0x1600
302 #define RK3568_ESMART0_CTRL_BASE 0x1800
303 #define RK3568_ESMART1_CTRL_BASE 0x1A00
304 #define RK3568_SMART0_CTRL_BASE 0x1C00
305 #define RK3568_SMART1_CTRL_BASE 0x1E00
306 #define RK3588_ESMART2_CTRL_BASE 0x1C00
307 #define RK3588_ESMART3_CTRL_BASE 0x1E00
309 #define RK3568_CLUSTER_WIN_CTRL0 0x00
310 #define RK3568_CLUSTER_WIN_CTRL1 0x04
311 #define RK3568_CLUSTER_WIN_YRGB_MST 0x10
312 #define RK3568_CLUSTER_WIN_CBR_MST 0x14
313 #define RK3568_CLUSTER_WIN_VIR 0x18
314 #define RK3568_CLUSTER_WIN_ACT_INFO 0x20
315 #define RK3568_CLUSTER_WIN_DSP_INFO 0x24
316 #define RK3568_CLUSTER_WIN_DSP_ST 0x28
317 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30
318 #define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C
319 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50
320 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54
321 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58
322 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C
323 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60
324 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64
325 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68
326 #define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C
328 #define RK3568_CLUSTER_CTRL 0x100
331 #define RK3568_SMART_CTRL0 0x00
332 #define RK3568_SMART_CTRL1 0x04
333 #define RK3568_SMART_REGION0_CTRL 0x10
334 #define RK3568_SMART_REGION0_YRGB_MST 0x14
335 #define RK3568_SMART_REGION0_CBR_MST 0x18
336 #define RK3568_SMART_REGION0_VIR 0x1C
337 #define RK3568_SMART_REGION0_ACT_INFO 0x20
338 #define RK3568_SMART_REGION0_DSP_INFO 0x24
339 #define RK3568_SMART_REGION0_DSP_ST 0x28
340 #define RK3568_SMART_REGION0_SCL_CTRL 0x30
341 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34
342 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38
343 #define RK3568_SMART_REGION0_SCL_OFFSET 0x3C
344 #define RK3568_SMART_REGION1_CTRL 0x40
345 #define RK3568_SMART_REGION1_YRGB_MST 0x44
346 #define RK3568_SMART_REGION1_CBR_MST 0x48
347 #define RK3568_SMART_REGION1_VIR 0x4C
348 #define RK3568_SMART_REGION1_ACT_INFO 0x50
349 #define RK3568_SMART_REGION1_DSP_INFO 0x54
350 #define RK3568_SMART_REGION1_DSP_ST 0x58
351 #define RK3568_SMART_REGION1_SCL_CTRL 0x60
352 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64
353 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68
354 #define RK3568_SMART_REGION1_SCL_OFFSET 0x6C
355 #define RK3568_SMART_REGION2_CTRL 0x70
356 #define RK3568_SMART_REGION2_YRGB_MST 0x74
357 #define RK3568_SMART_REGION2_CBR_MST 0x78
358 #define RK3568_SMART_REGION2_VIR 0x7C
359 #define RK3568_SMART_REGION2_ACT_INFO 0x80
360 #define RK3568_SMART_REGION2_DSP_INFO 0x84
361 #define RK3568_SMART_REGION2_DSP_ST 0x88
362 #define RK3568_SMART_REGION2_SCL_CTRL 0x90
363 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94
364 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98
365 #define RK3568_SMART_REGION2_SCL_OFFSET 0x9C
366 #define RK3568_SMART_REGION3_CTRL 0xA0
367 #define RK3568_SMART_REGION3_YRGB_MST 0xA4
368 #define RK3568_SMART_REGION3_CBR_MST 0xA8
369 #define RK3568_SMART_REGION3_VIR 0xAC
370 #define RK3568_SMART_REGION3_ACT_INFO 0xB0
371 #define RK3568_SMART_REGION3_DSP_INFO 0xB4
372 #define RK3568_SMART_REGION3_DSP_ST 0xB8
373 #define RK3568_SMART_REGION3_SCL_CTRL 0xC0
374 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4
375 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8
376 #define RK3568_SMART_REGION3_SCL_OFFSET 0xCC
377 #define RK3568_SMART_COLOR_KEY_CTRL 0xD0
380 #define RK3568_HDR_LUT_CTRL 0x2000
381 #define RK3568_HDR_LUT_MST 0x2004
382 #define RK3568_SDR2HDR_CTRL 0x2010
383 #define RK3568_HDR2SDR_CTRL 0x2020
384 #define RK3568_HDR2SDR_SRC_RANGE 0x2024
385 #define RK3568_HDR2SDR_NORMFACEETF 0x2028
386 #define RK3568_HDR2SDR_DST_RANGE 0x202C
387 #define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030
388 #define RK3568_HDR_EETF_OETF_Y0 0x203C
389 #define RK3568_HDR_SAT_Y0 0x20C0
390 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0
391 #define RK3568_HDR_OETF_DX_POW1 0x2200
392 #define RK3568_HDR_OETF_XN1 0x2300
409 #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0)
412 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0)
415 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0)
430 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0)
446 #define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0)
458 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0)
472 #define VOP2_CLUSTER_YUV444_10 0x12
494 #define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0)
500 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0)
502 #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0)
504 #define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0)
509 #define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0)
517 #define VP_INT_FS BIT(0)
522 ROCKCHIP_VOP2_CLUSTER0 = 0,