Lines Matching +full:0 +full:x1c00

19 #define VOP_VERSION_RK3568	VOP2_VERSION(0x40, 0x15, 0x8023)
20 #define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
21 #define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
22 #define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
23 #define VOP_VERSION_RK3576 VOP2_VERSION(0x50, 0x19, 0x9765)
25 #define VOP2_VP_FEATURE_OUTPUT_10BIT BIT(0)
27 #define VOP2_FEATURE_HAS_SYS_GRF BIT(0)
33 #define WIN_FEATURE_AFBDC BIT(0)
68 * should be all none zero, 0 will be treat as invalid;
70 #define VOP2_PD_CLUSTER0 BIT(0)
398 #define RK3568_GRF_VO_CON1 0x0364
400 #define RK3588_GRF_SOC_CON1 0x0304
401 #define RK3588_GRF_VOP_CON2 0x08
402 #define RK3588_GRF_VO1_CON0 0x00
405 #define RK3568_REG_CFG_DONE 0x000
406 #define RK3568_VERSION_INFO 0x004
407 #define RK3568_SYS_AUTO_GATING_CTRL 0x008
408 #define RK3576_SYS_MMU_CTRL_IMD 0x020
409 #define RK3568_SYS_AXI_LUT_CTRL 0x024
410 #define RK3568_DSP_IF_EN 0x028
411 #define RK3576_SYS_PORT_CTRL_IMD 0x028
412 #define RK3568_DSP_IF_CTRL 0x02c
413 #define RK3568_DSP_IF_POL 0x030
414 #define RK3576_SYS_CLUSTER_PD_CTRL_IMD 0x030
415 #define RK3588_SYS_PD_CTRL 0x034
416 #define RK3568_WB_CTRL 0x40
417 #define RK3568_WB_XSCAL_FACTOR 0x44
418 #define RK3568_WB_YRGB_MST 0x48
419 #define RK3568_WB_CBR_MST 0x4C
420 #define RK3568_OTP_WIN_EN 0x050
421 #define RK3568_LUT_PORT_SEL 0x058
422 #define RK3568_SYS_STATUS0 0x060
423 #define RK3568_VP_LINE_FLAG(vp) (0x70 + (vp) * 0x4)
424 #define RK3568_SYS0_INT_EN 0x80
425 #define RK3568_SYS0_INT_CLR 0x84
426 #define RK3568_SYS0_INT_STATUS 0x88
427 #define RK3568_SYS1_INT_EN 0x90
428 #define RK3568_SYS1_INT_CLR 0x94
429 #define RK3568_SYS1_INT_STATUS 0x98
430 #define RK3568_VP_INT_EN(vp) (0xA0 + (vp) * 0x10)
431 #define RK3568_VP_INT_CLR(vp) (0xA4 + (vp) * 0x10)
432 #define RK3568_VP_INT_STATUS(vp) (0xA8 + (vp) * 0x10)
433 #define RK3568_VP_INT_RAW_STATUS(vp) (0xAC + (vp) * 0x10)
434 #define RK3576_WB_CTRL 0x100
435 #define RK3576_WB_XSCAL_FACTOR 0x104
436 #define RK3576_WB_YRGB_MST 0x108
437 #define RK3576_WB_CBR_MST 0x10C
438 #define RK3576_WB_VIR_STRIDE 0x110
439 #define RK3576_WB_TIMEOUT_CTRL 0x114
440 #define RK3576_MIPI0_IF_CTRL 0x180
441 #define RK3576_HDMI0_IF_CTRL 0x184
442 #define RK3576_EDP0_IF_CTRL 0x188
443 #define RK3576_DP0_IF_CTRL 0x18C
444 #define RK3576_RGB_IF_CTRL 0x194
445 #define RK3576_DP1_IF_CTRL 0x1A4
446 #define RK3576_DP2_IF_CTRL 0x1B0
449 #define RK3576_SYS_EXTRA_ALPHA_CTRL 0x500
450 #define RK3576_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530
451 #define RK3576_CLUSTER0_MIX_DST_COLOR_CTRL 0x534
452 #define RK3576_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538
453 #define RK3576_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c
454 #define RK3576_CLUSTER1_MIX_SRC_COLOR_CTRL 0x540
455 #define RK3576_CLUSTER1_MIX_DST_COLOR_CTRL 0x544
456 #define RK3576_CLUSTER1_MIX_SRC_ALPHA_CTRL 0x548
457 #define RK3576_CLUSTER1_MIX_DST_ALPHA_CTRL 0x54c
460 #define RK3576_OVL_CTRL(vp) (0x600 + (vp) * 0x100)
461 #define RK3576_OVL_LAYER_SEL(vp) (0x604 + (vp) * 0x100)
462 #define RK3576_OVL_MIX0_SRC_COLOR_CTRL(vp) (0x620 + (vp) * 0x100)
463 #define RK3576_OVL_MIX0_DST_COLOR_CTRL(vp) (0x624 + (vp) * 0x100)
464 #define RK3576_OVL_MIX0_SRC_ALPHA_CTRL(vp) (0x628 + (vp) * 0x100)
465 #define RK3576_OVL_MIX0_DST_ALPHA_CTRL(vp) (0x62C + (vp) * 0x100)
466 #define RK3576_OVL_MIX1_SRC_COLOR_CTRL(vp) (0x630 + (vp) * 0x100)
467 #define RK3576_OVL_MIX1_DST_COLOR_CTRL(vp) (0x634 + (vp) * 0x100)
468 #define RK3576_OVL_MIX1_SRC_ALPHA_CTRL(vp) (0x638 + (vp) * 0x100)
469 #define RK3576_OVL_MIX1_DST_ALPHA_CTRL(vp) (0x63C + (vp) * 0x100)
470 #define RK3576_OVL_MIX2_SRC_COLOR_CTRL(vp) (0x640 + (vp) * 0x100)
471 #define RK3576_OVL_MIX2_DST_COLOR_CTRL(vp) (0x644 + (vp) * 0x100)
472 #define RK3576_OVL_MIX2_SRC_ALPHA_CTRL(vp) (0x648 + (vp) * 0x100)
473 #define RK3576_OVL_MIX2_DST_ALPHA_CTRL(vp) (0x64C + (vp) * 0x100)
474 #define RK3576_EXTRA_OVL_SRC_COLOR_CTRL(vp) (0x650 + (vp) * 0x100)
475 #define RK3576_EXTRA_OVL_DST_COLOR_CTRL(vp) (0x654 + (vp) * 0x100)
476 #define RK3576_EXTRA_OVL_SRC_ALPHA_CTRL(vp) (0x658 + (vp) * 0x100)
477 #define RK3576_EXTRA_OVL_DST_ALPHA_CTRL(vp) (0x65C + (vp) * 0x100)
478 #define RK3576_OVL_HDR_SRC_COLOR_CTRL(vp) (0x660 + (vp) * 0x100)
479 #define RK3576_OVL_HDR_DST_COLOR_CTRL(vp) (0x664 + (vp) * 0x100)
480 #define RK3576_OVL_HDR_SRC_ALPHA_CTRL(vp) (0x668 + (vp) * 0x100)
481 #define RK3576_OVL_HDR_DST_ALPHA_CTRL(vp) (0x66C + (vp) * 0x100)
482 #define RK3576_OVL_BG_MIX_CTRL(vp) (0x670 + (vp) * 0x100)
485 #define RK3568_VP0_CTRL_BASE 0x0C00
486 #define RK3568_VP1_CTRL_BASE 0x0D00
487 #define RK3568_VP2_CTRL_BASE 0x0E00
488 #define RK3588_VP3_CTRL_BASE 0x0F00
489 #define RK3568_VP_DSP_CTRL 0x00
490 #define RK3568_VP_MIPI_CTRL 0x04
491 #define RK3568_VP_COLOR_BAR_CTRL 0x08
492 #define RK3588_VP_CLK_CTRL 0x0C
493 #define RK3568_VP_3D_LUT_CTRL 0x10
494 #define RK3568_VP_3D_LUT_MST 0x20
495 #define RK3568_VP_DSP_BG 0x2C
496 #define RK3568_VP_PRE_SCAN_HTIMING 0x30
497 #define RK3568_VP_POST_DSP_HACT_INFO 0x34
498 #define RK3568_VP_POST_DSP_VACT_INFO 0x38
499 #define RK3568_VP_POST_SCL_FACTOR_YRGB 0x3C
500 #define RK3568_VP_POST_SCL_CTRL 0x40
501 #define RK3568_VP_POST_DSP_VACT_INFO_F1 0x44
502 #define RK3568_VP_DSP_HTOTAL_HS_END 0x48
503 #define RK3568_VP_DSP_HACT_ST_END 0x4C
504 #define RK3568_VP_DSP_VTOTAL_VS_END 0x50
505 #define RK3568_VP_DSP_VACT_ST_END 0x54
506 #define RK3568_VP_DSP_VS_ST_END_F1 0x58
507 #define RK3568_VP_DSP_VACT_ST_END_F1 0x5C
508 #define RK3568_VP_BCSH_CTRL 0x60
509 #define RK3568_VP_BCSH_BCS 0x64
510 #define RK3568_VP_BCSH_H 0x68
511 #define RK3568_VP_BCSH_COLOR_BAR 0x6C
514 #define RK3568_OVL_CTRL 0x600
515 #define RK3568_OVL_LAYER_SEL 0x604
516 #define RK3568_OVL_PORT_SEL 0x608
517 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610
518 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
519 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
520 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
521 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650
522 #define RK3568_MIX0_DST_COLOR_CTRL 0x654
523 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
524 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
525 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
526 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
527 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
528 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC
529 #define RK3568_VP_BG_MIX_CTRL(vp) (0x6E0 + (vp) * 4)
530 #define RK3568_CLUSTER_DLY_NUM 0x6F0
531 #define RK3568_SMART_DLY_NUM 0x6F8
534 #define RK3568_CLUSTER0_CTRL_BASE 0x1000
535 #define RK3568_CLUSTER1_CTRL_BASE 0x1200
536 #define RK3588_CLUSTER2_CTRL_BASE 0x1400
537 #define RK3588_CLUSTER3_CTRL_BASE 0x1600
538 #define RK3568_ESMART0_CTRL_BASE 0x1800
539 #define RK3568_ESMART1_CTRL_BASE 0x1A00
540 #define RK3568_SMART0_CTRL_BASE 0x1C00
541 #define RK3568_SMART1_CTRL_BASE 0x1E00
542 #define RK3588_ESMART2_CTRL_BASE 0x1C00
543 #define RK3588_ESMART3_CTRL_BASE 0x1E00
545 #define RK3568_CLUSTER_WIN_CTRL0 0x00
546 #define RK3568_CLUSTER_WIN_CTRL1 0x04
547 #define RK3568_CLUSTER_WIN_CTRL2 0x08
548 #define RK3568_CLUSTER_WIN_YRGB_MST 0x10
549 #define RK3568_CLUSTER_WIN_CBR_MST 0x14
550 #define RK3568_CLUSTER_WIN_VIR 0x18
551 #define RK3568_CLUSTER_WIN_ACT_INFO 0x20
552 #define RK3568_CLUSTER_WIN_DSP_INFO 0x24
553 #define RK3568_CLUSTER_WIN_DSP_ST 0x28
554 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30
555 #define RK3568_CLUSTER_WIN_TRANSFORM_OFFSET 0x3C
556 #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50
557 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54
558 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58
559 #define RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH 0x5C
560 #define RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE 0x60
561 #define RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET 0x64
562 #define RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET 0x68
563 #define RK3568_CLUSTER_WIN_AFBCD_CTRL 0x6C
565 #define RK3576_CLUSTER_WIN_AFBCD_PLD_PTR_OFFSET 0x78
567 #define RK3568_CLUSTER_CTRL 0x100
568 #define RK3576_CLUSTER_PORT_SEL_IMD 0x1F4
569 #define RK3576_CLUSTER_DLY_NUM 0x1F8
572 #define RK3568_SMART_CTRL0 0x00
573 #define RK3568_SMART_CTRL1 0x04
574 #define RK3588_SMART_AXI_CTRL 0x08
575 #define RK3568_SMART_REGION0_CTRL 0x10
576 #define RK3568_SMART_REGION0_YRGB_MST 0x14
577 #define RK3568_SMART_REGION0_CBR_MST 0x18
578 #define RK3568_SMART_REGION0_VIR 0x1C
579 #define RK3568_SMART_REGION0_ACT_INFO 0x20
580 #define RK3568_SMART_REGION0_DSP_INFO 0x24
581 #define RK3568_SMART_REGION0_DSP_ST 0x28
582 #define RK3568_SMART_REGION0_SCL_CTRL 0x30
583 #define RK3568_SMART_REGION0_SCL_FACTOR_YRGB 0x34
584 #define RK3568_SMART_REGION0_SCL_FACTOR_CBR 0x38
585 #define RK3568_SMART_REGION0_SCL_OFFSET 0x3C
586 #define RK3568_SMART_REGION1_CTRL 0x40
587 #define RK3568_SMART_REGION1_YRGB_MST 0x44
588 #define RK3568_SMART_REGION1_CBR_MST 0x48
589 #define RK3568_SMART_REGION1_VIR 0x4C
590 #define RK3568_SMART_REGION1_ACT_INFO 0x50
591 #define RK3568_SMART_REGION1_DSP_INFO 0x54
592 #define RK3568_SMART_REGION1_DSP_ST 0x58
593 #define RK3568_SMART_REGION1_SCL_CTRL 0x60
594 #define RK3568_SMART_REGION1_SCL_FACTOR_YRGB 0x64
595 #define RK3568_SMART_REGION1_SCL_FACTOR_CBR 0x68
596 #define RK3568_SMART_REGION1_SCL_OFFSET 0x6C
597 #define RK3568_SMART_REGION2_CTRL 0x70
598 #define RK3568_SMART_REGION2_YRGB_MST 0x74
599 #define RK3568_SMART_REGION2_CBR_MST 0x78
600 #define RK3568_SMART_REGION2_VIR 0x7C
601 #define RK3568_SMART_REGION2_ACT_INFO 0x80
602 #define RK3568_SMART_REGION2_DSP_INFO 0x84
603 #define RK3568_SMART_REGION2_DSP_ST 0x88
604 #define RK3568_SMART_REGION2_SCL_CTRL 0x90
605 #define RK3568_SMART_REGION2_SCL_FACTOR_YRGB 0x94
606 #define RK3568_SMART_REGION2_SCL_FACTOR_CBR 0x98
607 #define RK3568_SMART_REGION2_SCL_OFFSET 0x9C
608 #define RK3568_SMART_REGION3_CTRL 0xA0
609 #define RK3568_SMART_REGION3_YRGB_MST 0xA4
610 #define RK3568_SMART_REGION3_CBR_MST 0xA8
611 #define RK3568_SMART_REGION3_VIR 0xAC
612 #define RK3568_SMART_REGION3_ACT_INFO 0xB0
613 #define RK3568_SMART_REGION3_DSP_INFO 0xB4
614 #define RK3568_SMART_REGION3_DSP_ST 0xB8
615 #define RK3568_SMART_REGION3_SCL_CTRL 0xC0
616 #define RK3568_SMART_REGION3_SCL_FACTOR_YRGB 0xC4
617 #define RK3568_SMART_REGION3_SCL_FACTOR_CBR 0xC8
618 #define RK3568_SMART_REGION3_SCL_OFFSET 0xCC
619 #define RK3568_SMART_COLOR_KEY_CTRL 0xD0
620 #define RK3576_SMART_ALPHA_MAP 0xD8
621 #define RK3576_SMART_PORT_SEL_IMD 0xF4
622 #define RK3576_SMART_DLY_NUM 0xF8
625 #define RK3568_HDR_LUT_CTRL 0x2000
626 #define RK3568_HDR_LUT_MST 0x2004
627 #define RK3568_SDR2HDR_CTRL 0x2010
628 #define RK3568_HDR2SDR_CTRL 0x2020
629 #define RK3568_HDR2SDR_SRC_RANGE 0x2024
630 #define RK3568_HDR2SDR_NORMFACEETF 0x2028
631 #define RK3568_HDR2SDR_DST_RANGE 0x202C
632 #define RK3568_HDR2SDR_NORMFACCGAMMA 0x2030
633 #define RK3568_HDR_EETF_OETF_Y0 0x203C
634 #define RK3568_HDR_SAT_Y0 0x20C0
635 #define RK3568_HDR_EOTF_OETF_Y0 0x20F0
636 #define RK3568_HDR_OETF_DX_POW1 0x2200
637 #define RK3568_HDR_OETF_XN1 0x2300
655 #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0)
660 #define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0)
663 #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0)
678 #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0)
694 #define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0)
706 #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0)
722 #define VOP2_CLUSTER_YUV444_10 0x12
746 #define RK3568_OVL_PORT_SET__PORT0_MUX GENMASK(3, 0)
752 #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0)
754 #define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0)
756 #define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0)
761 #define RK3568_SMART_DLY_NUM__ESMART0 GENMASK(7, 0)
769 #define VP_INT_FS BIT(0)
773 #define RK3576_OVL_CTRL__YUV_MODE BIT(0)
782 #define RK3576_DSP_IF_EN BIT(0)
785 ROCKCHIP_VOP2_CLUSTER0 = 0,