Lines Matching full:vp
267 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v) in vop2_vp_write() argument
269 regmap_write(vp->vop2->map, vp->data->offset + offset, v); in vop2_vp_write()
300 static void vop2_cfg_done(struct vop2_video_port *vp) in vop2_cfg_done() argument
302 struct vop2 *vop2 = vp->vop2; in vop2_cfg_done()
305 val |= BIT(vp->id) | (BIT(vp->id) << 16); in vop2_cfg_done()
853 static void vop2_setup_csc_mode(struct vop2_video_port *vp, in vop2_setup_csc_mode() argument
857 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); in vop2_setup_csc_mode()
884 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq) in vop2_crtc_enable_irq() argument
886 struct vop2 *vop2 = vp->vop2; in vop2_crtc_enable_irq()
888 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq); in vop2_crtc_enable_irq()
889 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq); in vop2_crtc_enable_irq()
892 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq) in vop2_crtc_disable_irq() argument
894 struct vop2 *vop2 = vp->vop2; in vop2_crtc_disable_irq()
896 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16); in vop2_crtc_disable_irq()
1004 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_disable() local
1005 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_disable()
1023 reinit_completion(&vp->dsp_hold_completion); in vop2_crtc_atomic_disable()
1025 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID); in vop2_crtc_atomic_disable()
1027 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY); in vop2_crtc_atomic_disable()
1029 ret = wait_for_completion_timeout(&vp->dsp_hold_completion, in vop2_crtc_atomic_disable()
1032 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id); in vop2_crtc_atomic_disable()
1034 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID); in vop2_crtc_atomic_disable()
1036 clk_disable_unprepare(vp->dclk); in vop2_crtc_atomic_disable()
1061 struct vop2_video_port *vp; in vop2_plane_atomic_check() local
1074 vp = to_vop2_video_port(crtc); in vop2_plane_atomic_check()
1075 vop2 = vp->vop2; in vop2_plane_atomic_check()
1200 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_plane_atomic_update() local
1274 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n", in vop2_plane_atomic_update()
1275 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay); in vop2_plane_atomic_update()
1285 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n", in vop2_plane_atomic_update()
1286 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay); in vop2_plane_atomic_update()
1299 drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n", in vop2_plane_atomic_update()
1300 vp->id, win->data->name, actual_w); in vop2_plane_atomic_update()
1306 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n", in vop2_plane_atomic_update()
1307 vp->id, win->data->name, actual_w); in vop2_plane_atomic_update()
1317 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", in vop2_plane_atomic_update()
1318 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, in vop2_plane_atomic_update()
1344 drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n", in vop2_plane_atomic_update()
1345 vp->id, win->data->name, stride); in vop2_plane_atomic_update()
1428 vop2_setup_csc_mode(vp, win, pstate); in vop2_plane_atomic_update()
1461 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_enable_vblank() local
1463 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD); in vop2_crtc_enable_vblank()
1470 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_disable_vblank() local
1472 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD); in vop2_crtc_disable_vblank()
1516 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_post_config() local
1533 bg_dly = vp->data->pre_scan_max_dly[3]; in vop2_post_config()
1534 vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id), in vop2_post_config()
1538 vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); in vop2_post_config()
1546 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val); in vop2_post_config()
1551 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val); in vop2_post_config()
1554 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val); in vop2_post_config()
1561 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val); in vop2_post_config()
1568 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val); in vop2_post_config()
1571 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); in vop2_post_config()
1574 static unsigned long rk3568_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags) in rk3568_set_intf_mux() argument
1576 struct vop2 *vop2 = vp->vop2; in rk3568_set_intf_mux()
1577 struct drm_crtc *crtc = &vp->crtc; in rk3568_set_intf_mux()
1587 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id); in rk3568_set_intf_mux()
1598 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id); in rk3568_set_intf_mux()
1605 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id); in rk3568_set_intf_mux()
1612 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id); in rk3568_set_intf_mux()
1619 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); in rk3568_set_intf_mux()
1626 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id); in rk3568_set_intf_mux()
1633 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id); in rk3568_set_intf_mux()
1638 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); in rk3568_set_intf_mux()
1672 static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id, in rk3588_calc_cru_cfg() argument
1676 struct vop2 *vop2 = vp->vop2; in rk3588_calc_cru_cfg()
1677 struct drm_crtc *crtc = &vp->crtc; in rk3588_calc_cru_cfg()
1794 static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags) in rk3588_set_intf_mux() argument
1796 struct vop2 *vop2 = vp->vop2; in rk3588_set_intf_mux()
1801 clock = rk3588_calc_cru_cfg(vp, id, &dclk_core_div, &dclk_out_div, in rk3588_set_intf_mux()
1821 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id); in rk3588_set_intf_mux()
1833 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id); in rk3588_set_intf_mux()
1845 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id); in rk3588_set_intf_mux()
1855 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id); in rk3588_set_intf_mux()
1862 val = rk3588_get_mipi_port_mux(vp->id); in rk3588_set_intf_mux()
1870 val = rk3588_get_mipi_port_mux(vp->id); in rk3588_set_intf_mux()
1877 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP0_MUX, vp->id); in rk3588_set_intf_mux()
1884 FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); in rk3588_set_intf_mux()
1889 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); in rk3588_set_intf_mux()
1895 vop2_vp_write(vp, RK3588_VP_CLK_CTRL, vp_clk_div); in rk3588_set_intf_mux()
1903 static unsigned long vop2_set_intf_mux(struct vop2_video_port *vp, int ep_id, u32 polflags) in vop2_set_intf_mux() argument
1905 struct vop2 *vop2 = vp->vop2; in vop2_set_intf_mux()
1908 return rk3568_set_intf_mux(vp, ep_id, polflags); in vop2_set_intf_mux()
1910 return rk3588_set_intf_mux(vp, ep_id, polflags); in vop2_set_intf_mux()
1923 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_enable() local
1924 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_enable()
1926 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id]; in vop2_crtc_atomic_enable()
1948 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n", in vop2_crtc_atomic_enable()
1950 drm_mode_vrefresh(mode), vcstate->output_type, vp->id); in vop2_crtc_atomic_enable()
1954 ret = clk_prepare_enable(vp->dclk); in vop2_crtc_atomic_enable()
1957 vp->id, ret); in vop2_crtc_atomic_enable()
1969 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); in vop2_crtc_atomic_enable()
1987 clock = vop2_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); in vop2_crtc_atomic_enable()
2013 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len); in vop2_crtc_atomic_enable()
2016 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val); in vop2_crtc_atomic_enable()
2020 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val); in vop2_crtc_atomic_enable()
2027 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val); in vop2_crtc_atomic_enable()
2030 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val); in vop2_crtc_atomic_enable()
2040 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id), in vop2_crtc_atomic_enable()
2043 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len); in vop2_crtc_atomic_enable()
2050 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0); in vop2_crtc_atomic_enable()
2052 clk_set_rate(vp->dclk, clock); in vop2_crtc_atomic_enable()
2056 vop2_cfg_done(vp); in vop2_crtc_atomic_enable()
2058 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl); in vop2_crtc_atomic_enable()
2068 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_check() local
2076 if (nplanes > vp->nlayers) in vop2_crtc_atomic_check()
2148 struct vop2_video_port *vp; in vop2_find_start_mixer_id_for_vp() local
2153 vp = &vop2->vps[i]; in vop2_find_start_mixer_id_for_vp()
2154 used_layer += hweight32(vp->win_mask); in vop2_find_start_mixer_id_for_vp()
2198 static void vop2_setup_alpha(struct vop2_video_port *vp) in vop2_setup_alpha() argument
2200 struct vop2 *vop2 = vp->vop2; in vop2_setup_alpha()
2212 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id); in vop2_setup_alpha()
2215 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { in vop2_setup_alpha()
2231 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { in vop2_setup_alpha()
2281 if (vp->id == 0) { in vop2_setup_alpha()
2305 static void vop2_setup_layer_mixer(struct vop2_video_port *vp) in vop2_setup_layer_mixer() argument
2307 struct vop2 *vop2 = vp->vop2; in vop2_setup_layer_mixer()
2317 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); in vop2_setup_layer_mixer()
2322 ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id); in vop2_setup_layer_mixer()
2324 ovl_ctrl &= ~RK3568_OVL_CTRL__YUV_MODE(vp->id); in vop2_setup_layer_mixer()
2352 for (i = 0; i < vp->id; i++) in vop2_setup_layer_mixer()
2356 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) { in vop2_setup_layer_mixer()
2362 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id); in vop2_setup_layer_mixer()
2366 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); in vop2_setup_layer_mixer()
2370 port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER2, vp->id); in vop2_setup_layer_mixer()
2374 port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER3, vp->id); in vop2_setup_layer_mixer()
2378 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); in vop2_setup_layer_mixer()
2382 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); in vop2_setup_layer_mixer()
2386 port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART2, vp->id); in vop2_setup_layer_mixer()
2390 port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART3, vp->id); in vop2_setup_layer_mixer()
2394 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); in vop2_setup_layer_mixer()
2398 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id); in vop2_setup_layer_mixer()
2410 for (; nlayer < vp->nlayers; nlayer++) { in vop2_setup_layer_mixer()
2462 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_begin() local
2463 struct vop2 *vop2 = vp->vop2; in vop2_crtc_atomic_begin()
2466 vp->win_mask = 0; in vop2_crtc_atomic_begin()
2473 vp->win_mask |= BIT(win->data->phys_id); in vop2_crtc_atomic_begin()
2479 if (!vp->win_mask) in vop2_crtc_atomic_begin()
2482 vop2_setup_layer_mixer(vp); in vop2_crtc_atomic_begin()
2483 vop2_setup_alpha(vp); in vop2_crtc_atomic_begin()
2490 struct vop2_video_port *vp = to_vop2_video_port(crtc); in vop2_crtc_atomic_flush() local
2494 vop2_cfg_done(vp); in vop2_crtc_atomic_flush()
2500 vp->event = crtc->state->event; in vop2_crtc_atomic_flush()
2583 struct vop2_video_port *vp = &vop2->vps[i]; in vop2_isr() local
2584 struct drm_crtc *crtc = &vp->crtc; in vop2_isr()
2587 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id)); in vop2_isr()
2588 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs); in vop2_isr()
2591 complete(&vp->dsp_hold_completion); in vop2_isr()
2598 if (vp->event) { in vop2_isr()
2601 if (!(val & BIT(vp->id))) { in vop2_isr()
2602 drm_crtc_send_vblank_event(crtc, vp->event); in vop2_isr()
2603 vp->event = NULL; in vop2_isr()
2614 "POST_BUF_EMPTY irq err at vp%d\n", in vop2_isr()
2615 vp->id); in vop2_isr()
2675 struct vop2_video_port *vp = &vop2->vps[i]; in find_vp_without_primary() local
2677 if (!vp->crtc.port) in find_vp_without_primary()
2679 if (vp->primary_plane) in find_vp_without_primary()
2682 return vp; in find_vp_without_primary()
2695 struct vop2_video_port *vp; in vop2_create_crtcs() local
2704 vp_data = &vop2_data->vp[i]; in vop2_create_crtcs()
2705 vp = &vop2->vps[i]; in vop2_create_crtcs()
2706 vp->vop2 = vop2; in vop2_create_crtcs()
2707 vp->id = vp_data->id; in vop2_create_crtcs()
2708 vp->data = vp_data; in vop2_create_crtcs()
2710 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id); in vop2_create_crtcs()
2711 vp->dclk = devm_clk_get(vop2->dev, dclk_name); in vop2_create_crtcs()
2712 if (IS_ERR(vp->dclk)) { in vop2_create_crtcs()
2714 return PTR_ERR(vp->dclk); in vop2_create_crtcs()
2719 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i); in vop2_create_crtcs()
2730 vp->crtc.port = port; in vop2_create_crtcs()
2754 vp = find_vp_without_primary(vop2); in vop2_create_crtcs()
2755 if (vp) { in vop2_create_crtcs()
2757 vp->primary_plane = win; in vop2_create_crtcs()
2777 vp = &vop2->vps[i]; in vop2_create_crtcs()
2779 if (!vp->crtc.port) in vop2_create_crtcs()
2782 plane = &vp->primary_plane->base; in vop2_create_crtcs()
2784 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL, in vop2_create_crtcs()
2786 "video_port%d", vp->id); in vop2_create_crtcs()
2792 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs); in vop2_create_crtcs()
2794 init_completion(&vp->dsp_hold_completion); in vop2_create_crtcs()
2798 * On the VOP2 it's very hard to change the number of layers on a VP in vop2_create_crtcs()
2803 struct vop2_video_port *vp = &vop2->vps[i]; in vop2_create_crtcs() local
2805 if (vp->crtc.port) in vop2_create_crtcs()
2806 vp->nlayers = vop2_data->win_size / nvps; in vop2_create_crtcs()