Lines Matching refs:vop

44 #define VOP_WIN_SET(vop, win, name, v) \
45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
46 #define VOP_SCL_SET(vop, win, name, v) \
47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
48 #define VOP_SCL_SET_EXT(vop, win, name, v) \
49 vop_reg_set(vop, &win->phy->scl->ext->name, \
52 #define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
58 #define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
64 #define VOP_INTR_SET_MASK(vop, name, mask, v) \
65 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
67 #define VOP_REG_SET(vop, group, name, v) \
68 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
70 #define VOP_HAS_REG(vop, group, name) \
71 (!!(vop->data->group->name.mask))
73 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
76 for (i = 0; i < vop->data->intr->nintrs; i++) { \
77 if (vop->data->intr->intrs[i] & type) { \
82 VOP_INTR_SET_MASK(vop, name, mask, reg); \
84 #define VOP_INTR_GET_TYPE(vop, name, type) \
85 vop_get_intr_type(vop, &vop->data->intr->name, type)
87 #define VOP_WIN_GET(vop, win, name) \
88 vop_read_reg(vop, win->base, &win->phy->name)
93 #define VOP_WIN_GET_YRGBADDR(vop, win) \
94 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
97 ((vop_win) - (vop_win)->vop->win)
99 #define VOP_AFBC_SET(vop, name, v) \
101 if ((vop)->data->afbc) \
102 vop_reg_set((vop), &(vop)->data->afbc->name, \
106 #define to_vop(x) container_of(x, struct vop, crtc)
135 struct vop *vop;
139 struct vop {
162 /* physical map length of vop register */
167 /* lock vop irq reg */
174 /* vop AHP clk */
176 /* vop dclk */
178 /* vop share memory frequency */
181 /* vop dclk reset */
190 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
192 return readl(vop->regs + offset);
195 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
198 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
201 static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
208 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
219 uint32_t cached_val = vop->regsbak[offset >> 2];
222 vop->regsbak[offset >> 2] = v;
226 writel_relaxed(v, vop->regs + offset);
228 writel(v, vop->regs + offset);
231 static inline uint32_t vop_get_intr_type(struct vop *vop,
235 uint32_t regs = vop_read_reg(vop, 0, reg);
237 for (i = 0; i < vop->data->intr->nintrs; i++) {
238 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
239 ret |= vop->data->intr->intrs[i];
245 static inline void vop_cfg_done(struct vop *vop)
247 VOP_REG_SET(vop, common, cfg_done, 1);
260 * check for 3.x to also only rb swap BGR888 for unknown vop version
381 static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
400 DRM_DEV_ERROR(vop->dev, "Maximum dst width (4096) exceeded\n");
405 VOP_SCL_SET(vop, win, scale_yrgb_x,
407 VOP_SCL_SET(vop, win, scale_yrgb_y,
410 VOP_SCL_SET(vop, win, scale_cbcr_x,
412 VOP_SCL_SET(vop, win, scale_cbcr_y,
435 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
438 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
442 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
454 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
457 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
459 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
460 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
462 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
463 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
464 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
465 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
466 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
470 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
473 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
475 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
476 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
477 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
478 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
479 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
480 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
481 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
485 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
489 if (WARN_ON(!vop->is_enabled))
492 spin_lock_irqsave(&vop->irq_lock, flags);
494 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
495 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
497 spin_unlock_irqrestore(&vop->irq_lock, flags);
500 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
504 if (WARN_ON(!vop->is_enabled))
507 spin_lock_irqsave(&vop->irq_lock, flags);
509 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
511 spin_unlock_irqrestore(&vop->irq_lock, flags);
536 static bool vop_line_flag_irq_is_enabled(struct vop *vop)
541 spin_lock_irqsave(&vop->irq_lock, flags);
543 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
545 spin_unlock_irqrestore(&vop->irq_lock, flags);
550 static void vop_line_flag_irq_enable(struct vop *vop)
554 if (WARN_ON(!vop->is_enabled))
557 spin_lock_irqsave(&vop->irq_lock, flags);
559 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
560 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
562 spin_unlock_irqrestore(&vop->irq_lock, flags);
565 static void vop_line_flag_irq_disable(struct vop *vop)
569 if (WARN_ON(!vop->is_enabled))
572 spin_lock_irqsave(&vop->irq_lock, flags);
574 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
576 spin_unlock_irqrestore(&vop->irq_lock, flags);
579 static int vop_core_clks_enable(struct vop *vop)
583 ret = clk_enable(vop->hclk);
587 ret = clk_enable(vop->aclk);
594 clk_disable(vop->hclk);
598 static void vop_core_clks_disable(struct vop *vop)
600 clk_disable(vop->aclk);
601 clk_disable(vop->hclk);
604 static void vop_win_disable(struct vop *vop, const struct vop_win *vop_win)
609 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
610 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
611 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
612 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
615 VOP_WIN_SET(vop, win, enable, 0);
616 vop->win_enabled &= ~BIT(VOP_WIN_TO_INDEX(vop_win));
621 struct vop *vop = to_vop(crtc);
624 ret = pm_runtime_resume_and_get(vop->dev);
626 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
630 ret = vop_core_clks_enable(vop);
634 ret = clk_enable(vop->dclk);
639 * Slave iommu shares power, irq and clock with vop. It was associated
644 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
646 DRM_DEV_ERROR(vop->dev,
651 spin_lock(&vop->reg_lock);
652 for (i = 0; i < vop->len; i += 4)
653 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
665 for (i = 0; i < vop->data->win_size; i++) {
666 struct vop_win *vop_win = &vop->win[i];
668 vop_win_disable(vop, vop_win);
672 if (vop->data->afbc) {
675 * Disable AFBC and forget there was a vop window with AFBC
677 VOP_AFBC_SET(vop, enable, 0);
682 vop_cfg_done(vop);
684 spin_unlock(&vop->reg_lock);
687 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
689 vop->is_enabled = true;
691 spin_lock(&vop->reg_lock);
693 VOP_REG_SET(vop, common, standby, 1);
695 spin_unlock(&vop->reg_lock);
702 clk_disable(vop->dclk);
704 vop_core_clks_disable(vop);
706 pm_runtime_put_sync(vop->dev);
712 struct vop *vop = to_vop(crtc);
715 spin_lock(&vop->reg_lock);
717 for (i = 0; i < vop->data->win_size; i++) {
718 struct vop_win *vop_win = &vop->win[i];
721 VOP_WIN_SET(vop, win, enable,
722 enabled && (vop->win_enabled & BIT(i)));
724 vop_cfg_done(vop);
726 spin_unlock(&vop->reg_lock);
732 struct vop *vop = to_vop(crtc);
734 WARN_ON(vop->event);
741 mutex_lock(&vop->vop_lock);
752 reinit_completion(&vop->dsp_hold_completion);
753 vop_dsp_hold_valid_irq_enable(vop);
755 spin_lock(&vop->reg_lock);
757 VOP_REG_SET(vop, common, standby, 1);
759 spin_unlock(&vop->reg_lock);
761 if (!wait_for_completion_timeout(&vop->dsp_hold_completion,
765 vop_dsp_hold_valid_irq_disable(vop);
767 vop->is_enabled = false;
770 * vop standby complete, so iommu detach is safe.
772 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
774 clk_disable(vop->dclk);
775 vop_core_clks_disable(vop);
776 pm_runtime_put(vop->dev);
778 mutex_unlock(&vop->vop_lock);
862 struct vop *vop = to_vop(crtc);
864 if (!vop->data->afbc) {
865 DRM_DEBUG_KMS("vop does not support AFBC\n");
897 struct vop *vop = to_vop(old_state->crtc);
902 spin_lock(&vop->reg_lock);
904 vop_win_disable(vop, vop_win);
906 spin_unlock(&vop->reg_lock);
918 struct vop *vop = to_vop(new_state->crtc);
937 * can't update plane when vop is disabled.
942 if (WARN_ON(!vop->is_enabled))
982 spin_lock(&vop->reg_lock);
987 VOP_AFBC_SET(vop, format, afbc_format | AFBC_TILE_16x16);
988 VOP_AFBC_SET(vop, hreg_block_split, 0);
989 VOP_AFBC_SET(vop, win_sel, VOP_WIN_TO_INDEX(vop_win));
990 VOP_AFBC_SET(vop, hdr_ptr, dma_addr);
991 VOP_AFBC_SET(vop, pic_size, act_info);
994 VOP_WIN_SET(vop, win, format, format);
995 VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format));
996 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
997 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
998 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
999 VOP_WIN_SET(vop, win, y_mir_en,
1001 VOP_WIN_SET(vop, win, x_mir_en,
1017 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
1018 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
1021 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
1028 VOP_WIN_SET(vop, win, uv_swap, uv_swap);
1032 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
1036 VOP_WIN_SET(vop, win, act_info, act_info);
1037 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
1038 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
1040 rb_swap = has_rb_swapped(vop->data->version, fb->format->format);
1041 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
1051 VOP_WIN_SET(vop, win, dst_alpha_ctl,
1058 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
1060 VOP_WIN_SET(vop, win, alpha_pre_mul, ALPHA_SRC_PRE_MUL);
1061 VOP_WIN_SET(vop, win, alpha_mode, ALPHA_PER_PIX);
1062 VOP_WIN_SET(vop, win, alpha_en, 1);
1064 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1065 VOP_WIN_SET(vop, win, alpha_en, 0);
1068 VOP_WIN_SET(vop, win, enable, 1);
1069 vop->win_enabled |= BIT(win_index);
1070 spin_unlock(&vop->reg_lock);
1111 struct vop *vop = to_vop(plane->state->crtc);
1124 if (vop->is_enabled) {
1126 spin_lock(&vop->reg_lock);
1127 vop_cfg_done(vop);
1128 spin_unlock(&vop->reg_lock);
1141 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
1142 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1167 struct vop *vop = to_vop(crtc);
1170 if (WARN_ON(!vop->is_enabled))
1173 spin_lock_irqsave(&vop->irq_lock, flags);
1175 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
1176 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
1178 spin_unlock_irqrestore(&vop->irq_lock, flags);
1185 struct vop *vop = to_vop(crtc);
1188 if (WARN_ON(!vop->is_enabled))
1191 spin_lock_irqsave(&vop->irq_lock, flags);
1193 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1195 spin_unlock_irqrestore(&vop->irq_lock, flags);
1201 struct vop *vop = to_vop(crtc);
1203 if (vop->data->max_output.width && mode->hdisplay > vop->data->max_output.width)
1213 struct vop *vop = to_vop(crtc);
1242 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000);
1244 rate = clk_round_rate(vop->dclk,
1251 static bool vop_dsp_lut_is_enabled(struct vop *vop)
1253 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1256 static u32 vop_lut_buffer_index(struct vop *vop)
1258 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);
1261 static void vop_crtc_write_gamma_lut(struct vop *vop, struct drm_crtc *crtc)
1264 unsigned int i, bpc = ilog2(vop->data->lut_size);
1272 writel(word, vop->lut_regs + i * 4);
1276 static void vop_crtc_gamma_set(struct vop *vop, struct drm_crtc *crtc,
1284 if (!vop->lut_regs)
1287 if (!state->gamma_lut || !VOP_HAS_REG(vop, common, update_gamma_lut)) {
1292 spin_lock(&vop->reg_lock);
1293 VOP_REG_SET(vop, common, dsp_lut_en, 0);
1294 vop_cfg_done(vop);
1295 spin_unlock(&vop->reg_lock);
1301 ret = readx_poll_timeout(vop_dsp_lut_is_enabled, vop,
1304 DRM_DEV_ERROR(vop->dev, "display LUT RAM enable timeout!\n");
1315 old_idx = vop_lut_buffer_index(vop);
1318 spin_lock(&vop->reg_lock);
1319 vop_crtc_write_gamma_lut(vop, crtc);
1320 VOP_REG_SET(vop, common, dsp_lut_en, 1);
1321 VOP_REG_SET(vop, common, update_gamma_lut, 1);
1322 vop_cfg_done(vop);
1323 spin_unlock(&vop->reg_lock);
1325 if (VOP_HAS_REG(vop, common, update_gamma_lut)) {
1326 ret = readx_poll_timeout(vop_lut_buffer_index, vop,
1329 DRM_DEV_ERROR(vop->dev, "gamma LUT update timeout!\n");
1337 spin_lock(&vop->reg_lock);
1338 VOP_REG_SET(vop, common, update_gamma_lut, 0);
1339 spin_unlock(&vop->reg_lock);
1350 struct vop *vop = to_vop(crtc);
1358 vop_crtc_gamma_set(vop, crtc, old_crtc_state);
1366 struct vop *vop = to_vop(crtc);
1367 const struct vop_data *vop_data = vop->data;
1390 mutex_lock(&vop->vop_lock);
1392 WARN_ON(vop->event);
1396 mutex_unlock(&vop->vop_lock);
1397 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1404 VOP_REG_SET(vop, output, pin_pol, pin_pol);
1405 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1409 VOP_REG_SET(vop, output, rgb_dclk_pol, 1);
1410 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1411 VOP_REG_SET(vop, output, rgb_en, 1);
1414 VOP_REG_SET(vop, output, edp_dclk_pol, 1);
1415 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1416 VOP_REG_SET(vop, output, edp_en, 1);
1419 VOP_REG_SET(vop, output, hdmi_dclk_pol, 1);
1420 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1421 VOP_REG_SET(vop, output, hdmi_en, 1);
1424 VOP_REG_SET(vop, output, mipi_dclk_pol, 1);
1425 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1426 VOP_REG_SET(vop, output, mipi_en, 1);
1427 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1431 VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1432 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1433 VOP_REG_SET(vop, output, dp_en, 1);
1436 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1441 * if vop is not support RGB10 output, need force RGB10 to RGB888.
1448 VOP_REG_SET(vop, common, pre_dither_down, 1);
1450 VOP_REG_SET(vop, common, pre_dither_down, 0);
1453 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1454 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1455 VOP_REG_SET(vop, common, dither_down_en, 1);
1457 VOP_REG_SET(vop, common, dither_down_en, 0);
1460 VOP_REG_SET(vop, common, out_mode, s->output_mode);
1462 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1465 VOP_REG_SET(vop, modeset, hact_st_end, val);
1466 VOP_REG_SET(vop, modeset, hpost_st_end, val);
1468 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1471 VOP_REG_SET(vop, modeset, vact_st_end, val);
1472 VOP_REG_SET(vop, modeset, vpost_st_end, val);
1474 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1476 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1478 VOP_REG_SET(vop, common, standby, 0);
1479 mutex_unlock(&vop->vop_lock);
1487 vop_crtc_gamma_set(vop, crtc, old_state);
1490 static bool vop_fs_irq_is_pending(struct vop *vop)
1492 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1495 static void vop_wait_for_irq_handler(struct vop *vop)
1508 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1511 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1513 synchronize_irq(vop->irq);
1521 struct vop *vop = to_vop(crtc);
1527 if (vop->lut_regs && crtc_state->color_mgmt_changed &&
1570 struct vop *vop = to_vop(crtc);
1575 if (WARN_ON(!vop->is_enabled))
1578 spin_lock(&vop->reg_lock);
1582 VOP_AFBC_SET(vop, enable, s->enable_afbc);
1583 vop_cfg_done(vop);
1586 if (VOP_HAS_REG(vop, common, dma_stop))
1587 VOP_REG_SET(vop, common, dma_stop, 0);
1589 spin_unlock(&vop->reg_lock);
1596 vop_wait_for_irq_handler(vop);
1601 WARN_ON(vop->event);
1603 vop->event = crtc->state->event;
1618 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1619 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1673 static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1678 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1693 struct vop *vop = to_vop(crtc);
1697 connector = vop_get_edp_connector(vop);
1752 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1755 drm_crtc_vblank_put(&vop->crtc);
1759 static void vop_handle_vblank(struct vop *vop)
1761 struct drm_device *drm = vop->drm_dev;
1762 struct drm_crtc *crtc = &vop->crtc;
1765 if (vop->event) {
1766 drm_crtc_send_vblank_event(crtc, vop->event);
1768 vop->event = NULL;
1772 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1773 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1778 struct vop *vop = data;
1779 struct drm_crtc *crtc = &vop->crtc;
1785 * vop-device is disabled the irq has to be targeted at the iommu.
1787 if (!pm_runtime_get_if_in_use(vop->dev))
1790 if (vop_core_clks_enable(vop)) {
1791 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1799 spin_lock(&vop->irq_lock);
1801 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1804 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1806 spin_unlock(&vop->irq_lock);
1808 /* This is expected for vop iommu irqs, since the irq is shared */
1813 complete(&vop->dsp_hold_completion);
1819 complete(&vop->line_flag_completion);
1826 vop_handle_vblank(vop);
1833 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1837 vop_core_clks_disable(vop);
1839 pm_runtime_put(vop->dev);
1855 static int vop_create_crtc(struct vop *vop)
1857 const struct vop_data *vop_data = vop->data;
1858 struct device *dev = vop->dev;
1859 struct drm_device *drm_dev = vop->drm_dev;
1861 struct drm_crtc *crtc = &vop->crtc;
1872 struct vop_win *vop_win = &vop->win[i];
1879 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1886 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1906 if (vop->lut_regs) {
1916 struct vop_win *vop_win = &vop->win[i];
1923 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1931 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1941 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1947 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1950 init_completion(&vop->dsp_hold_completion);
1951 init_completion(&vop->line_flag_completion);
1956 DRM_DEV_DEBUG_KMS(vop->dev,
1971 static void vop_destroy_crtc(struct vop *vop)
1973 struct drm_crtc *crtc = &vop->crtc;
1974 struct drm_device *drm_dev = vop->drm_dev;
1984 * The planes are "&vop->win[i].base". That means the memory is
1985 * all part of the big "struct vop" chunk of memory. That memory
1998 drm_flip_work_cleanup(&vop->fb_unref_work);
2001 static int vop_initial(struct vop *vop)
2006 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
2007 if (IS_ERR(vop->hclk)) {
2008 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
2009 return PTR_ERR(vop->hclk);
2011 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
2012 if (IS_ERR(vop->aclk)) {
2013 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
2014 return PTR_ERR(vop->aclk);
2016 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
2017 if (IS_ERR(vop->dclk)) {
2018 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
2019 return PTR_ERR(vop->dclk);
2022 ret = pm_runtime_resume_and_get(vop->dev);
2024 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
2028 ret = clk_prepare(vop->dclk);
2030 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
2034 /* Enable both the hclk and aclk to setup the vop */
2035 ret = clk_prepare_enable(vop->hclk);
2037 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
2041 ret = clk_prepare_enable(vop->aclk);
2043 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
2048 * do hclk_reset, reset all vop registers.
2050 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
2052 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
2060 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
2061 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
2063 for (i = 0; i < vop->len; i += sizeof(u32))
2064 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
2066 VOP_REG_SET(vop, misc, global_regdone_en, 1);
2067 VOP_REG_SET(vop, common, dsp_blank, 0);
2069 for (i = 0; i < vop->data->win_size; i++) {
2070 struct vop_win *vop_win = &vop->win[i];
2074 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
2075 vop_win_disable(vop, vop_win);
2076 VOP_WIN_SET(vop, win, gate, 1);
2079 vop_cfg_done(vop);
2084 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
2085 if (IS_ERR(vop->dclk_rst)) {
2086 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
2087 ret = PTR_ERR(vop->dclk_rst);
2090 reset_control_assert(vop->dclk_rst);
2092 reset_control_deassert(vop->dclk_rst);
2094 clk_disable(vop->hclk);
2095 clk_disable(vop->aclk);
2097 vop->is_enabled = false;
2099 pm_runtime_put_sync(vop->dev);
2104 clk_disable_unprepare(vop->aclk);
2106 clk_disable_unprepare(vop->hclk);
2108 clk_unprepare(vop->dclk);
2110 pm_runtime_put_sync(vop->dev);
2115 * Initialize the vop->win array elements.
2117 static void vop_win_init(struct vop *vop)
2119 const struct vop_data *vop_data = vop->data;
2123 struct vop_win *vop_win = &vop->win[i];
2127 vop_win->vop = vop;
2146 struct vop *vop = to_vop(crtc);
2150 if (!crtc || !vop->is_enabled)
2153 mutex_lock(&vop->vop_lock);
2159 if (vop_line_flag_irq_is_enabled(vop)) {
2164 reinit_completion(&vop->line_flag_completion);
2165 vop_line_flag_irq_enable(vop);
2167 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
2169 vop_line_flag_irq_disable(vop);
2172 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
2178 mutex_unlock(&vop->vop_lock);
2188 struct vop *vop;
2196 /* Allocate vop struct and its vop_win array */
2197 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
2199 if (!vop)
2202 vop->dev = dev;
2203 vop->data = vop_data;
2204 vop->drm_dev = drm_dev;
2205 dev_set_drvdata(dev, vop);
2207 vop_win_init(vop);
2210 vop->regs = devm_ioremap_resource(dev, res);
2211 if (IS_ERR(vop->regs))
2212 return PTR_ERR(vop->regs);
2213 vop->len = resource_size(res);
2221 vop->lut_regs = devm_ioremap_resource(dev, res);
2222 if (IS_ERR(vop->lut_regs))
2223 return PTR_ERR(vop->lut_regs);
2226 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
2227 if (!vop->regsbak)
2232 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
2235 vop->irq = (unsigned int)irq;
2237 spin_lock_init(&vop->reg_lock);
2238 spin_lock_init(&vop->irq_lock);
2239 mutex_init(&vop->vop_lock);
2241 ret = vop_create_crtc(vop);
2247 ret = vop_initial(vop);
2250 "cannot initial vop dev - err %d\n", ret);
2254 ret = devm_request_irq(dev, vop->irq, vop_isr,
2255 IRQF_SHARED, dev_name(dev), vop);
2259 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
2260 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0);
2261 if (IS_ERR(vop->rgb)) {
2262 ret = PTR_ERR(vop->rgb);
2273 vop_destroy_crtc(vop);
2279 struct vop *vop = dev_get_drvdata(dev);
2281 if (vop->rgb)
2282 rockchip_rgb_fini(vop->rgb);
2285 vop_destroy_crtc(vop);
2287 clk_unprepare(vop->aclk);
2288 clk_unprepare(vop->hclk);
2289 clk_unprepare(vop->dclk);