Lines Matching +full:0 +full:x4a8
45 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
47 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
50 win->base, ~0, v, #name)
55 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
56 } while (0)
61 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
62 } while (0)
65 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
68 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
75 int i, reg = 0, mask = 0; \
76 for (i = 0; i < vop->data->intr->nintrs; i++) { \
83 } while (0)
103 0, ~0, v, #name); \
104 } while (0)
109 #define AFBC_FMT_RGB565 0x0
110 #define AFBC_FMT_U8U8U8U8 0x5
111 #define AFBC_FMT_U8U8U8 0x4
121 0x4A8, 0x0, 0x662,
122 0x4A8, 0x1E6F, 0x1CBF,
123 0x4A8, 0x812, 0x0,
124 0x321168, 0x0877CF, 0x2EB127
217 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
234 uint32_t i, ret = 0;
235 uint32_t regs = vop_read_reg(vop, 0, reg);
237 for (i = 0; i < vop->data->intr->nintrs; i++) {
354 *vskiplines = 0;
453 true, 0, NULL);
469 dst_w, true, 0, NULL);
509 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
574 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
584 if (ret < 0)
588 if (ret < 0)
591 return 0;
615 VOP_WIN_SET(vop, win, enable, 0);
625 if (ret < 0) {
631 if (WARN_ON(ret < 0))
635 if (WARN_ON(ret < 0))
652 for (i = 0; i < vop->len; i += 4)
665 for (i = 0; i < vop->data->win_size; i++) {
677 VOP_AFBC_SET(vop, enable, 0);
699 return 0;
717 for (i = 0; i < vop->data->win_size; i++) {
802 DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
807 return vop_convert_afbc_format(format) >= 0;
827 return 0;
841 return 0;
844 if (ret < 0)
870 if (ret < 0)
877 fb->offsets[0]);
888 return 0;
950 obj = fb->obj[0];
955 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
958 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
962 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
964 if (fb->format->char_per_block[0])
965 offset = drm_format_info_min_pitch(fb->format, 0,
968 offset = (src->x1 >> 16) * fb->format->cpp[0];
970 offset += (src->y1 >> 16) * fb->pitches[0];
971 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
978 dma_addr += (actual_h - 1) * fb->pitches[0];
988 VOP_AFBC_SET(vop, hreg_block_split, 0);
996 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
1000 (new_state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
1002 (new_state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
1020 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
1050 if (fb->format->has_alpha && win_index > 0) {
1064 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
1065 VOP_WIN_SET(vop, win, alpha_en, 0);
1140 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
1180 return 0;
1193 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1253 return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
1258 return vop_read_reg(vop, 0, &vop->data->common->lut_buffer_index);
1266 for (i = 0; i < crtc->gamma_size; i++) {
1293 VOP_REG_SET(vop, common, dsp_lut_en, 0);
1334 * update_gamma_lut is auto cleared by HW, but write 0 to clear the bit
1338 VOP_REG_SET(vop, common, update_gamma_lut, 0);
1401 BIT(HSYNC_POSITIVE) : 0;
1403 BIT(VSYNC_POSITIVE) : 0;
1405 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1431 VOP_REG_SET(vop, output, dp_dclk_pol, 0);
1450 VOP_REG_SET(vop, common, pre_dither_down, 0);
1457 VOP_REG_SET(vop, common, dither_down_en, 0);
1474 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1478 VOP_REG_SET(vop, common, standby, 0);
1509 !pending, 0, 10 * 1000);
1525 int afbc_planes = 0;
1558 s->enable_afbc = afbc_planes > 0;
1560 return 0;
1587 VOP_REG_SET(vop, common, dma_stop, 0);
1600 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1617 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1701 if (source_name && strcmp(source_name, "auto") == 0)
1715 if (source_name && strcmp(source_name, "auto") != 0)
1719 return 0;
1846 unsigned int flags = 0;
1848 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1849 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1871 for (i = 0; i < vop_data->win_size; i++) {
1880 0, &vop_plane_funcs,
1908 drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
1915 for (i = 0; i < vop_data->win_size; i++) {
1960 return 0;
2023 if (ret < 0) {
2029 if (ret < 0) {
2036 if (ret < 0) {
2042 if (ret < 0) {
2061 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
2063 for (i = 0; i < vop->len; i += sizeof(u32))
2067 VOP_REG_SET(vop, common, dsp_blank, 0);
2069 for (i = 0; i < vop->data->win_size; i++) {
2101 return 0;
2122 for (i = 0; i < vop_data->win_size; i++) {
2148 int ret = 0;
2154 if (mstimeout <= 0) {
2171 if (jiffies_left == 0) {
2209 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2230 irq = platform_get_irq(pdev, 0);
2231 if (irq < 0) {
2248 if (ret < 0) {
2260 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev, 0);
2269 return 0;