Lines Matching +full:rk3066 +full:- +full:hdmi
1 // SPDX-License-Identifier: GPL-2.0
4 * Zheng Yang <zhengyang@rock-chips.com>
68 static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
70 return readl_relaxed(hdmi->regs + offset);
73 static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val)
75 writel_relaxed(val, hdmi->regs + offset);
78 static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset,
81 u8 temp = hdmi_readb(hdmi, offset) & ~msk;
84 hdmi_writeb(hdmi, offset, temp);
87 static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi)
91 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE;
93 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
94 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
97 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
98 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK);
101 static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi)
103 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK;
106 static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode)
111 current_mode = rk3066_hdmi_get_power_mode(hdmi);
113 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode);
114 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode);
129 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode);
132 hdmi_modb(hdmi, HDMI_SYS_CTRL,
135 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
139 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
143 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
157 hdmi->tmdsclk = DEFAULT_PLLA_RATE;
163 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge);
166 drm_err(bridge->dev, "Unsupported infoframe type: %u\n", type);
170 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, HDMI_INFOFRAME_AVI);
180 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge);
184 drm_err(bridge->dev, "Unsupported infoframe type: %u\n", type);
191 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4, buffer[i]);
196 static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi,
203 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
205 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
207 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
210 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3)
216 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value);
219 value = mode->htotal;
220 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF);
221 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF);
223 value = mode->htotal - mode->hdisplay;
224 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF);
225 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF);
227 value = mode->htotal - mode->hsync_start;
228 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF);
229 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF);
231 value = mode->hsync_end - mode->hsync_start;
232 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF);
233 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF);
235 value = mode->vtotal;
236 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF);
237 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF);
239 value = mode->vtotal - mode->vdisplay;
240 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF);
242 value = mode->vtotal - mode->vsync_start + vsync_offset;
243 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF);
245 value = mode->vsync_end - mode->vsync_start;
246 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF);
252 rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value)
254 hdmi_writeb(hdmi, offset, value);
255 hdmi_modb(hdmi, HDMI_SYS_CTRL,
258 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0);
262 static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi)
265 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22);
268 * The semi-public documentation does not describe the hdmi registers
272 if (hdmi->tmdsclk > 100000000) {
273 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E);
274 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
275 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
276 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
277 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA);
278 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1);
279 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
280 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22);
281 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
282 } else if (hdmi->tmdsclk > 50000000) {
283 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06);
284 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
285 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
286 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
287 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA);
288 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3);
289 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
290 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
291 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
293 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02);
294 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
295 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
296 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
297 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2);
298 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2);
299 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
300 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
301 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
305 static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi,
308 struct drm_bridge *bridge = &hdmi->bridge;
315 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
319 return -EINVAL;
321 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc);
323 return -EINVAL;
325 display = &connector->display_info;
326 mode = &new_crtc_state->adjusted_mode;
328 hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
329 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
331 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 ||
332 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 ||
333 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 ||
334 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18)
335 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
337 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
339 hdmi->tmdsclk = mode->clock * 1000;
342 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK,
346 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B)
347 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
350 hdmi_modb(hdmi, HDMI_AV_CTRL1,
352 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1,
356 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20);
358 rk3066_hdmi_config_video_timing(hdmi, mode);
360 if (display->is_hdmi) {
361 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK,
365 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
368 rk3066_hdmi_config_phy(hdmi);
370 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E);
378 rk3066_hdmi_i2c_init(hdmi);
381 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
389 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge);
394 conn_state = drm_atomic_get_new_connector_state(state, hdmi->connector);
398 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
402 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, &hdmi->encoder.encoder);
408 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val);
410 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n",
413 rk3066_hdmi_setup(hdmi, state);
419 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge);
421 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
423 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
424 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2,
426 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
431 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
441 s->output_mode = ROCKCHIP_OUT_MODE_P888;
442 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
455 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge);
457 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
464 struct rk3066_hdmi *hdmi = bridge_to_rk3066_hdmi(bridge);
467 drm_edid = drm_edid_read_ddc(connector, bridge->ddc);
469 dev_dbg(hdmi->dev, "failed to get edid\n");
503 struct rk3066_hdmi *hdmi = dev_id;
507 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A)
508 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B);
510 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1);
512 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt);
515 hdmi->i2c->stat = interrupt;
516 complete(&hdmi->i2c->cmpltn);
527 struct rk3066_hdmi *hdmi = dev_id;
529 drm_helper_hpd_irq_event(hdmi->connector->dev);
534 static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
536 int length = msgs->len;
537 u8 *buf = msgs->buf;
540 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10);
541 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR)
542 return -EAGAIN;
544 while (length--)
545 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR);
550 static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
557 if (msgs->len != 1 ||
558 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
559 return -EINVAL;
561 reinit_completion(&hdmi->i2c->cmpltn);
563 if (msgs->addr == DDC_SEGMENT_ADDR)
564 hdmi->i2c->segment_addr = msgs->buf[0];
565 if (msgs->addr == DDC_ADDR)
566 hdmi->i2c->ddc_addr = msgs->buf[0];
569 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00);
572 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
575 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
583 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap);
584 struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
587 mutex_lock(&i2c->i2c_lock);
589 rk3066_hdmi_i2c_init(hdmi);
591 /* Unmute HDMI EDID interrupt. */
592 hdmi_modb(hdmi, HDMI_INTR_MASK1,
594 i2c->stat = 0;
597 DRM_DEV_DEBUG(hdmi->dev,
602 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]);
604 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]);
613 /* Mute HDMI EDID interrupt. */
614 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
616 mutex_unlock(&i2c->i2c_lock);
631 static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)
637 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
639 return ERR_PTR(-ENOMEM);
641 mutex_init(&i2c->i2c_lock);
642 init_completion(&i2c->cmpltn);
644 adap = &i2c->adap;
645 adap->owner = THIS_MODULE;
646 adap->dev.parent = hdmi->dev;
647 adap->dev.of_node = hdmi->dev->of_node;
648 adap->algo = &rk3066_hdmi_algorithm;
649 strscpy(adap->name, "RK3066 HDMI", sizeof(adap->name));
650 i2c_set_adapdata(adap, hdmi);
652 ret = devm_i2c_add_adapter(hdmi->dev, adap);
654 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n",
655 adap->name);
656 devm_kfree(hdmi->dev, i2c);
660 hdmi->i2c = i2c;
662 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
668 rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
670 struct drm_encoder *encoder = &hdmi->encoder.encoder;
671 struct device *dev = hdmi->dev;
674 encoder->possible_crtcs =
675 drm_of_find_possible_crtcs(drm, dev->of_node);
683 if (encoder->possible_crtcs == 0)
684 return -EPROBE_DEFER;
689 hdmi->bridge.driver_private = hdmi;
690 hdmi->bridge.funcs = &rk3066_hdmi_bridge_funcs;
691 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT |
695 hdmi->bridge.of_node = hdmi->dev->of_node;
696 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
697 hdmi->bridge.vendor = "Rockchip";
698 hdmi->bridge.product = "RK3066 HDMI";
700 hdmi->bridge.ddc = rk3066_hdmi_i2c_adapter(hdmi);
701 if (IS_ERR(hdmi->bridge.ddc))
702 return PTR_ERR(hdmi->bridge.ddc);
704 if (IS_ERR(hdmi->bridge.ddc))
705 return PTR_ERR(hdmi->bridge.ddc);
707 ret = devm_drm_bridge_add(dev, &hdmi->bridge);
711 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
715 hdmi->connector = drm_bridge_connector_init(drm, encoder);
716 if (IS_ERR(hdmi->connector)) {
717 ret = PTR_ERR(hdmi->connector);
718 dev_err(hdmi->dev, "failed to init bridge connector: %d\n", ret);
722 drm_connector_attach_encoder(hdmi->connector, encoder);
732 struct rk3066_hdmi *hdmi;
736 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
737 if (!hdmi)
738 return -ENOMEM;
740 hdmi->dev = dev;
741 hdmi->drm_dev = drm;
742 hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
743 if (IS_ERR(hdmi->regs))
744 return PTR_ERR(hdmi->regs);
750 hdmi->hclk = devm_clk_get(dev, "hclk");
751 if (IS_ERR(hdmi->hclk)) {
752 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n");
753 return PTR_ERR(hdmi->hclk);
756 ret = clk_prepare_enable(hdmi->hclk);
758 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret);
762 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
764 if (IS_ERR(hdmi->grf_regmap)) {
766 ret = PTR_ERR(hdmi->grf_regmap);
771 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25);
773 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
775 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG);
776 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0);
777 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0);
778 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0);
779 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
781 ret = rk3066_hdmi_register(drm, hdmi);
785 dev_set_drvdata(dev, hdmi);
789 dev_name(dev), hdmi);
791 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret);
798 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
800 clk_disable_unprepare(hdmi->hclk);
808 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
810 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
812 clk_disable_unprepare(hdmi->hclk);
822 return component_add(&pdev->dev, &rk3066_hdmi_ops);
827 component_del(&pdev->dev, &rk3066_hdmi_ops);
831 { .compatible = "rockchip,rk3066-hdmi" },
840 .name = "rockchip-rk3066-hdmi",