Lines Matching +full:rk3288 +full:- +full:vop
1 // SPDX-License-Identifier: GPL-2.0-or-later
59 * struct rockchip_hdmi_chip_data - splite the grf setting of kind of chips
61 * @lcdsel_big: reg value of selecting vop big for HDMI
62 * @lcdsel_lit: reg value of selecting vop little for HDMI
200 struct device_node *np = hdmi->dev->of_node; in rockchip_hdmi_parse_dt()
203 hdmi->regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_hdmi_parse_dt()
204 if (IS_ERR(hdmi->regmap)) { in rockchip_hdmi_parse_dt()
205 dev_err(hdmi->dev, "Unable to get rockchip,grf\n"); in rockchip_hdmi_parse_dt()
206 return PTR_ERR(hdmi->regmap); in rockchip_hdmi_parse_dt()
209 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "ref"); in rockchip_hdmi_parse_dt()
210 if (!hdmi->ref_clk) in rockchip_hdmi_parse_dt()
211 hdmi->ref_clk = devm_clk_get_optional_enabled(hdmi->dev, "vpll"); in rockchip_hdmi_parse_dt()
213 if (IS_ERR(hdmi->ref_clk)) { in rockchip_hdmi_parse_dt()
214 ret = PTR_ERR(hdmi->ref_clk); in rockchip_hdmi_parse_dt()
215 return dev_err_probe(hdmi->dev, ret, "failed to get reference clock\n"); in rockchip_hdmi_parse_dt()
218 hdmi->grf_clk = devm_clk_get_optional(hdmi->dev, "grf"); in rockchip_hdmi_parse_dt()
219 if (IS_ERR(hdmi->grf_clk)) { in rockchip_hdmi_parse_dt()
220 ret = PTR_ERR(hdmi->grf_clk); in rockchip_hdmi_parse_dt()
221 return dev_err_probe(hdmi->dev, ret, "failed to get grf clock\n"); in rockchip_hdmi_parse_dt()
224 ret = devm_regulator_get_enable(hdmi->dev, "avdd-0v9"); in rockchip_hdmi_parse_dt()
228 ret = devm_regulator_get_enable(hdmi->dev, "avdd-1v8"); in rockchip_hdmi_parse_dt()
239 int pclk = mode->clock * 1000; in dw_hdmi_rockchip_mode_valid()
241 if (hdmi->chip_data->max_tmds_clock && in dw_hdmi_rockchip_mode_valid()
242 mode->clock > hdmi->chip_data->max_tmds_clock) in dw_hdmi_rockchip_mode_valid()
245 if (hdmi->ref_clk) { in dw_hdmi_rockchip_mode_valid()
246 int rpclk = clk_round_rate(hdmi->ref_clk, pclk); in dw_hdmi_rockchip_mode_valid()
248 if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000) in dw_hdmi_rockchip_mode_valid()
252 if (hdmi->hdmiphy_clk) { in dw_hdmi_rockchip_mode_valid()
253 int rpclk = clk_round_rate(hdmi->hdmiphy_clk, pclk); in dw_hdmi_rockchip_mode_valid()
255 if (rpclk < 0 || abs(rpclk - pclk) > pclk / 1000) in dw_hdmi_rockchip_mode_valid()
280 clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000); in dw_hdmi_rockchip_encoder_mode_set()
289 if (hdmi->chip_data->lcdsel_grf_reg < 0) in dw_hdmi_rockchip_encoder_enable()
292 ret = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder); in dw_hdmi_rockchip_encoder_enable()
294 val = hdmi->chip_data->lcdsel_lit; in dw_hdmi_rockchip_encoder_enable()
296 val = hdmi->chip_data->lcdsel_big; in dw_hdmi_rockchip_encoder_enable()
298 ret = clk_prepare_enable(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
300 dev_err(hdmi->dev, "failed to enable grfclk %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
304 ret = regmap_write(hdmi->regmap, hdmi->chip_data->lcdsel_grf_reg, val); in dw_hdmi_rockchip_encoder_enable()
306 dev_err(hdmi->dev, "Could not write to GRF: %d\n", ret); in dw_hdmi_rockchip_encoder_enable()
308 clk_disable_unprepare(hdmi->grf_clk); in dw_hdmi_rockchip_encoder_enable()
309 dev_dbg(hdmi->dev, "vop %s output to hdmi\n", ret ? "LIT" : "BIG"); in dw_hdmi_rockchip_encoder_enable()
319 s->output_mode = ROCKCHIP_OUT_MODE_AAAA; in dw_hdmi_rockchip_encoder_atomic_check()
320 s->output_type = DRM_MODE_CONNECTOR_HDMIA; in dw_hdmi_rockchip_encoder_atomic_check()
341 return phy_power_on(hdmi->phy); in dw_hdmi_rockchip_genphy_init()
348 phy_power_off(hdmi->phy); in dw_hdmi_rockchip_genphy_disable()
357 regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON6, in dw_hdmi_rk3228_setup_hpd()
362 regmap_write(hdmi->regmap, RK3228_GRF_SOC_CON2, in dw_hdmi_rk3228_setup_hpd()
376 regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4, in dw_hdmi_rk3328_read_hpd()
380 regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4, in dw_hdmi_rk3328_read_hpd()
392 /* Enable and map pins to 3V grf-controlled io-voltage */ in dw_hdmi_rk3328_setup_hpd()
393 regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON4, in dw_hdmi_rk3328_setup_hpd()
399 regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON3, in dw_hdmi_rk3328_setup_hpd()
404 regmap_write(hdmi->regmap, RK3328_GRF_SOC_CON2, in dw_hdmi_rk3328_setup_hpd()
421 .lcdsel_grf_reg = -1,
457 .lcdsel_grf_reg = -1,
487 .lcdsel_grf_reg = -1,
501 { .compatible = "rockchip,rk3228-dw-hdmi",
504 { .compatible = "rockchip,rk3288-dw-hdmi",
507 { .compatible = "rockchip,rk3328-dw-hdmi",
510 { .compatible = "rockchip,rk3399-dw-hdmi",
513 { .compatible = "rockchip,rk3568-dw-hdmi",
531 if (!pdev->dev.of_node) in dw_hdmi_rockchip_bind()
532 return -ENODEV; in dw_hdmi_rockchip_bind()
534 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); in dw_hdmi_rockchip_bind()
536 return -ENOMEM; in dw_hdmi_rockchip_bind()
538 match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node); in dw_hdmi_rockchip_bind()
539 plat_data = devm_kmemdup(&pdev->dev, match->data, in dw_hdmi_rockchip_bind()
542 return -ENOMEM; in dw_hdmi_rockchip_bind()
544 hdmi->dev = &pdev->dev; in dw_hdmi_rockchip_bind()
545 hdmi->plat_data = plat_data; in dw_hdmi_rockchip_bind()
546 hdmi->chip_data = plat_data->phy_data; in dw_hdmi_rockchip_bind()
547 plat_data->phy_data = hdmi; in dw_hdmi_rockchip_bind()
548 plat_data->priv_data = hdmi; in dw_hdmi_rockchip_bind()
549 encoder = &hdmi->encoder.encoder; in dw_hdmi_rockchip_bind()
551 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); in dw_hdmi_rockchip_bind()
552 rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder, in dw_hdmi_rockchip_bind()
553 dev->of_node, 0, 0); in dw_hdmi_rockchip_bind()
561 if (encoder->possible_crtcs == 0) in dw_hdmi_rockchip_bind()
562 return -EPROBE_DEFER; in dw_hdmi_rockchip_bind()
566 return dev_err_probe(hdmi->dev, ret, "Unable to parse OF data\n"); in dw_hdmi_rockchip_bind()
569 hdmi->phy = devm_phy_optional_get(dev, "hdmi"); in dw_hdmi_rockchip_bind()
570 if (IS_ERR(hdmi->phy)) { in dw_hdmi_rockchip_bind()
571 ret = PTR_ERR(hdmi->phy); in dw_hdmi_rockchip_bind()
572 return dev_err_probe(hdmi->dev, ret, "failed to get phy\n"); in dw_hdmi_rockchip_bind()
575 if (hdmi->phy) { in dw_hdmi_rockchip_bind()
578 clkspec.np = hdmi->phy->dev.of_node; in dw_hdmi_rockchip_bind()
579 hdmi->hdmiphy_clk = of_clk_get_from_provider(&clkspec); in dw_hdmi_rockchip_bind()
580 if (IS_ERR(hdmi->hdmiphy_clk)) in dw_hdmi_rockchip_bind()
581 hdmi->hdmiphy_clk = NULL; in dw_hdmi_rockchip_bind()
584 if (hdmi->chip_data == &rk3568_chip_data) { in dw_hdmi_rockchip_bind()
585 regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1, in dw_hdmi_rockchip_bind()
595 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); in dw_hdmi_rockchip_bind()
601 if (IS_ERR(hdmi->hdmi)) { in dw_hdmi_rockchip_bind()
602 ret = PTR_ERR(hdmi->hdmi); in dw_hdmi_rockchip_bind()
619 dw_hdmi_unbind(hdmi->hdmi); in dw_hdmi_rockchip_unbind()
620 drm_encoder_cleanup(&hdmi->encoder.encoder); in dw_hdmi_rockchip_unbind()
630 return component_add(&pdev->dev, &dw_hdmi_rockchip_ops); in dw_hdmi_rockchip_probe()
635 component_del(&pdev->dev, &dw_hdmi_rockchip_ops); in dw_hdmi_rockchip_remove()
642 dw_hdmi_resume(hdmi->hdmi); in dw_hdmi_rockchip_resume()
655 .name = "dwhdmi-rockchip",