Lines Matching full:dsi
368 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
370 writel(val, dsi->base + reg); in dsi_write()
373 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_phy_write() argument
382 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
384 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
387 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
389 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
392 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
398 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2bc() argument
400 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
406 static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2ui() argument
408 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
413 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_init() local
416 if (dsi->phy) in dw_mipi_dsi_phy_init()
431 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
433 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
435 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
437 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
441 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
443 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
447 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, in dw_mipi_dsi_phy_init()
453 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, in dw_mipi_dsi_phy_init()
455 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, in dw_mipi_dsi_phy_init()
459 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_phy_init()
462 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
463 INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
464 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
465 LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
473 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
475 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, in dw_mipi_dsi_phy_init()
476 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
478 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, in dw_mipi_dsi_phy_init()
481 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
483 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, in dw_mipi_dsi_phy_init()
486 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, in dw_mipi_dsi_phy_init()
490 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
493 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, in dw_mipi_dsi_phy_init()
498 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
499 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
500 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
501 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); in dw_mipi_dsi_phy_init()
502 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
503 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); in dw_mipi_dsi_phy_init()
504 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
505 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); in dw_mipi_dsi_phy_init()
506 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
507 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
508 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, in dw_mipi_dsi_phy_init()
509 BIT(5) | (ns2bc(dsi, 60) + 7)); in dw_mipi_dsi_phy_init()
511 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
512 TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
513 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
514 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); in dw_mipi_dsi_phy_init()
515 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
516 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); in dw_mipi_dsi_phy_init()
517 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
518 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); in dw_mipi_dsi_phy_init()
519 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, in dw_mipi_dsi_phy_init()
520 BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
522 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
529 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_on() local
532 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); in dw_mipi_dsi_phy_power_on()
534 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); in dw_mipi_dsi_phy_power_on()
538 phy_configure(dsi->phy, &dsi->phy_opts); in dw_mipi_dsi_phy_power_on()
539 phy_power_on(dsi->phy); in dw_mipi_dsi_phy_power_on()
544 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_phy_power_off() local
546 phy_power_off(dsi->phy); in dw_mipi_dsi_phy_power_off()
554 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_get_lane_mbps() local
566 dsi->format = format; in dw_mipi_dsi_get_lane_mbps()
567 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_mbps()
569 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
571 dsi->format); in dw_mipi_dsi_get_lane_mbps()
582 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_mbps()
587 if (dsi->phy) { in dw_mipi_dsi_get_lane_mbps()
590 &dsi->phy_opts.mipi_dphy); in dw_mipi_dsi_get_lane_mbps()
591 dsi->lane_mbps = target_mbps; in dw_mipi_dsi_get_lane_mbps()
592 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
597 fin = clk_get_rate(dsi->pllref_clk); in dw_mipi_dsi_get_lane_mbps()
640 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); in dw_mipi_dsi_get_lane_mbps()
641 *lane_mbps = dsi->lane_mbps; in dw_mipi_dsi_get_lane_mbps()
642 dsi->input_div = best_prediv; in dw_mipi_dsi_get_lane_mbps()
643 dsi->feedback_div = best_fbdiv; in dw_mipi_dsi_get_lane_mbps()
645 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); in dw_mipi_dsi_get_lane_mbps()
737 static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_config() argument
739 if (dsi->cdata->lanecfg1_grf_reg) in dw_mipi_dsi_rockchip_config()
740 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, in dw_mipi_dsi_rockchip_config()
741 dsi->cdata->lanecfg1); in dw_mipi_dsi_rockchip_config()
743 if (dsi->cdata->lanecfg2_grf_reg) in dw_mipi_dsi_rockchip_config()
744 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, in dw_mipi_dsi_rockchip_config()
745 dsi->cdata->lanecfg2); in dw_mipi_dsi_rockchip_config()
747 if (dsi->cdata->enable_grf_reg) in dw_mipi_dsi_rockchip_config()
748 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, in dw_mipi_dsi_rockchip_config()
749 dsi->cdata->enable); in dw_mipi_dsi_rockchip_config()
752 static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_rockchip_set_lcdsel() argument
755 if (dsi->cdata->lcdsel_grf_reg) in dw_mipi_dsi_rockchip_set_lcdsel()
756 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, in dw_mipi_dsi_rockchip_set_lcdsel()
757 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); in dw_mipi_dsi_rockchip_set_lcdsel()
766 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_atomic_check() local
768 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
784 if (dsi->slave) in dw_mipi_dsi_encoder_atomic_check()
792 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); in dw_mipi_dsi_encoder_enable() local
795 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, in dw_mipi_dsi_encoder_enable()
796 &dsi->encoder.encoder); in dw_mipi_dsi_encoder_enable()
805 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
807 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
811 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); in dw_mipi_dsi_encoder_enable()
812 if (dsi->slave) in dw_mipi_dsi_encoder_enable()
813 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); in dw_mipi_dsi_encoder_enable()
815 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
824 static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, in rockchip_dsi_drm_create_encoder() argument
827 struct drm_encoder *encoder = &dsi->encoder.encoder; in rockchip_dsi_drm_create_encoder()
831 dsi->dev->of_node); in rockchip_dsi_drm_create_encoder()
845 *dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) in dw_mipi_dsi_rockchip_find_second() argument
850 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); in dw_mipi_dsi_rockchip_find_second()
852 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); in dw_mipi_dsi_rockchip_find_second()
861 if (node == dsi->dev->of_node) in dw_mipi_dsi_rockchip_find_second()
908 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_bind() local
914 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_bind()
919 master1 = of_property_read_bool(dsi->dev->of_node, in dw_mipi_dsi_rockchip_bind()
925 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); in dw_mipi_dsi_rockchip_bind()
930 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); in dw_mipi_dsi_rockchip_bind()
934 /* we are the slave in dual-DSI */ in dw_mipi_dsi_rockchip_bind()
936 dsi->is_slave = true; in dw_mipi_dsi_rockchip_bind()
940 dsi->slave = dev_get_drvdata(second); in dw_mipi_dsi_rockchip_bind()
941 if (!dsi->slave) { in dw_mipi_dsi_rockchip_bind()
946 dsi->slave->is_slave = true; in dw_mipi_dsi_rockchip_bind()
947 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); in dw_mipi_dsi_rockchip_bind()
951 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_rockchip_bind()
952 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
953 pm_runtime_get_sync(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
955 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
965 * commands over DSI. in dw_mipi_dsi_rockchip_bind()
967 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
969 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_bind()
973 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_bind()
974 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
975 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_bind()
977 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_bind()
979 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); in dw_mipi_dsi_rockchip_bind()
984 rockchip_drm_encoder_set_crtc_endpoint_id(&dsi->encoder, in dw_mipi_dsi_rockchip_bind()
987 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder.encoder); in dw_mipi_dsi_rockchip_bind()
993 dsi->dsi_bound = true; in dw_mipi_dsi_rockchip_bind()
998 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_bind()
1000 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_bind()
1001 if (dsi->slave) in dw_mipi_dsi_rockchip_bind()
1002 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_bind()
1011 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_unbind() local
1013 if (dsi->is_slave) in dw_mipi_dsi_rockchip_unbind()
1016 dsi->dsi_bound = false; in dw_mipi_dsi_rockchip_unbind()
1018 dw_mipi_dsi_unbind(dsi->dmd); in dw_mipi_dsi_rockchip_unbind()
1020 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_rockchip_unbind()
1022 pm_runtime_put(dsi->dev); in dw_mipi_dsi_rockchip_unbind()
1023 if (dsi->slave) in dw_mipi_dsi_rockchip_unbind()
1024 pm_runtime_put(dsi->slave->dev); in dw_mipi_dsi_rockchip_unbind()
1035 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_attach() local
1039 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1041 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_rockchip_host_attach()
1042 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_rockchip_host_attach()
1043 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1047 dsi->usage_mode = DW_DSI_USAGE_DSI; in dw_mipi_dsi_rockchip_host_attach()
1048 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1050 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_attach()
1052 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", in dw_mipi_dsi_rockchip_host_attach()
1057 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_attach()
1075 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1076 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_attach()
1077 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_attach()
1084 struct dw_mipi_dsi_rockchip *dsi = priv_data; in dw_mipi_dsi_rockchip_host_detach() local
1087 second = dw_mipi_dsi_rockchip_find_second(dsi); in dw_mipi_dsi_rockchip_host_detach()
1091 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); in dw_mipi_dsi_rockchip_host_detach()
1093 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1094 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_rockchip_host_detach()
1095 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_host_detach()
1132 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_init() local
1135 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1137 if (dsi->usage_mode != DW_DSI_USAGE_IDLE) { in dw_mipi_dsi_dphy_init()
1138 DRM_DEV_ERROR(dsi->dev, "dsi controller already in use\n"); in dw_mipi_dsi_dphy_init()
1139 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1143 dsi->usage_mode = DW_DSI_USAGE_PHY; in dw_mipi_dsi_dphy_init()
1144 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1146 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1150 if (dsi->cdata->dphy_rx_init) { in dw_mipi_dsi_dphy_init()
1151 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_init()
1155 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1157 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1161 ret = dsi->cdata->dphy_rx_init(phy); in dw_mipi_dsi_dphy_init()
1162 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_init()
1163 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_init()
1171 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_init()
1173 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1174 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_init()
1175 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_init()
1182 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_exit() local
1184 component_del(dsi->dev, &dw_mipi_dsi_rockchip_dphy_ops); in dw_mipi_dsi_dphy_exit()
1186 mutex_lock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1187 dsi->usage_mode = DW_DSI_USAGE_IDLE; in dw_mipi_dsi_dphy_exit()
1188 mutex_unlock(&dsi->usage_mutex); in dw_mipi_dsi_dphy_exit()
1196 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_configure() local
1203 dsi->dphy_config = *config; in dw_mipi_dsi_dphy_configure()
1204 dsi->lane_mbps = div_u64(config->hs_clk_rate, 1000 * 1000 * 1); in dw_mipi_dsi_dphy_configure()
1211 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_on() local
1214 DRM_DEV_DEBUG(dsi->dev, "lanes %d - data_rate_mbps %u\n", in dw_mipi_dsi_dphy_power_on()
1215 dsi->dphy_config.lanes, dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1217 i = max_mbps_to_parameter(dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1219 DRM_DEV_ERROR(dsi->dev, "failed to get parameter for %dmbps clock\n", in dw_mipi_dsi_dphy_power_on()
1220 dsi->lane_mbps); in dw_mipi_dsi_dphy_power_on()
1224 ret = pm_runtime_resume_and_get(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1226 DRM_DEV_ERROR(dsi->dev, "failed to enable device: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1230 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1232 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1236 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1238 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1242 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1244 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1249 if (dsi->cdata->dphy_rx_power_on) { in dw_mipi_dsi_dphy_power_on()
1250 ret = dsi->cdata->dphy_rx_power_on(phy); in dw_mipi_dsi_dphy_power_on()
1252 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy bringup failed: %d\n", ret); in dw_mipi_dsi_dphy_power_on()
1261 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_CLK, 0); in dw_mipi_dsi_dphy_power_on()
1262 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, in dw_mipi_dsi_dphy_power_on()
1264 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_1, 0); in dw_mipi_dsi_dphy_power_on()
1265 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_2, 0); in dw_mipi_dsi_dphy_power_on()
1266 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_3, 0); in dw_mipi_dsi_dphy_power_on()
1269 dw_mipi_dsi_phy_write(dsi, 0x0, 0); in dw_mipi_dsi_dphy_power_on()
1271 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1272 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1277 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_dphy_power_on()
1279 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_on()
1281 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_on()
1283 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_on()
1289 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in dw_mipi_dsi_dphy_power_off() local
1292 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1294 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1298 if (dsi->cdata->dphy_rx_power_off) { in dw_mipi_dsi_dphy_power_off()
1299 ret = dsi->cdata->dphy_rx_power_off(phy); in dw_mipi_dsi_dphy_power_off()
1301 DRM_DEV_ERROR(dsi->dev, "hardware-specific phy shutdown failed: %d\n", ret); in dw_mipi_dsi_dphy_power_off()
1304 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_dphy_power_off()
1305 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_dphy_power_off()
1307 pm_runtime_put(dsi->dev); in dw_mipi_dsi_dphy_power_off()
1322 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_rockchip_resume() local
1326 * Re-configure DSI state, if we were previously initialized. We need in dw_mipi_dsi_rockchip_resume()
1329 if (dsi->dsi_bound) { in dw_mipi_dsi_rockchip_resume()
1330 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1332 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_rockchip_resume()
1336 dw_mipi_dsi_rockchip_config(dsi); in dw_mipi_dsi_rockchip_resume()
1337 if (dsi->slave) in dw_mipi_dsi_rockchip_resume()
1338 dw_mipi_dsi_rockchip_config(dsi->slave); in dw_mipi_dsi_rockchip_resume()
1340 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_rockchip_resume()
1354 struct dw_mipi_dsi_rockchip *dsi; in dw_mipi_dsi_rockchip_probe() local
1361 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in dw_mipi_dsi_rockchip_probe()
1362 if (!dsi) in dw_mipi_dsi_rockchip_probe()
1365 dsi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in dw_mipi_dsi_rockchip_probe()
1366 if (IS_ERR(dsi->base)) { in dw_mipi_dsi_rockchip_probe()
1367 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); in dw_mipi_dsi_rockchip_probe()
1368 return PTR_ERR(dsi->base); in dw_mipi_dsi_rockchip_probe()
1374 dsi->cdata = &cdata[i]; in dw_mipi_dsi_rockchip_probe()
1381 if (!dsi->cdata) { in dw_mipi_dsi_rockchip_probe()
1382 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); in dw_mipi_dsi_rockchip_probe()
1387 dsi->phy = devm_phy_optional_get(dev, "dphy"); in dw_mipi_dsi_rockchip_probe()
1388 if (IS_ERR(dsi->phy)) { in dw_mipi_dsi_rockchip_probe()
1389 ret = PTR_ERR(dsi->phy); in dw_mipi_dsi_rockchip_probe()
1394 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_rockchip_probe()
1395 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_rockchip_probe()
1396 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_rockchip_probe()
1401 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_rockchip_probe()
1402 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_rockchip_probe()
1403 if (dsi->phy) { in dw_mipi_dsi_rockchip_probe()
1408 dsi->pllref_clk = NULL; in dw_mipi_dsi_rockchip_probe()
1410 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_rockchip_probe()
1418 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { in dw_mipi_dsi_rockchip_probe()
1419 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_rockchip_probe()
1420 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_rockchip_probe()
1421 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_rockchip_probe()
1428 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { in dw_mipi_dsi_rockchip_probe()
1429 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_rockchip_probe()
1430 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_rockchip_probe()
1431 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_rockchip_probe()
1437 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in dw_mipi_dsi_rockchip_probe()
1438 if (IS_ERR(dsi->grf_regmap)) { in dw_mipi_dsi_rockchip_probe()
1440 return PTR_ERR(dsi->grf_regmap); in dw_mipi_dsi_rockchip_probe()
1443 dsi->dev = dev; in dw_mipi_dsi_rockchip_probe()
1444 dsi->pdata.base = dsi->base; in dw_mipi_dsi_rockchip_probe()
1445 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; in dw_mipi_dsi_rockchip_probe()
1446 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; in dw_mipi_dsi_rockchip_probe()
1447 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; in dw_mipi_dsi_rockchip_probe()
1448 dsi->pdata.priv_data = dsi; in dw_mipi_dsi_rockchip_probe()
1449 platform_set_drvdata(pdev, dsi); in dw_mipi_dsi_rockchip_probe()
1451 mutex_init(&dsi->usage_mutex); in dw_mipi_dsi_rockchip_probe()
1453 dsi->dphy = devm_phy_create(dev, NULL, &dw_mipi_dsi_dphy_ops); in dw_mipi_dsi_rockchip_probe()
1454 if (IS_ERR(dsi->dphy)) { in dw_mipi_dsi_rockchip_probe()
1456 return PTR_ERR(dsi->dphy); in dw_mipi_dsi_rockchip_probe()
1459 phy_set_drvdata(dsi->dphy, dsi); in dw_mipi_dsi_rockchip_probe()
1464 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); in dw_mipi_dsi_rockchip_probe()
1465 if (IS_ERR(dsi->dmd)) { in dw_mipi_dsi_rockchip_probe()
1466 ret = PTR_ERR(dsi->dmd); in dw_mipi_dsi_rockchip_probe()
1478 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); in dw_mipi_dsi_rockchip_remove() local
1480 dw_mipi_dsi_remove(dsi->dmd); in dw_mipi_dsi_rockchip_remove()
1535 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_init() local
1541 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1543 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1545 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_init()
1547 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_init()
1555 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_on() local
1558 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR); in rk3399_dphy_tx1rx1_power_on()
1561 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1563 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1566 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1568 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1572 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON24, in rk3399_dphy_tx1rx1_power_on()
1574 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1579 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in rk3399_dphy_tx1rx1_power_on()
1583 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_on()
1584 HIWORD_UPDATE(GENMASK(dsi->dphy_config.lanes - 1, 0), in rk3399_dphy_tx1rx1_power_on()
1594 struct dw_mipi_dsi_rockchip *dsi = phy_get_drvdata(phy); in rk3399_dphy_tx1rx1_power_off() local
1596 regmap_write(dsi->grf_regmap, RK3399_GRF_SOC_CON23, in rk3399_dphy_tx1rx1_power_off()
1688 .compatible = "rockchip,px30-mipi-dsi",
1691 .compatible = "rockchip,rk3128-mipi-dsi",
1694 .compatible = "rockchip,rk3288-mipi-dsi",
1697 .compatible = "rockchip,rk3399-mipi-dsi",
1700 .compatible = "rockchip,rk3568-mipi-dsi",
1703 .compatible = "rockchip,rv1126-mipi-dsi",
1716 .name = "dw-mipi-dsi-rockchip",
1718 * For dual-DSI display, one DSI pokes at the other DSI's