Lines Matching +full:audio +full:- +full:video
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chris Zhong <zyw@rock-chips.com>
14 #include "cdn-dp-core.h"
15 #include "cdn-dp-reg.h"
26 writel(clk / 1000000, dp->regs + SW_CLK_H); in cdn_dp_set_fw_clk()
45 writel(val, dp->regs + SOURCE_DPTX_CAR); in cdn_dp_clock_reset()
48 writel(val, dp->regs + SOURCE_PHY_CAR); in cdn_dp_clock_reset()
54 writel(val, dp->regs + SOURCE_PKT_CAR); in cdn_dp_clock_reset()
62 writel(val, dp->regs + SOURCE_AIF_CAR); in cdn_dp_clock_reset()
68 writel(val, dp->regs + SOURCE_CIPHER_CAR); in cdn_dp_clock_reset()
72 writel(val, dp->regs + SOURCE_CRYPTO_CAR); in cdn_dp_clock_reset()
75 writel(0, dp->regs + APB_INT_MASK); in cdn_dp_clock_reset()
82 ret = readx_poll_timeout(readl, dp->regs + MAILBOX_EMPTY_ADDR, in cdn_dp_mailbox_read()
88 return readl(dp->regs + MAILBOX0_RD_DATA) & 0xff; in cdn_dp_mailbox_read()
95 ret = readx_poll_timeout(readl, dp->regs + MAILBOX_FULL_ADDR, in cdp_dp_mailbox_write()
101 writel(val, dp->regs + MAILBOX0_WR_DATA); in cdp_dp_mailbox_write()
135 return -EINVAL; in cdn_dp_mailbox_validate_receive()
273 ret = -EINVAL; in cdn_dp_dpcd_write()
277 DRM_DEV_ERROR(dp->dev, "dpcd write failed: %d\n", ret); in cdn_dp_dpcd_write()
289 dp->regs + APB_CTRL); in cdn_dp_load_firmware()
292 writel(*i_mem++, dp->regs + ADDR_IMEM + i); in cdn_dp_load_firmware()
295 writel(*d_mem++, dp->regs + ADDR_DMEM + i); in cdn_dp_load_firmware()
297 /* un-reset ucpu */ in cdn_dp_load_firmware()
298 writel(0, dp->regs + APB_CTRL); in cdn_dp_load_firmware()
301 ret = readx_poll_timeout(readl, dp->regs + KEEP_ALIVE, in cdn_dp_load_firmware()
304 DRM_DEV_ERROR(dp->dev, "failed to loaded the FW reg = %x\n", in cdn_dp_load_firmware()
306 return -EINVAL; in cdn_dp_load_firmware()
309 reg = readl(dp->regs + VER_L) & 0xff; in cdn_dp_load_firmware()
310 dp->fw_version = reg; in cdn_dp_load_firmware()
311 reg = readl(dp->regs + VER_H) & 0xff; in cdn_dp_load_firmware()
312 dp->fw_version |= reg << 8; in cdn_dp_load_firmware()
313 reg = readl(dp->regs + VER_LIB_L_ADDR) & 0xff; in cdn_dp_load_firmware()
314 dp->fw_version |= reg << 16; in cdn_dp_load_firmware()
315 reg = readl(dp->regs + VER_LIB_H_ADDR) & 0xff; in cdn_dp_load_firmware()
316 dp->fw_version |= reg << 24; in cdn_dp_load_firmware()
318 DRM_DEV_DEBUG(dp->dev, "firmware version: %x\n", dp->fw_version); in cdn_dp_load_firmware()
353 DRM_DEV_ERROR(dp->dev, "set firmware active failed\n"); in cdn_dp_set_firmware_active()
382 DRM_DEV_ERROR(dp->dev, "set host cap failed: %d\n", ret); in cdn_dp_set_host_cap()
398 DRM_DEV_ERROR(dp->dev, "set event config failed: %d\n", ret); in cdn_dp_event_config()
405 return readl(dp->regs + SW_EVENTS0); in cdn_dp_get_event()
430 DRM_DEV_ERROR(dp->dev, "get hpd status failed: %d\n", ret); in cdn_dp_get_hpd_status()
469 DRM_DEV_ERROR(dp->dev, "get block[%d] edid failed: %d\n", block, in cdn_dp_get_edid_block()
511 ret = -ETIMEDOUT; in cdn_dp_training_start()
514 DRM_DEV_ERROR(dp->dev, "training failed: %d\n", ret); in cdn_dp_training_start()
538 dp->max_rate = drm_dp_bw_code_to_link_rate(status[0]); in cdn_dp_get_training_status()
539 dp->max_lanes = status[1]; in cdn_dp_get_training_status()
543 DRM_DEV_ERROR(dp->dev, "get training status failed: %d\n", ret); in cdn_dp_get_training_status()
553 DRM_DEV_ERROR(dp->dev, "Failed to start training %d\n", ret); in cdn_dp_train_link()
559 DRM_DEV_ERROR(dp->dev, "Failed to get training stat %d\n", ret); in cdn_dp_train_link()
563 DRM_DEV_DEBUG_KMS(dp->dev, "rate:0x%x, lanes:%d\n", dp->max_rate, in cdn_dp_train_link()
564 dp->max_lanes); in cdn_dp_train_link()
578 DRM_DEV_ERROR(dp->dev, "set video status failed: %d\n", ret); in cdn_dp_set_video_status()
583 static int cdn_dp_get_msa_misc(struct video_info *video, in cdn_dp_get_msa_misc() argument
589 switch (video->color_fmt) { in cdn_dp_get_msa_misc()
606 switch (video->color_depth) { in cdn_dp_get_msa_misc()
625 ((video->color_fmt == Y_ONLY) ? (1 << 14) : 0); in cdn_dp_get_msa_misc()
632 struct video_info *video = &dp->video_info; in cdn_dp_config_video() local
633 struct drm_display_mode *mode = &dp->mode; in cdn_dp_config_video()
639 bit_per_pix = (video->color_fmt == YCBCR_4_2_2) ? in cdn_dp_config_video()
640 (video->color_depth * 2) : (video->color_depth * 3); in cdn_dp_config_video()
642 link_rate = dp->max_rate / 1000; in cdn_dp_config_video()
661 symbol = (u64)tu_size_reg * mode->clock * bit_per_pix; in cdn_dp_config_video()
662 do_div(symbol, dp->max_lanes * link_rate * 8); in cdn_dp_config_video()
665 ret = -EINVAL; in cdn_dp_config_video()
666 DRM_DEV_ERROR(dp->dev, in cdn_dp_config_video()
668 mode->clock, dp->max_lanes, link_rate); in cdn_dp_config_video()
671 } while ((symbol <= 1) || (tu_size_reg - symbol < 4) || in cdn_dp_config_video()
681 val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; in cdn_dp_config_video()
682 val /= (dp->max_lanes * link_rate); in cdn_dp_config_video()
683 val = div_u64(8 * (symbol + 1), bit_per_pix) - val; in cdn_dp_config_video()
687 switch (video->color_depth) { in cdn_dp_config_video()
705 val += video->color_fmt << 8; in cdn_dp_config_video()
710 val = video->h_sync_polarity ? DP_FRAMER_SP_HSP : 0; in cdn_dp_config_video()
711 val |= video->v_sync_polarity ? DP_FRAMER_SP_VSP : 0; in cdn_dp_config_video()
716 val = (mode->hsync_start - mode->hdisplay) << 16; in cdn_dp_config_video()
717 val |= mode->htotal - mode->hsync_end; in cdn_dp_config_video()
722 val = mode->hdisplay * bit_per_pix / 8; in cdn_dp_config_video()
727 val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16); in cdn_dp_config_video()
732 val = mode->hsync_end - mode->hsync_start; in cdn_dp_config_video()
733 val |= (mode->hdisplay << 16) | (video->h_sync_polarity << 15); in cdn_dp_config_video()
738 val = mode->vtotal; in cdn_dp_config_video()
739 val |= (mode->vtotal - mode->vsync_start) << 16; in cdn_dp_config_video()
744 val = mode->vsync_end - mode->vsync_start; in cdn_dp_config_video()
745 val |= (mode->vdisplay << 16) | (video->v_sync_polarity << 15); in cdn_dp_config_video()
750 val = cdn_dp_get_msa_misc(video, mode); in cdn_dp_config_video()
759 val = mode->hsync_end - mode->hsync_start; in cdn_dp_config_video()
760 val |= mode->hdisplay << 16; in cdn_dp_config_video()
765 val = mode->vdisplay; in cdn_dp_config_video()
766 val |= (mode->vtotal - mode->vsync_start) << 16; in cdn_dp_config_video()
771 val = mode->vtotal; in cdn_dp_config_video()
780 DRM_DEV_ERROR(dp->dev, "config video failed: %d\n", ret); in cdn_dp_config_video()
784 int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio) in cdn_dp_audio_stop() argument
790 DRM_DEV_ERROR(dp->dev, "audio stop failed: %d\n", ret); in cdn_dp_audio_stop()
794 writel(0, dp->regs + SPDIF_CTRL_ADDR); in cdn_dp_audio_stop()
796 /* clearn the audio config and reset */ in cdn_dp_audio_stop()
797 writel(0, dp->regs + AUDIO_SRC_CNTL); in cdn_dp_audio_stop()
798 writel(0, dp->regs + AUDIO_SRC_CNFG); in cdn_dp_audio_stop()
799 writel(AUDIO_SW_RST, dp->regs + AUDIO_SRC_CNTL); in cdn_dp_audio_stop()
800 writel(0, dp->regs + AUDIO_SRC_CNTL); in cdn_dp_audio_stop()
803 writel(0, dp->regs + SMPL2PKT_CNTL); in cdn_dp_audio_stop()
804 writel(AUDIO_SW_RST, dp->regs + SMPL2PKT_CNTL); in cdn_dp_audio_stop()
805 writel(0, dp->regs + SMPL2PKT_CNTL); in cdn_dp_audio_stop()
808 writel(AUDIO_SW_RST, dp->regs + FIFO_CNTL); in cdn_dp_audio_stop()
809 writel(0, dp->regs + FIFO_CNTL); in cdn_dp_audio_stop()
811 if (audio->format == AFMT_SPDIF) in cdn_dp_audio_stop()
812 clk_disable_unprepare(dp->spdif_clk); in cdn_dp_audio_stop()
823 DRM_DEV_ERROR(dp->dev, "audio mute failed: %d\n", ret); in cdn_dp_audio_mute()
829 struct audio_info *audio) in cdn_dp_audio_config_i2s() argument
834 if (audio->channels == 2) { in cdn_dp_audio_config_i2s()
835 if (dp->max_lanes == 1) in cdn_dp_audio_config_i2s()
841 } else if (audio->channels == 4) { in cdn_dp_audio_config_i2s()
845 writel(0x0, dp->regs + SPDIF_CTRL_ADDR); in cdn_dp_audio_config_i2s()
847 writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL); in cdn_dp_audio_config_i2s()
849 val = MAX_NUM_CH(audio->channels); in cdn_dp_audio_config_i2s()
850 val |= NUM_OF_I2S_PORTS(audio->channels); in cdn_dp_audio_config_i2s()
853 writel(val, dp->regs + SMPL2PKT_CNFG); in cdn_dp_audio_config_i2s()
855 if (audio->sample_width == 16) in cdn_dp_audio_config_i2s()
857 else if (audio->sample_width == 24) in cdn_dp_audio_config_i2s()
862 val |= AUDIO_CH_NUM(audio->channels); in cdn_dp_audio_config_i2s()
865 writel(val, dp->regs + AUDIO_SRC_CNFG); in cdn_dp_audio_config_i2s()
867 for (i = 0; i < (audio->channels + 1) / 2; i++) { in cdn_dp_audio_config_i2s()
868 if (audio->sample_width == 16) in cdn_dp_audio_config_i2s()
870 else if (audio->sample_width == 24) in cdn_dp_audio_config_i2s()
874 writel(val, dp->regs + STTS_BIT_CH(i)); in cdn_dp_audio_config_i2s()
877 switch (audio->sample_rate) { in cdn_dp_audio_config_i2s()
908 writel(val, dp->regs + COM_CH_STTS_BITS); in cdn_dp_audio_config_i2s()
910 writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL); in cdn_dp_audio_config_i2s()
911 writel(I2S_DEC_START, dp->regs + AUDIO_SRC_CNTL); in cdn_dp_audio_config_i2s()
918 writel(SYNC_WR_TO_CH_ZERO, dp->regs + FIFO_CNTL); in cdn_dp_audio_config_spdif()
921 writel(val, dp->regs + SMPL2PKT_CNFG); in cdn_dp_audio_config_spdif()
922 writel(SMPL2PKT_EN, dp->regs + SMPL2PKT_CNTL); in cdn_dp_audio_config_spdif()
925 writel(val, dp->regs + SPDIF_CTRL_ADDR); in cdn_dp_audio_config_spdif()
927 clk_prepare_enable(dp->spdif_clk); in cdn_dp_audio_config_spdif()
928 clk_set_rate(dp->spdif_clk, CDN_DP_SPDIF_CLK); in cdn_dp_audio_config_spdif()
931 int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio) in cdn_dp_audio_config() argument
936 if (audio->format == AFMT_SPDIF) { in cdn_dp_audio_config()
937 reset_control_assert(dp->spdif_rst); in cdn_dp_audio_config()
938 reset_control_deassert(dp->spdif_rst); in cdn_dp_audio_config()
949 if (audio->format == AFMT_I2S) in cdn_dp_audio_config()
950 cdn_dp_audio_config_i2s(dp, audio); in cdn_dp_audio_config()
951 else if (audio->format == AFMT_SPDIF) in cdn_dp_audio_config()
958 DRM_DEV_ERROR(dp->dev, "audio config failed: %d\n", ret); in cdn_dp_audio_config()