32  * uvd_v2_2_fence_emit - emit an fence & trap command
37  * Write a fence and a trap command to the ring.
42 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in uvd_v2_2_fence_emit()  local
43 	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;  in uvd_v2_2_fence_emit()
45 	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));  in uvd_v2_2_fence_emit()
46 	radeon_ring_write(ring, fence->seq);  in uvd_v2_2_fence_emit()
47 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v2_2_fence_emit()
48 	radeon_ring_write(ring, lower_32_bits(addr));  in uvd_v2_2_fence_emit()
49 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v2_2_fence_emit()
50 	radeon_ring_write(ring, upper_32_bits(addr) & 0xff);  in uvd_v2_2_fence_emit()
51 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v2_2_fence_emit()
52 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
54 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v2_2_fence_emit()
55 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
56 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v2_2_fence_emit()
57 	radeon_ring_write(ring, 0);  in uvd_v2_2_fence_emit()
58 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v2_2_fence_emit()
59 	radeon_ring_write(ring, 2);  in uvd_v2_2_fence_emit()
63  * uvd_v2_2_semaphore_emit - emit semaphore command
66  * @ring: radeon_ring pointer
70  * Emit a semaphore command (either wait or signal) to the UVD ring.
73 			     struct radeon_ring *ring,  in uvd_v2_2_semaphore_emit()  argument
77 	uint64_t addr = semaphore->gpu_addr;  in uvd_v2_2_semaphore_emit()
79 	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));  in uvd_v2_2_semaphore_emit()
80 	radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);  in uvd_v2_2_semaphore_emit()
82 	radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));  in uvd_v2_2_semaphore_emit()
83 	radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);  in uvd_v2_2_semaphore_emit()
85 	radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));  in uvd_v2_2_semaphore_emit()
86 	radeon_ring_write(ring, emit_wait ? 1 : 0);  in uvd_v2_2_semaphore_emit()
92  * uvd_v2_2_resume - memory controller programming
105 	if (rdev->family == CHIP_RV770)  in uvd_v2_2_resume()
112 	/* program the VCPU memory controller bits 0-27 */  in uvd_v2_2_resume()
113 	addr = rdev->uvd.gpu_addr >> 3;  in uvd_v2_2_resume()
114 	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3;  in uvd_v2_2_resume()
119 	size = RADEON_UVD_HEAP_SIZE >> 3;  in uvd_v2_2_resume()
125 	       (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;  in uvd_v2_2_resume()
129 	/* bits 28-31 */  in uvd_v2_2_resume()
130 	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;  in uvd_v2_2_resume()
133 	/* bits 32-39 */  in uvd_v2_2_resume()
134 	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;  in uvd_v2_2_resume()
138 	switch (rdev->family) {  in uvd_v2_2_resume()
140 		return -EINVAL;  in uvd_v2_2_resume()