32  * uvd_v1_0_get_rptr - get read pointer
35  * @ring: radeon_ring pointer
40 			   struct radeon_ring *ring)  in uvd_v1_0_get_rptr()  argument
46  * uvd_v1_0_get_wptr - get write pointer
49  * @ring: radeon_ring pointer
54 			   struct radeon_ring *ring)  in uvd_v1_0_get_wptr()  argument
60  * uvd_v1_0_set_wptr - set write pointer
63  * @ring: radeon_ring pointer
68 		       struct radeon_ring *ring)  in uvd_v1_0_set_wptr()  argument
70 	WREG32(UVD_RBC_RB_WPTR, ring->wptr);  in uvd_v1_0_set_wptr()
74  * uvd_v1_0_fence_emit - emit an fence & trap command
79  * Write a fence and a trap command to the ring.
84 	struct radeon_ring *ring = &rdev->ring[fence->ring];  in uvd_v1_0_fence_emit()  local
85 	uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;  in uvd_v1_0_fence_emit()
87 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v1_0_fence_emit()
88 	radeon_ring_write(ring, addr & 0xffffffff);  in uvd_v1_0_fence_emit()
89 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v1_0_fence_emit()
90 	radeon_ring_write(ring, fence->seq);  in uvd_v1_0_fence_emit()
91 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v1_0_fence_emit()
92 	radeon_ring_write(ring, 0);  in uvd_v1_0_fence_emit()
94 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));  in uvd_v1_0_fence_emit()
95 	radeon_ring_write(ring, 0);  in uvd_v1_0_fence_emit()
96 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));  in uvd_v1_0_fence_emit()
97 	radeon_ring_write(ring, 0);  in uvd_v1_0_fence_emit()
98 	radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));  in uvd_v1_0_fence_emit()
99 	radeon_ring_write(ring, 2);  in uvd_v1_0_fence_emit()
104  * uvd_v1_0_resume - memory controller programming
120 	/* program the VCPU memory controller bits 0-27 */  in uvd_v1_0_resume()
121 	addr = (rdev->uvd.gpu_addr >> 3) + 16;  in uvd_v1_0_resume()
122 	size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size) >> 3;  in uvd_v1_0_resume()
127 	size = RADEON_UVD_HEAP_SIZE >> 3;  in uvd_v1_0_resume()
133 	       (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3;  in uvd_v1_0_resume()
137 	/* bits 28-31 */  in uvd_v1_0_resume()
138 	addr = (rdev->uvd.gpu_addr >> 28) & 0xF;  in uvd_v1_0_resume()
141 	/* bits 32-39 */  in uvd_v1_0_resume()
142 	addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;  in uvd_v1_0_resume()
145 	WREG32(UVD_FW_START, *((uint32_t *)rdev->uvd.cpu_addr));  in uvd_v1_0_resume()
151  * uvd_v1_0_init - start and test UVD block
159 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_init()  local
164 	if (rdev->family < CHIP_RV740)  in uvd_v1_0_init()
173 	ring->ready = true;  in uvd_v1_0_init()
174 	r = radeon_ring_test(rdev, R600_RING_TYPE_UVD_INDEX, ring);  in uvd_v1_0_init()
176 		ring->ready = false;  in uvd_v1_0_init()
180 	r = radeon_ring_lock(rdev, ring, 10);  in uvd_v1_0_init()
182 		DRM_ERROR("radeon: ring failed to lock UVD ring (%d).\n", r);  in uvd_v1_0_init()
187 	radeon_ring_write(ring, tmp);  in uvd_v1_0_init()
188 	radeon_ring_write(ring, 0xFFFFF);  in uvd_v1_0_init()
191 	radeon_ring_write(ring, tmp);  in uvd_v1_0_init()
192 	radeon_ring_write(ring, 0xFFFFF);  in uvd_v1_0_init()
195 	radeon_ring_write(ring, tmp);  in uvd_v1_0_init()
196 	radeon_ring_write(ring, 0xFFFFF);  in uvd_v1_0_init()
199 	radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0));  in uvd_v1_0_init()
200 	radeon_ring_write(ring, 0x8);  in uvd_v1_0_init()
202 	radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));  in uvd_v1_0_init()
203 	radeon_ring_write(ring, 3);  in uvd_v1_0_init()
205 	radeon_ring_unlock_commit(rdev, ring, false);  in uvd_v1_0_init()
212 		switch (rdev->family) {  in uvd_v1_0_init()
242  * uvd_v1_0_fini - stop the hardware block
246  * Stop the UVD block, mark ring as not ready any more
250 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_fini()  local
253 	ring->ready = false;  in uvd_v1_0_fini()
257  * uvd_v1_0_start - start UVD block
265 	struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in uvd_v1_0_start()  local
281 	WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));  in uvd_v1_0_start()
323 	WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));  in uvd_v1_0_start()
346 		r = -1;  in uvd_v1_0_start()
355 	WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));  in uvd_v1_0_start()
363 	/* program the 4GB memory segment for rptr and ring buffer */  in uvd_v1_0_start()
364 	WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |  in uvd_v1_0_start()
367 	/* Initialize the ring buffer's read and write pointers */  in uvd_v1_0_start()
370 	ring->wptr = RREG32(UVD_RBC_RB_RPTR);  in uvd_v1_0_start()
371 	WREG32(UVD_RBC_RB_WPTR, ring->wptr);  in uvd_v1_0_start()
373 	/* set the ring address */  in uvd_v1_0_start()
374 	WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);  in uvd_v1_0_start()
376 	/* Set ring buffer size */  in uvd_v1_0_start()
377 	rb_bufsz = order_base_2(ring->ring_size);  in uvd_v1_0_start()
385  * uvd_v1_0_stop - stop UVD block
398 	WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));  in uvd_v1_0_stop()
410 	WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));  in uvd_v1_0_stop()
414  * uvd_v1_0_ring_test - register write test
417  * @ring: radeon_ring pointer
421 int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)  in uvd_v1_0_ring_test()  argument
428 	r = radeon_ring_lock(rdev, ring, 3);  in uvd_v1_0_ring_test()
430 		DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n",  in uvd_v1_0_ring_test()
431 			  ring->idx, r);  in uvd_v1_0_ring_test()
434 	radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));  in uvd_v1_0_ring_test()
435 	radeon_ring_write(ring, 0xDEADBEEF);  in uvd_v1_0_ring_test()
436 	radeon_ring_unlock_commit(rdev, ring, false);  in uvd_v1_0_ring_test()
437 	for (i = 0; i < rdev->usec_timeout; i++) {  in uvd_v1_0_ring_test()
444 	if (i < rdev->usec_timeout) {  in uvd_v1_0_ring_test()
445 		DRM_INFO("ring test on %d succeeded in %d usecs\n",  in uvd_v1_0_ring_test()
446 			 ring->idx, i);  in uvd_v1_0_ring_test()
448 		DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",  in uvd_v1_0_ring_test()
449 			  ring->idx, tmp);  in uvd_v1_0_ring_test()
450 		r = -EINVAL;  in uvd_v1_0_ring_test()
456  * uvd_v1_0_semaphore_emit - emit semaphore command
459  * @ring: radeon_ring pointer
463  * Emit a semaphore command (either wait or signal) to the UVD ring.
466 			     struct radeon_ring *ring,  in uvd_v1_0_semaphore_emit()  argument
475  * uvd_v1_0_ib_execute - execute indirect buffer
480  * Write ring commands to execute the indirect buffer
484 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in uvd_v1_0_ib_execute()  local
486 	radeon_ring_write(ring, PACKET0(UVD_RBC_IB_BASE, 0));  in uvd_v1_0_ib_execute()
487 	radeon_ring_write(ring, ib->gpu_addr);  in uvd_v1_0_ib_execute()
488 	radeon_ring_write(ring, PACKET0(UVD_RBC_IB_SIZE, 0));  in uvd_v1_0_ib_execute()
489 	radeon_ring_write(ring, ib->length_dw);  in uvd_v1_0_ib_execute()
493  * uvd_v1_0_ib_test - test ib execution
496  * @ring: radeon_ring pointer
500 int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)  in uvd_v1_0_ib_test()  argument
505 	if (rdev->family < CHIP_RV740)  in uvd_v1_0_ib_test()
514 	r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);  in uvd_v1_0_ib_test()
520 	r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);  in uvd_v1_0_ib_test()
533 		r = -ETIMEDOUT;  in uvd_v1_0_ib_test()
537 	DRM_INFO("ib test on ring %d succeeded\n",  ring->idx);  in uvd_v1_0_ib_test()