Lines Matching refs:uint8_t
54 uint8_t DisplayPhy1Config;
55 uint8_t DisplayPhy2Config;
56 uint8_t DisplayPhy3Config;
57 uint8_t DisplayPhy4Config;
59 uint8_t DisplayPhy5Config;
60 uint8_t DisplayPhy6Config;
61 uint8_t DisplayPhy7Config;
62 uint8_t DisplayPhy8Config;
68 uint8_t SClkDpmEnabledLevels;
69 uint8_t MClkDpmEnabledLevels;
70 uint8_t LClkDpmEnabledLevels;
71 uint8_t PCIeDpmEnabledLevels;
73 uint8_t UVDDpmEnabledLevels;
74 uint8_t SAMUDpmEnabledLevels;
75 uint8_t ACPDpmEnabledLevels;
76 uint8_t VCEDpmEnabledLevels;
95 uint8_t Smio;
96 uint8_t padding;
108 uint8_t padding1[2];
117 uint8_t SclkDid;
118 uint8_t DisplayWatermark;
119 uint8_t EnabledForActivity;
120 uint8_t EnabledForThrottle;
121 uint8_t UpH;
122 uint8_t DownH;
123 uint8_t VoltageDownH;
124 uint8_t PowerThrottle;
125 uint8_t DeepSleepDivId;
126 uint8_t padding[3];
136 uint8_t SclkDid;
137 uint8_t DisplayWatermark;
138 uint8_t DeepSleepDivId;
139 uint8_t padding;
156 uint8_t VddcOffsetVid;
157 uint8_t VddcPhase;
171 uint8_t EdcReadEnable;
172 uint8_t EdcWriteEnable;
173 uint8_t RttEnable;
174 uint8_t StutterEnable;
176 uint8_t StrobeEnable;
177 uint8_t StrobeRatio;
178 uint8_t EnabledForThrottle;
179 uint8_t EnabledForActivity;
181 uint8_t UpH;
182 uint8_t DownH;
183 uint8_t VoltageDownH;
184 uint8_t padding;
187 uint8_t DisplayWatermark;
188 uint8_t padding1;
204 uint8_t PcieGenSpeed;
205 uint8_t PcieLaneCount;
206 uint8_t EnabledForActivity;
207 uint8_t Padding;
219 uint8_t McArbBurstTime;
220 uint8_t padding[3];
235 uint8_t MinVddcPhases;
236 uint8_t VclkDivider;
237 uint8_t DclkDivider;
238 uint8_t padding[3];
246 uint8_t MinPhases;
247 uint8_t Divider;
262 uint8_t DisplayWatermark;
263 uint8_t McArbIndex;
264 uint8_t McRegIndex;
265 uint8_t SeqIndex;
266 uint8_t SclkDid;
269 uint8_t PCIeGen;
298 uint8_t GraphicsDpmLevelCount;
299 uint8_t MemoryDpmLevelCount;
300 uint8_t LinkLevelCount;
301 uint8_t UvdLevelCount;
302 uint8_t VceLevelCount;
303 uint8_t AcpLevelCount;
304 uint8_t SamuLevelCount;
305 uint8_t MasterDeepSleepControl;
323 uint8_t UvdBootLevel;
324 uint8_t VceBootLevel;
325 uint8_t AcpBootLevel;
326 uint8_t SamuBootLevel;
328 uint8_t UVDInterval;
329 uint8_t VCEInterval;
330 uint8_t ACPInterval;
331 uint8_t SAMUInterval;
333 uint8_t GraphicsBootLevel;
334 uint8_t GraphicsVoltageChangeEnable;
335 uint8_t GraphicsThermThrottleEnable;
336 uint8_t GraphicsInterval;
338 uint8_t VoltageInterval;
339 uint8_t ThermalInterval;
343 uint8_t MemoryBootLevel;
344 uint8_t MemoryVoltageChangeEnable;
346 uint8_t MemoryInterval;
347 uint8_t MemoryThermThrottleEnable;
353 uint8_t PCIeBootLinkLevel;
354 uint8_t PCIeGenInterval;
355 uint8_t DTEInterval;
356 uint8_t DTEMode;
358 uint8_t SVI2Enable;
359 uint8_t VRHotGpio;
360 uint8_t AcDcGpio;
361 uint8_t ThermGpio;
375 uint8_t DTEAmbientTempBase;
376 uint8_t DTETjOffset;
377 uint8_t GpuTjMax;
378 uint8_t GpuTjHyst;
410 uint8_t last;
411 uint8_t reserved[3];
435 uint8_t TempSrc;
444 uint8_t BapmVddCVidHiSidd[8];
447 uint8_t BapmVddCVidLoSidd[8];
450 uint8_t VddCVid[8];
453 uint8_t SviLoadLineEn;
454 uint8_t SviLoadLineVddC;
455 uint8_t SviLoadLineTrimVddC;
456 uint8_t SviLoadLineOffsetVddC;
460 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
461 uint8_t TDC_MAWt;
464 uint8_t TdcWaterfallCtl;
465 uint8_t LPMLTemperatureMin;
466 uint8_t LPMLTemperatureMax;
467 uint8_t Reserved;
470 uint8_t BapmVddCVidHiSidd2[8];
479 uint8_t GnbLPML[16];
482 uint8_t GnbLPMLMaxVid;
483 uint8_t GnbLPMLMinVid;
484 uint8_t Reserved1[2];