Lines Matching refs:new_ps

6460 	struct radeon_ps *new_ps = &requested_ps;  in si_dpm_pre_set_power_state()  local
6462 ni_update_requested_ps(rdev, new_ps); in si_dpm_pre_set_power_state()
6471 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; in si_power_control_set_level() local
6480 ret = si_populate_smc_tdp_limits(rdev, new_ps); in si_power_control_set_level()
6483 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); in si_power_control_set_level()
6498 struct radeon_ps *new_ps = &eg_pi->requested_rps; in si_dpm_set_power_state() local
6513 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6514 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6515 ret = si_enable_power_containment(rdev, new_ps, false); in si_dpm_set_power_state()
6520 ret = si_enable_smc_cac(rdev, new_ps, false); in si_dpm_set_power_state()
6530 ret = si_upload_sw_state(rdev, new_ps); in si_dpm_set_power_state()
6546 ret = si_upload_mc_reg_table(rdev, new_ps); in si_dpm_set_power_state()
6552 ret = si_program_memory_timing_parameters(rdev, new_ps); in si_dpm_set_power_state()
6557 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6569 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6570 si_set_vce_clock(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6572 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); in si_dpm_set_power_state()
6573 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); in si_dpm_set_power_state()
6578 ret = si_enable_smc_cac(rdev, new_ps, true); in si_dpm_set_power_state()
6583 ret = si_enable_power_containment(rdev, new_ps, true); in si_dpm_set_power_state()
6601 struct radeon_ps *new_ps = &eg_pi->requested_rps; in si_dpm_post_set_power_state() local
6603 ni_update_current_ps(rdev, new_ps); in si_dpm_post_set_power_state()