Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x03ffffff
159 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
160 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
161 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
164 (0x8000 << 16) | (0x98f4 >> 2),
165 0x00000000,
166 (0x8040 << 16) | (0x98f4 >> 2),
167 0x00000000,
168 (0x8000 << 16) | (0xe80 >> 2),
169 0x00000000,
170 (0x8040 << 16) | (0xe80 >> 2),
171 0x00000000,
172 (0x8000 << 16) | (0x89bc >> 2),
173 0x00000000,
174 (0x8040 << 16) | (0x89bc >> 2),
175 0x00000000,
176 (0x8000 << 16) | (0x8c1c >> 2),
177 0x00000000,
178 (0x8040 << 16) | (0x8c1c >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x98f0 >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0xe7c >> 2),
183 0x00000000,
184 (0x8000 << 16) | (0x9148 >> 2),
185 0x00000000,
186 (0x8040 << 16) | (0x9148 >> 2),
187 0x00000000,
188 (0x9c00 << 16) | (0x9150 >> 2),
189 0x00000000,
190 (0x9c00 << 16) | (0x897c >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x8d8c >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0xac54 >> 2),
195 0X00000000,
196 0x3,
197 (0x9c00 << 16) | (0x98f8 >> 2),
198 0x00000000,
199 (0x9c00 << 16) | (0x9910 >> 2),
200 0x00000000,
201 (0x9c00 << 16) | (0x9914 >> 2),
202 0x00000000,
203 (0x9c00 << 16) | (0x9918 >> 2),
204 0x00000000,
205 (0x9c00 << 16) | (0x991c >> 2),
206 0x00000000,
207 (0x9c00 << 16) | (0x9920 >> 2),
208 0x00000000,
209 (0x9c00 << 16) | (0x9924 >> 2),
210 0x00000000,
211 (0x9c00 << 16) | (0x9928 >> 2),
212 0x00000000,
213 (0x9c00 << 16) | (0x992c >> 2),
214 0x00000000,
215 (0x9c00 << 16) | (0x9930 >> 2),
216 0x00000000,
217 (0x9c00 << 16) | (0x9934 >> 2),
218 0x00000000,
219 (0x9c00 << 16) | (0x9938 >> 2),
220 0x00000000,
221 (0x9c00 << 16) | (0x993c >> 2),
222 0x00000000,
223 (0x9c00 << 16) | (0x9940 >> 2),
224 0x00000000,
225 (0x9c00 << 16) | (0x9944 >> 2),
226 0x00000000,
227 (0x9c00 << 16) | (0x9948 >> 2),
228 0x00000000,
229 (0x9c00 << 16) | (0x994c >> 2),
230 0x00000000,
231 (0x9c00 << 16) | (0x9950 >> 2),
232 0x00000000,
233 (0x9c00 << 16) | (0x9954 >> 2),
234 0x00000000,
235 (0x9c00 << 16) | (0x9958 >> 2),
236 0x00000000,
237 (0x9c00 << 16) | (0x995c >> 2),
238 0x00000000,
239 (0x9c00 << 16) | (0x9960 >> 2),
240 0x00000000,
241 (0x9c00 << 16) | (0x9964 >> 2),
242 0x00000000,
243 (0x9c00 << 16) | (0x9968 >> 2),
244 0x00000000,
245 (0x9c00 << 16) | (0x996c >> 2),
246 0x00000000,
247 (0x9c00 << 16) | (0x9970 >> 2),
248 0x00000000,
249 (0x9c00 << 16) | (0x9974 >> 2),
250 0x00000000,
251 (0x9c00 << 16) | (0x9978 >> 2),
252 0x00000000,
253 (0x9c00 << 16) | (0x997c >> 2),
254 0x00000000,
255 (0x9c00 << 16) | (0x9980 >> 2),
256 0x00000000,
257 (0x9c00 << 16) | (0x9984 >> 2),
258 0x00000000,
259 (0x9c00 << 16) | (0x9988 >> 2),
260 0x00000000,
261 (0x9c00 << 16) | (0x998c >> 2),
262 0x00000000,
263 (0x9c00 << 16) | (0x8c00 >> 2),
264 0x00000000,
265 (0x9c00 << 16) | (0x8c14 >> 2),
266 0x00000000,
267 (0x9c00 << 16) | (0x8c04 >> 2),
268 0x00000000,
269 (0x9c00 << 16) | (0x8c08 >> 2),
270 0x00000000,
271 (0x8000 << 16) | (0x9b7c >> 2),
272 0x00000000,
273 (0x8040 << 16) | (0x9b7c >> 2),
274 0x00000000,
275 (0x8000 << 16) | (0xe84 >> 2),
276 0x00000000,
277 (0x8040 << 16) | (0xe84 >> 2),
278 0x00000000,
279 (0x8000 << 16) | (0x89c0 >> 2),
280 0x00000000,
281 (0x8040 << 16) | (0x89c0 >> 2),
282 0x00000000,
283 (0x8000 << 16) | (0x914c >> 2),
284 0x00000000,
285 (0x8040 << 16) | (0x914c >> 2),
286 0x00000000,
287 (0x8000 << 16) | (0x8c20 >> 2),
288 0x00000000,
289 (0x8040 << 16) | (0x8c20 >> 2),
290 0x00000000,
291 (0x8000 << 16) | (0x9354 >> 2),
292 0x00000000,
293 (0x8040 << 16) | (0x9354 >> 2),
294 0x00000000,
295 (0x9c00 << 16) | (0x9060 >> 2),
296 0x00000000,
297 (0x9c00 << 16) | (0x9364 >> 2),
298 0x00000000,
299 (0x9c00 << 16) | (0x9100 >> 2),
300 0x00000000,
301 (0x9c00 << 16) | (0x913c >> 2),
302 0x00000000,
303 (0x8000 << 16) | (0x90e0 >> 2),
304 0x00000000,
305 (0x8000 << 16) | (0x90e4 >> 2),
306 0x00000000,
307 (0x8000 << 16) | (0x90e8 >> 2),
308 0x00000000,
309 (0x8040 << 16) | (0x90e0 >> 2),
310 0x00000000,
311 (0x8040 << 16) | (0x90e4 >> 2),
312 0x00000000,
313 (0x8040 << 16) | (0x90e8 >> 2),
314 0x00000000,
315 (0x9c00 << 16) | (0x8bcc >> 2),
316 0x00000000,
317 (0x9c00 << 16) | (0x8b24 >> 2),
318 0x00000000,
319 (0x9c00 << 16) | (0x88c4 >> 2),
320 0x00000000,
321 (0x9c00 << 16) | (0x8e50 >> 2),
322 0x00000000,
323 (0x9c00 << 16) | (0x8c0c >> 2),
324 0x00000000,
325 (0x9c00 << 16) | (0x8e58 >> 2),
326 0x00000000,
327 (0x9c00 << 16) | (0x8e5c >> 2),
328 0x00000000,
329 (0x9c00 << 16) | (0x9508 >> 2),
330 0x00000000,
331 (0x9c00 << 16) | (0x950c >> 2),
332 0x00000000,
333 (0x9c00 << 16) | (0x9494 >> 2),
334 0x00000000,
335 (0x9c00 << 16) | (0xac0c >> 2),
336 0x00000000,
337 (0x9c00 << 16) | (0xac10 >> 2),
338 0x00000000,
339 (0x9c00 << 16) | (0xac14 >> 2),
340 0x00000000,
341 (0x9c00 << 16) | (0xae00 >> 2),
342 0x00000000,
343 (0x9c00 << 16) | (0xac08 >> 2),
344 0x00000000,
345 (0x9c00 << 16) | (0x88d4 >> 2),
346 0x00000000,
347 (0x9c00 << 16) | (0x88c8 >> 2),
348 0x00000000,
349 (0x9c00 << 16) | (0x88cc >> 2),
350 0x00000000,
351 (0x9c00 << 16) | (0x89b0 >> 2),
352 0x00000000,
353 (0x9c00 << 16) | (0x8b10 >> 2),
354 0x00000000,
355 (0x9c00 << 16) | (0x8a14 >> 2),
356 0x00000000,
357 (0x9c00 << 16) | (0x9830 >> 2),
358 0x00000000,
359 (0x9c00 << 16) | (0x9834 >> 2),
360 0x00000000,
361 (0x9c00 << 16) | (0x9838 >> 2),
362 0x00000000,
363 (0x9c00 << 16) | (0x9a10 >> 2),
364 0x00000000,
365 (0x8000 << 16) | (0x9870 >> 2),
366 0x00000000,
367 (0x8000 << 16) | (0x9874 >> 2),
368 0x00000000,
369 (0x8001 << 16) | (0x9870 >> 2),
370 0x00000000,
371 (0x8001 << 16) | (0x9874 >> 2),
372 0x00000000,
373 (0x8040 << 16) | (0x9870 >> 2),
374 0x00000000,
375 (0x8040 << 16) | (0x9874 >> 2),
376 0x00000000,
377 (0x8041 << 16) | (0x9870 >> 2),
378 0x00000000,
379 (0x8041 << 16) | (0x9874 >> 2),
380 0x00000000,
381 0x00000000
385 0xc424, 0xffffffff, 0x00601005,
386 0xc47c, 0xffffffff, 0x10104040,
387 0xc488, 0xffffffff, 0x0100000a,
388 0xc314, 0xffffffff, 0x00000800,
389 0xc30c, 0xffffffff, 0x800000f4,
390 0xf4a8, 0xffffffff, 0x00000000
394 0x9a10, 0x00010000, 0x00018208,
395 0x9830, 0xffffffff, 0x00000000,
396 0x9834, 0xf00fffff, 0x00000400,
397 0x9838, 0x0002021c, 0x00020200,
398 0xc78, 0x00000080, 0x00000000,
399 0xd030, 0x000300c0, 0x00800040,
400 0xd830, 0x000300c0, 0x00800040,
401 0x5bb0, 0x000000f0, 0x00000070,
402 0x5bc0, 0x00200000, 0x50100000,
403 0x7030, 0x31000311, 0x00000011,
404 0x277c, 0x00000003, 0x000007ff,
405 0x240c, 0x000007ff, 0x00000000,
406 0x8a14, 0xf000001f, 0x00000007,
407 0x8b24, 0xffffffff, 0x00ffffff,
408 0x8b10, 0x0000ff0f, 0x00000000,
409 0x28a4c, 0x07ffffff, 0x4e000000,
410 0x28350, 0x3f3f3fff, 0x2a00126a,
411 0x30, 0x000000ff, 0x0040,
412 0x34, 0x00000040, 0x00004040,
413 0x9100, 0x07ffffff, 0x03000000,
414 0x8e88, 0x01ff1f3f, 0x00000000,
415 0x8e84, 0x01ff1f3f, 0x00000000,
416 0x9060, 0x0000007f, 0x00000020,
417 0x9508, 0x00010000, 0x00010000,
418 0xac14, 0x00000200, 0x000002fb,
419 0xac10, 0xffffffff, 0x0000543b,
420 0xac0c, 0xffffffff, 0xa9210876,
421 0x88d0, 0xffffffff, 0x000fff40,
422 0x88d4, 0x0000001f, 0x00000010,
423 0x1410, 0x20000000, 0x20fffed8,
424 0x15c0, 0x000c0fc0, 0x000c0400
428 0xc64, 0x00000001, 0x00000001
432 0xc424, 0xffffffff, 0x00601004,
433 0xc47c, 0xffffffff, 0x10102020,
434 0xc488, 0xffffffff, 0x01000020,
435 0xc314, 0xffffffff, 0x00000800,
436 0xc30c, 0xffffffff, 0x800000a4
440 0x9a10, 0x00010000, 0x00018208,
441 0x9830, 0xffffffff, 0x00000000,
442 0x9834, 0xf00fffff, 0x00000400,
443 0x9838, 0x0002021c, 0x00020200,
444 0xc78, 0x00000080, 0x00000000,
445 0xd030, 0x000300c0, 0x00800040,
446 0xd830, 0x000300c0, 0x00800040,
447 0x5bb0, 0x000000f0, 0x00000070,
448 0x5bc0, 0x00200000, 0x50100000,
449 0x7030, 0x31000311, 0x00000011,
450 0x2ae4, 0x00073ffe, 0x000022a2,
451 0x240c, 0x000007ff, 0x00000000,
452 0x8a14, 0xf000001f, 0x00000007,
453 0x8b24, 0xffffffff, 0x00ffffff,
454 0x8b10, 0x0000ff0f, 0x00000000,
455 0x28a4c, 0x07ffffff, 0x4e000000,
456 0x28350, 0x3f3f3fff, 0x2a00126a,
457 0x30, 0x000000ff, 0x0040,
458 0x34, 0x00000040, 0x00004040,
459 0x9100, 0x07ffffff, 0x03000000,
460 0x9060, 0x0000007f, 0x00000020,
461 0x9508, 0x00010000, 0x00010000,
462 0xac14, 0x000003ff, 0x000000f7,
463 0xac10, 0xffffffff, 0x00000000,
464 0xac0c, 0xffffffff, 0x32761054,
465 0x88d4, 0x0000001f, 0x00000010,
466 0x15c0, 0x000c0fc0, 0x000c0400
470 0xc424, 0xffffffff, 0x033f1005,
471 0xc47c, 0xffffffff, 0x10808020,
472 0xc488, 0xffffffff, 0x00800008,
473 0xc314, 0xffffffff, 0x00001000,
474 0xc30c, 0xffffffff, 0x80010014
478 0x9a10, 0x00010000, 0x00018208,
479 0x9830, 0xffffffff, 0x00000000,
480 0x9834, 0xf00fffff, 0x00000400,
481 0x9838, 0x0002021c, 0x00020200,
482 0xc78, 0x00000080, 0x00000000,
483 0xd030, 0x000300c0, 0x00800040,
484 0xd030, 0x000300c0, 0x00800040,
485 0xd830, 0x000300c0, 0x00800040,
486 0xd830, 0x000300c0, 0x00800040,
487 0x5bb0, 0x000000f0, 0x00000070,
488 0x5bc0, 0x00200000, 0x50100000,
489 0x7030, 0x31000311, 0x00000011,
490 0x2ae4, 0x00073ffe, 0x000022a2,
491 0x2ae4, 0x00073ffe, 0x000022a2,
492 0x2ae4, 0x00073ffe, 0x000022a2,
493 0x240c, 0x000007ff, 0x00000000,
494 0x240c, 0x000007ff, 0x00000000,
495 0x240c, 0x000007ff, 0x00000000,
496 0x8a14, 0xf000001f, 0x00000007,
497 0x8a14, 0xf000001f, 0x00000007,
498 0x8a14, 0xf000001f, 0x00000007,
499 0x8b24, 0xffffffff, 0x00ffffff,
500 0x8b10, 0x0000ff0f, 0x00000000,
501 0x28a4c, 0x07ffffff, 0x4e000000,
502 0x28350, 0x3f3f3fff, 0x0000124a,
503 0x28350, 0x3f3f3fff, 0x0000124a,
504 0x28350, 0x3f3f3fff, 0x0000124a,
505 0x30, 0x000000ff, 0x0040,
506 0x34, 0x00000040, 0x00004040,
507 0x9100, 0x07ffffff, 0x03000000,
508 0x9100, 0x07ffffff, 0x03000000,
509 0x8e88, 0x01ff1f3f, 0x00000000,
510 0x8e88, 0x01ff1f3f, 0x00000000,
511 0x8e88, 0x01ff1f3f, 0x00000000,
512 0x8e84, 0x01ff1f3f, 0x00000000,
513 0x8e84, 0x01ff1f3f, 0x00000000,
514 0x8e84, 0x01ff1f3f, 0x00000000,
515 0x9060, 0x0000007f, 0x00000020,
516 0x9508, 0x00010000, 0x00010000,
517 0xac14, 0x000003ff, 0x00000003,
518 0xac14, 0x000003ff, 0x00000003,
519 0xac14, 0x000003ff, 0x00000003,
520 0xac10, 0xffffffff, 0x00000000,
521 0xac10, 0xffffffff, 0x00000000,
522 0xac10, 0xffffffff, 0x00000000,
523 0xac0c, 0xffffffff, 0x00001032,
524 0xac0c, 0xffffffff, 0x00001032,
525 0xac0c, 0xffffffff, 0x00001032,
526 0x88d4, 0x0000001f, 0x00000010,
527 0x88d4, 0x0000001f, 0x00000010,
528 0x88d4, 0x0000001f, 0x00000010,
529 0x15c0, 0x000c0fc0, 0x000c0400
533 0xc424, 0xffffffff, 0x00601005,
534 0xc47c, 0xffffffff, 0x10104040,
535 0xc488, 0xffffffff, 0x0100000a,
536 0xc314, 0xffffffff, 0x00000800,
537 0xc30c, 0xffffffff, 0x800000f4
541 0x9a10, 0x00010000, 0x00018208,
542 0x9830, 0xffffffff, 0x00000000,
543 0x9834, 0xf00fffff, 0x00000400,
544 0x9838, 0x0002021c, 0x00020200,
545 0xc78, 0x00000080, 0x00000000,
546 0xd030, 0x000300c0, 0x00800040,
547 0xd830, 0x000300c0, 0x00800040,
548 0x5bb0, 0x000000f0, 0x00000070,
549 0x5bc0, 0x00200000, 0x50100000,
550 0x7030, 0x31000311, 0x00000011,
551 0x2ae4, 0x00073ffe, 0x000022a2,
552 0x240c, 0x000007ff, 0x00000000,
553 0x8a14, 0xf000001f, 0x00000007,
554 0x8b24, 0xffffffff, 0x00ffffff,
555 0x8b10, 0x0000ff0f, 0x00000000,
556 0x28a4c, 0x07ffffff, 0x4e000000,
557 0x28350, 0x3f3f3fff, 0x00000082,
558 0x30, 0x000000ff, 0x0040,
559 0x34, 0x00000040, 0x00004040,
560 0x9100, 0x07ffffff, 0x03000000,
561 0x9060, 0x0000007f, 0x00000020,
562 0x9508, 0x00010000, 0x00010000,
563 0xac14, 0x000003ff, 0x000000f3,
564 0xac10, 0xffffffff, 0x00000000,
565 0xac0c, 0xffffffff, 0x00003210,
566 0x88d4, 0x0000001f, 0x00000010,
567 0x15c0, 0x000c0fc0, 0x000c0400
571 0x9a10, 0x00010000, 0x00018208,
572 0x9830, 0xffffffff, 0x00000000,
573 0x9834, 0xf00fffff, 0x00000400,
574 0x9838, 0x0002021c, 0x00020200,
575 0xd0c0, 0xff000fff, 0x00000100,
576 0xd030, 0x000300c0, 0x00800040,
577 0xd8c0, 0xff000fff, 0x00000100,
578 0xd830, 0x000300c0, 0x00800040,
579 0x2ae4, 0x00073ffe, 0x000022a2,
580 0x240c, 0x000007ff, 0x00000000,
581 0x8a14, 0xf000001f, 0x00000007,
582 0x8b24, 0xffffffff, 0x00ffffff,
583 0x8b10, 0x0000ff0f, 0x00000000,
584 0x28a4c, 0x07ffffff, 0x4e000000,
585 0x28350, 0x3f3f3fff, 0x00000000,
586 0x30, 0x000000ff, 0x0040,
587 0x34, 0x00000040, 0x00004040,
588 0x9100, 0x03e00000, 0x03600000,
589 0x9060, 0x0000007f, 0x00000020,
590 0x9508, 0x00010000, 0x00010000,
591 0xac14, 0x000003ff, 0x000000f1,
592 0xac10, 0xffffffff, 0x00000000,
593 0xac0c, 0xffffffff, 0x00003210,
594 0x88d4, 0x0000001f, 0x00000010,
595 0x15c0, 0x000c0fc0, 0x000c0400
599 0x98f8, 0xffffffff, 0x02010001
603 0xc400, 0xffffffff, 0xfffffffc,
604 0x802c, 0xffffffff, 0xe0000000,
605 0x9a60, 0xffffffff, 0x00000100,
606 0x92a4, 0xffffffff, 0x00000100,
607 0xc164, 0xffffffff, 0x00000100,
608 0x9774, 0xffffffff, 0x00000100,
609 0x8984, 0xffffffff, 0x06000100,
610 0x8a18, 0xffffffff, 0x00000100,
611 0x92a0, 0xffffffff, 0x00000100,
612 0xc380, 0xffffffff, 0x00000100,
613 0x8b28, 0xffffffff, 0x00000100,
614 0x9144, 0xffffffff, 0x00000100,
615 0x8d88, 0xffffffff, 0x00000100,
616 0x8d8c, 0xffffffff, 0x00000100,
617 0x9030, 0xffffffff, 0x00000100,
618 0x9034, 0xffffffff, 0x00000100,
619 0x9038, 0xffffffff, 0x00000100,
620 0x903c, 0xffffffff, 0x00000100,
621 0xad80, 0xffffffff, 0x00000100,
622 0xac54, 0xffffffff, 0x00000100,
623 0x897c, 0xffffffff, 0x06000100,
624 0x9868, 0xffffffff, 0x00000100,
625 0x9510, 0xffffffff, 0x00000100,
626 0xaf04, 0xffffffff, 0x00000100,
627 0xae04, 0xffffffff, 0x00000100,
628 0x949c, 0xffffffff, 0x00000100,
629 0x802c, 0xffffffff, 0xe0000000,
630 0x9160, 0xffffffff, 0x00010000,
631 0x9164, 0xffffffff, 0x00030002,
632 0x9168, 0xffffffff, 0x00040007,
633 0x916c, 0xffffffff, 0x00060005,
634 0x9170, 0xffffffff, 0x00090008,
635 0x9174, 0xffffffff, 0x00020001,
636 0x9178, 0xffffffff, 0x00040003,
637 0x917c, 0xffffffff, 0x00000007,
638 0x9180, 0xffffffff, 0x00060005,
639 0x9184, 0xffffffff, 0x00090008,
640 0x9188, 0xffffffff, 0x00030002,
641 0x918c, 0xffffffff, 0x00050004,
642 0x9190, 0xffffffff, 0x00000008,
643 0x9194, 0xffffffff, 0x00070006,
644 0x9198, 0xffffffff, 0x000a0009,
645 0x919c, 0xffffffff, 0x00040003,
646 0x91a0, 0xffffffff, 0x00060005,
647 0x91a4, 0xffffffff, 0x00000009,
648 0x91a8, 0xffffffff, 0x00080007,
649 0x91ac, 0xffffffff, 0x000b000a,
650 0x91b0, 0xffffffff, 0x00050004,
651 0x91b4, 0xffffffff, 0x00070006,
652 0x91b8, 0xffffffff, 0x0008000b,
653 0x91bc, 0xffffffff, 0x000a0009,
654 0x91c0, 0xffffffff, 0x000d000c,
655 0x91c4, 0xffffffff, 0x00060005,
656 0x91c8, 0xffffffff, 0x00080007,
657 0x91cc, 0xffffffff, 0x0000000b,
658 0x91d0, 0xffffffff, 0x000a0009,
659 0x91d4, 0xffffffff, 0x000d000c,
660 0x91d8, 0xffffffff, 0x00070006,
661 0x91dc, 0xffffffff, 0x00090008,
662 0x91e0, 0xffffffff, 0x0000000c,
663 0x91e4, 0xffffffff, 0x000b000a,
664 0x91e8, 0xffffffff, 0x000e000d,
665 0x91ec, 0xffffffff, 0x00080007,
666 0x91f0, 0xffffffff, 0x000a0009,
667 0x91f4, 0xffffffff, 0x0000000d,
668 0x91f8, 0xffffffff, 0x000c000b,
669 0x91fc, 0xffffffff, 0x000f000e,
670 0x9200, 0xffffffff, 0x00090008,
671 0x9204, 0xffffffff, 0x000b000a,
672 0x9208, 0xffffffff, 0x000c000f,
673 0x920c, 0xffffffff, 0x000e000d,
674 0x9210, 0xffffffff, 0x00110010,
675 0x9214, 0xffffffff, 0x000a0009,
676 0x9218, 0xffffffff, 0x000c000b,
677 0x921c, 0xffffffff, 0x0000000f,
678 0x9220, 0xffffffff, 0x000e000d,
679 0x9224, 0xffffffff, 0x00110010,
680 0x9228, 0xffffffff, 0x000b000a,
681 0x922c, 0xffffffff, 0x000d000c,
682 0x9230, 0xffffffff, 0x00000010,
683 0x9234, 0xffffffff, 0x000f000e,
684 0x9238, 0xffffffff, 0x00120011,
685 0x923c, 0xffffffff, 0x000c000b,
686 0x9240, 0xffffffff, 0x000e000d,
687 0x9244, 0xffffffff, 0x00000011,
688 0x9248, 0xffffffff, 0x0010000f,
689 0x924c, 0xffffffff, 0x00130012,
690 0x9250, 0xffffffff, 0x000d000c,
691 0x9254, 0xffffffff, 0x000f000e,
692 0x9258, 0xffffffff, 0x00100013,
693 0x925c, 0xffffffff, 0x00120011,
694 0x9260, 0xffffffff, 0x00150014,
695 0x9264, 0xffffffff, 0x000e000d,
696 0x9268, 0xffffffff, 0x0010000f,
697 0x926c, 0xffffffff, 0x00000013,
698 0x9270, 0xffffffff, 0x00120011,
699 0x9274, 0xffffffff, 0x00150014,
700 0x9278, 0xffffffff, 0x000f000e,
701 0x927c, 0xffffffff, 0x00110010,
702 0x9280, 0xffffffff, 0x00000014,
703 0x9284, 0xffffffff, 0x00130012,
704 0x9288, 0xffffffff, 0x00160015,
705 0x928c, 0xffffffff, 0x0010000f,
706 0x9290, 0xffffffff, 0x00120011,
707 0x9294, 0xffffffff, 0x00000015,
708 0x9298, 0xffffffff, 0x00140013,
709 0x929c, 0xffffffff, 0x00170016,
710 0x9150, 0xffffffff, 0x96940200,
711 0x8708, 0xffffffff, 0x00900100,
712 0xc478, 0xffffffff, 0x00000080,
713 0xc404, 0xffffffff, 0x0020003f,
714 0x30, 0xffffffff, 0x0000001c,
715 0x34, 0x000f0000, 0x000f0000,
716 0x160c, 0xffffffff, 0x00000100,
717 0x1024, 0xffffffff, 0x00000100,
718 0x102c, 0x00000101, 0x00000000,
719 0x20a8, 0xffffffff, 0x00000104,
720 0x264c, 0x000c0000, 0x000c0000,
721 0x2648, 0x000c0000, 0x000c0000,
722 0x55e4, 0xff000fff, 0x00000100,
723 0x55e8, 0x00000001, 0x00000001,
724 0x2f50, 0x00000001, 0x00000001,
725 0x30cc, 0xc0000fff, 0x00000104,
726 0xc1e4, 0x00000001, 0x00000001,
727 0xd0c0, 0xfffffff0, 0x00000100,
728 0xd8c0, 0xfffffff0, 0x00000100
732 0xc400, 0xffffffff, 0xfffffffc,
733 0x802c, 0xffffffff, 0xe0000000,
734 0x9a60, 0xffffffff, 0x00000100,
735 0x92a4, 0xffffffff, 0x00000100,
736 0xc164, 0xffffffff, 0x00000100,
737 0x9774, 0xffffffff, 0x00000100,
738 0x8984, 0xffffffff, 0x06000100,
739 0x8a18, 0xffffffff, 0x00000100,
740 0x92a0, 0xffffffff, 0x00000100,
741 0xc380, 0xffffffff, 0x00000100,
742 0x8b28, 0xffffffff, 0x00000100,
743 0x9144, 0xffffffff, 0x00000100,
744 0x8d88, 0xffffffff, 0x00000100,
745 0x8d8c, 0xffffffff, 0x00000100,
746 0x9030, 0xffffffff, 0x00000100,
747 0x9034, 0xffffffff, 0x00000100,
748 0x9038, 0xffffffff, 0x00000100,
749 0x903c, 0xffffffff, 0x00000100,
750 0xad80, 0xffffffff, 0x00000100,
751 0xac54, 0xffffffff, 0x00000100,
752 0x897c, 0xffffffff, 0x06000100,
753 0x9868, 0xffffffff, 0x00000100,
754 0x9510, 0xffffffff, 0x00000100,
755 0xaf04, 0xffffffff, 0x00000100,
756 0xae04, 0xffffffff, 0x00000100,
757 0x949c, 0xffffffff, 0x00000100,
758 0x802c, 0xffffffff, 0xe0000000,
759 0x9160, 0xffffffff, 0x00010000,
760 0x9164, 0xffffffff, 0x00030002,
761 0x9168, 0xffffffff, 0x00040007,
762 0x916c, 0xffffffff, 0x00060005,
763 0x9170, 0xffffffff, 0x00090008,
764 0x9174, 0xffffffff, 0x00020001,
765 0x9178, 0xffffffff, 0x00040003,
766 0x917c, 0xffffffff, 0x00000007,
767 0x9180, 0xffffffff, 0x00060005,
768 0x9184, 0xffffffff, 0x00090008,
769 0x9188, 0xffffffff, 0x00030002,
770 0x918c, 0xffffffff, 0x00050004,
771 0x9190, 0xffffffff, 0x00000008,
772 0x9194, 0xffffffff, 0x00070006,
773 0x9198, 0xffffffff, 0x000a0009,
774 0x919c, 0xffffffff, 0x00040003,
775 0x91a0, 0xffffffff, 0x00060005,
776 0x91a4, 0xffffffff, 0x00000009,
777 0x91a8, 0xffffffff, 0x00080007,
778 0x91ac, 0xffffffff, 0x000b000a,
779 0x91b0, 0xffffffff, 0x00050004,
780 0x91b4, 0xffffffff, 0x00070006,
781 0x91b8, 0xffffffff, 0x0008000b,
782 0x91bc, 0xffffffff, 0x000a0009,
783 0x91c0, 0xffffffff, 0x000d000c,
784 0x9200, 0xffffffff, 0x00090008,
785 0x9204, 0xffffffff, 0x000b000a,
786 0x9208, 0xffffffff, 0x000c000f,
787 0x920c, 0xffffffff, 0x000e000d,
788 0x9210, 0xffffffff, 0x00110010,
789 0x9214, 0xffffffff, 0x000a0009,
790 0x9218, 0xffffffff, 0x000c000b,
791 0x921c, 0xffffffff, 0x0000000f,
792 0x9220, 0xffffffff, 0x000e000d,
793 0x9224, 0xffffffff, 0x00110010,
794 0x9228, 0xffffffff, 0x000b000a,
795 0x922c, 0xffffffff, 0x000d000c,
796 0x9230, 0xffffffff, 0x00000010,
797 0x9234, 0xffffffff, 0x000f000e,
798 0x9238, 0xffffffff, 0x00120011,
799 0x923c, 0xffffffff, 0x000c000b,
800 0x9240, 0xffffffff, 0x000e000d,
801 0x9244, 0xffffffff, 0x00000011,
802 0x9248, 0xffffffff, 0x0010000f,
803 0x924c, 0xffffffff, 0x00130012,
804 0x9250, 0xffffffff, 0x000d000c,
805 0x9254, 0xffffffff, 0x000f000e,
806 0x9258, 0xffffffff, 0x00100013,
807 0x925c, 0xffffffff, 0x00120011,
808 0x9260, 0xffffffff, 0x00150014,
809 0x9150, 0xffffffff, 0x96940200,
810 0x8708, 0xffffffff, 0x00900100,
811 0xc478, 0xffffffff, 0x00000080,
812 0xc404, 0xffffffff, 0x0020003f,
813 0x30, 0xffffffff, 0x0000001c,
814 0x34, 0x000f0000, 0x000f0000,
815 0x160c, 0xffffffff, 0x00000100,
816 0x1024, 0xffffffff, 0x00000100,
817 0x102c, 0x00000101, 0x00000000,
818 0x20a8, 0xffffffff, 0x00000104,
819 0x55e4, 0xff000fff, 0x00000100,
820 0x55e8, 0x00000001, 0x00000001,
821 0x2f50, 0x00000001, 0x00000001,
822 0x30cc, 0xc0000fff, 0x00000104,
823 0xc1e4, 0x00000001, 0x00000001,
824 0xd0c0, 0xfffffff0, 0x00000100,
825 0xd8c0, 0xfffffff0, 0x00000100
829 0xc400, 0xffffffff, 0xfffffffc,
830 0x802c, 0xffffffff, 0xe0000000,
831 0x9a60, 0xffffffff, 0x00000100,
832 0x92a4, 0xffffffff, 0x00000100,
833 0xc164, 0xffffffff, 0x00000100,
834 0x9774, 0xffffffff, 0x00000100,
835 0x8984, 0xffffffff, 0x06000100,
836 0x8a18, 0xffffffff, 0x00000100,
837 0x92a0, 0xffffffff, 0x00000100,
838 0xc380, 0xffffffff, 0x00000100,
839 0x8b28, 0xffffffff, 0x00000100,
840 0x9144, 0xffffffff, 0x00000100,
841 0x8d88, 0xffffffff, 0x00000100,
842 0x8d8c, 0xffffffff, 0x00000100,
843 0x9030, 0xffffffff, 0x00000100,
844 0x9034, 0xffffffff, 0x00000100,
845 0x9038, 0xffffffff, 0x00000100,
846 0x903c, 0xffffffff, 0x00000100,
847 0xad80, 0xffffffff, 0x00000100,
848 0xac54, 0xffffffff, 0x00000100,
849 0x897c, 0xffffffff, 0x06000100,
850 0x9868, 0xffffffff, 0x00000100,
851 0x9510, 0xffffffff, 0x00000100,
852 0xaf04, 0xffffffff, 0x00000100,
853 0xae04, 0xffffffff, 0x00000100,
854 0x949c, 0xffffffff, 0x00000100,
855 0x802c, 0xffffffff, 0xe0000000,
856 0x9160, 0xffffffff, 0x00010000,
857 0x9164, 0xffffffff, 0x00030002,
858 0x9168, 0xffffffff, 0x00040007,
859 0x916c, 0xffffffff, 0x00060005,
860 0x9170, 0xffffffff, 0x00090008,
861 0x9174, 0xffffffff, 0x00020001,
862 0x9178, 0xffffffff, 0x00040003,
863 0x917c, 0xffffffff, 0x00000007,
864 0x9180, 0xffffffff, 0x00060005,
865 0x9184, 0xffffffff, 0x00090008,
866 0x9188, 0xffffffff, 0x00030002,
867 0x918c, 0xffffffff, 0x00050004,
868 0x9190, 0xffffffff, 0x00000008,
869 0x9194, 0xffffffff, 0x00070006,
870 0x9198, 0xffffffff, 0x000a0009,
871 0x919c, 0xffffffff, 0x00040003,
872 0x91a0, 0xffffffff, 0x00060005,
873 0x91a4, 0xffffffff, 0x00000009,
874 0x91a8, 0xffffffff, 0x00080007,
875 0x91ac, 0xffffffff, 0x000b000a,
876 0x91b0, 0xffffffff, 0x00050004,
877 0x91b4, 0xffffffff, 0x00070006,
878 0x91b8, 0xffffffff, 0x0008000b,
879 0x91bc, 0xffffffff, 0x000a0009,
880 0x91c0, 0xffffffff, 0x000d000c,
881 0x9200, 0xffffffff, 0x00090008,
882 0x9204, 0xffffffff, 0x000b000a,
883 0x9208, 0xffffffff, 0x000c000f,
884 0x920c, 0xffffffff, 0x000e000d,
885 0x9210, 0xffffffff, 0x00110010,
886 0x9214, 0xffffffff, 0x000a0009,
887 0x9218, 0xffffffff, 0x000c000b,
888 0x921c, 0xffffffff, 0x0000000f,
889 0x9220, 0xffffffff, 0x000e000d,
890 0x9224, 0xffffffff, 0x00110010,
891 0x9228, 0xffffffff, 0x000b000a,
892 0x922c, 0xffffffff, 0x000d000c,
893 0x9230, 0xffffffff, 0x00000010,
894 0x9234, 0xffffffff, 0x000f000e,
895 0x9238, 0xffffffff, 0x00120011,
896 0x923c, 0xffffffff, 0x000c000b,
897 0x9240, 0xffffffff, 0x000e000d,
898 0x9244, 0xffffffff, 0x00000011,
899 0x9248, 0xffffffff, 0x0010000f,
900 0x924c, 0xffffffff, 0x00130012,
901 0x9250, 0xffffffff, 0x000d000c,
902 0x9254, 0xffffffff, 0x000f000e,
903 0x9258, 0xffffffff, 0x00100013,
904 0x925c, 0xffffffff, 0x00120011,
905 0x9260, 0xffffffff, 0x00150014,
906 0x9150, 0xffffffff, 0x96940200,
907 0x8708, 0xffffffff, 0x00900100,
908 0xc478, 0xffffffff, 0x00000080,
909 0xc404, 0xffffffff, 0x0020003f,
910 0x30, 0xffffffff, 0x0000001c,
911 0x34, 0x000f0000, 0x000f0000,
912 0x160c, 0xffffffff, 0x00000100,
913 0x1024, 0xffffffff, 0x00000100,
914 0x102c, 0x00000101, 0x00000000,
915 0x20a8, 0xffffffff, 0x00000104,
916 0x264c, 0x000c0000, 0x000c0000,
917 0x2648, 0x000c0000, 0x000c0000,
918 0x55e4, 0xff000fff, 0x00000100,
919 0x55e8, 0x00000001, 0x00000001,
920 0x2f50, 0x00000001, 0x00000001,
921 0x30cc, 0xc0000fff, 0x00000104,
922 0xc1e4, 0x00000001, 0x00000001,
923 0xd0c0, 0xfffffff0, 0x00000100,
924 0xd8c0, 0xfffffff0, 0x00000100
928 0xc400, 0xffffffff, 0xfffffffc,
929 0x802c, 0xffffffff, 0xe0000000,
930 0x9a60, 0xffffffff, 0x00000100,
931 0x92a4, 0xffffffff, 0x00000100,
932 0xc164, 0xffffffff, 0x00000100,
933 0x9774, 0xffffffff, 0x00000100,
934 0x8984, 0xffffffff, 0x06000100,
935 0x8a18, 0xffffffff, 0x00000100,
936 0x92a0, 0xffffffff, 0x00000100,
937 0xc380, 0xffffffff, 0x00000100,
938 0x8b28, 0xffffffff, 0x00000100,
939 0x9144, 0xffffffff, 0x00000100,
940 0x8d88, 0xffffffff, 0x00000100,
941 0x8d8c, 0xffffffff, 0x00000100,
942 0x9030, 0xffffffff, 0x00000100,
943 0x9034, 0xffffffff, 0x00000100,
944 0x9038, 0xffffffff, 0x00000100,
945 0x903c, 0xffffffff, 0x00000100,
946 0xad80, 0xffffffff, 0x00000100,
947 0xac54, 0xffffffff, 0x00000100,
948 0x897c, 0xffffffff, 0x06000100,
949 0x9868, 0xffffffff, 0x00000100,
950 0x9510, 0xffffffff, 0x00000100,
951 0xaf04, 0xffffffff, 0x00000100,
952 0xae04, 0xffffffff, 0x00000100,
953 0x949c, 0xffffffff, 0x00000100,
954 0x802c, 0xffffffff, 0xe0000000,
955 0x9160, 0xffffffff, 0x00010000,
956 0x9164, 0xffffffff, 0x00030002,
957 0x9168, 0xffffffff, 0x00040007,
958 0x916c, 0xffffffff, 0x00060005,
959 0x9170, 0xffffffff, 0x00090008,
960 0x9174, 0xffffffff, 0x00020001,
961 0x9178, 0xffffffff, 0x00040003,
962 0x917c, 0xffffffff, 0x00000007,
963 0x9180, 0xffffffff, 0x00060005,
964 0x9184, 0xffffffff, 0x00090008,
965 0x9188, 0xffffffff, 0x00030002,
966 0x918c, 0xffffffff, 0x00050004,
967 0x9190, 0xffffffff, 0x00000008,
968 0x9194, 0xffffffff, 0x00070006,
969 0x9198, 0xffffffff, 0x000a0009,
970 0x919c, 0xffffffff, 0x00040003,
971 0x91a0, 0xffffffff, 0x00060005,
972 0x91a4, 0xffffffff, 0x00000009,
973 0x91a8, 0xffffffff, 0x00080007,
974 0x91ac, 0xffffffff, 0x000b000a,
975 0x91b0, 0xffffffff, 0x00050004,
976 0x91b4, 0xffffffff, 0x00070006,
977 0x91b8, 0xffffffff, 0x0008000b,
978 0x91bc, 0xffffffff, 0x000a0009,
979 0x91c0, 0xffffffff, 0x000d000c,
980 0x91c4, 0xffffffff, 0x00060005,
981 0x91c8, 0xffffffff, 0x00080007,
982 0x91cc, 0xffffffff, 0x0000000b,
983 0x91d0, 0xffffffff, 0x000a0009,
984 0x91d4, 0xffffffff, 0x000d000c,
985 0x9150, 0xffffffff, 0x96940200,
986 0x8708, 0xffffffff, 0x00900100,
987 0xc478, 0xffffffff, 0x00000080,
988 0xc404, 0xffffffff, 0x0020003f,
989 0x30, 0xffffffff, 0x0000001c,
990 0x34, 0x000f0000, 0x000f0000,
991 0x160c, 0xffffffff, 0x00000100,
992 0x1024, 0xffffffff, 0x00000100,
993 0x102c, 0x00000101, 0x00000000,
994 0x20a8, 0xffffffff, 0x00000104,
995 0x264c, 0x000c0000, 0x000c0000,
996 0x2648, 0x000c0000, 0x000c0000,
997 0x55e4, 0xff000fff, 0x00000100,
998 0x55e8, 0x00000001, 0x00000001,
999 0x2f50, 0x00000001, 0x00000001,
1000 0x30cc, 0xc0000fff, 0x00000104,
1001 0xc1e4, 0x00000001, 0x00000001,
1002 0xd0c0, 0xfffffff0, 0x00000100,
1003 0xd8c0, 0xfffffff0, 0x00000100
1007 0xc400, 0xffffffff, 0xfffffffc,
1008 0x802c, 0xffffffff, 0xe0000000,
1009 0x9a60, 0xffffffff, 0x00000100,
1010 0x92a4, 0xffffffff, 0x00000100,
1011 0xc164, 0xffffffff, 0x00000100,
1012 0x9774, 0xffffffff, 0x00000100,
1013 0x8984, 0xffffffff, 0x06000100,
1014 0x8a18, 0xffffffff, 0x00000100,
1015 0x92a0, 0xffffffff, 0x00000100,
1016 0xc380, 0xffffffff, 0x00000100,
1017 0x8b28, 0xffffffff, 0x00000100,
1018 0x9144, 0xffffffff, 0x00000100,
1019 0x8d88, 0xffffffff, 0x00000100,
1020 0x8d8c, 0xffffffff, 0x00000100,
1021 0x9030, 0xffffffff, 0x00000100,
1022 0x9034, 0xffffffff, 0x00000100,
1023 0x9038, 0xffffffff, 0x00000100,
1024 0x903c, 0xffffffff, 0x00000100,
1025 0xad80, 0xffffffff, 0x00000100,
1026 0xac54, 0xffffffff, 0x00000100,
1027 0x897c, 0xffffffff, 0x06000100,
1028 0x9868, 0xffffffff, 0x00000100,
1029 0x9510, 0xffffffff, 0x00000100,
1030 0xaf04, 0xffffffff, 0x00000100,
1031 0xae04, 0xffffffff, 0x00000100,
1032 0x949c, 0xffffffff, 0x00000100,
1033 0x802c, 0xffffffff, 0xe0000000,
1034 0x9160, 0xffffffff, 0x00010000,
1035 0x9164, 0xffffffff, 0x00030002,
1036 0x9168, 0xffffffff, 0x00040007,
1037 0x916c, 0xffffffff, 0x00060005,
1038 0x9170, 0xffffffff, 0x00090008,
1039 0x9174, 0xffffffff, 0x00020001,
1040 0x9178, 0xffffffff, 0x00040003,
1041 0x917c, 0xffffffff, 0x00000007,
1042 0x9180, 0xffffffff, 0x00060005,
1043 0x9184, 0xffffffff, 0x00090008,
1044 0x9188, 0xffffffff, 0x00030002,
1045 0x918c, 0xffffffff, 0x00050004,
1046 0x9190, 0xffffffff, 0x00000008,
1047 0x9194, 0xffffffff, 0x00070006,
1048 0x9198, 0xffffffff, 0x000a0009,
1049 0x919c, 0xffffffff, 0x00040003,
1050 0x91a0, 0xffffffff, 0x00060005,
1051 0x91a4, 0xffffffff, 0x00000009,
1052 0x91a8, 0xffffffff, 0x00080007,
1053 0x91ac, 0xffffffff, 0x000b000a,
1054 0x91b0, 0xffffffff, 0x00050004,
1055 0x91b4, 0xffffffff, 0x00070006,
1056 0x91b8, 0xffffffff, 0x0008000b,
1057 0x91bc, 0xffffffff, 0x000a0009,
1058 0x91c0, 0xffffffff, 0x000d000c,
1059 0x91c4, 0xffffffff, 0x00060005,
1060 0x91c8, 0xffffffff, 0x00080007,
1061 0x91cc, 0xffffffff, 0x0000000b,
1062 0x91d0, 0xffffffff, 0x000a0009,
1063 0x91d4, 0xffffffff, 0x000d000c,
1064 0x9150, 0xffffffff, 0x96940200,
1065 0x8708, 0xffffffff, 0x00900100,
1066 0xc478, 0xffffffff, 0x00000080,
1067 0xc404, 0xffffffff, 0x0020003f,
1068 0x30, 0xffffffff, 0x0000001c,
1069 0x34, 0x000f0000, 0x000f0000,
1070 0x160c, 0xffffffff, 0x00000100,
1071 0x1024, 0xffffffff, 0x00000100,
1072 0x20a8, 0xffffffff, 0x00000104,
1073 0x264c, 0x000c0000, 0x000c0000,
1074 0x2648, 0x000c0000, 0x000c0000,
1075 0x2f50, 0x00000001, 0x00000001,
1076 0x30cc, 0xc0000fff, 0x00000104,
1077 0xc1e4, 0x00000001, 0x00000001,
1078 0xd0c0, 0xfffffff0, 0x00000100,
1079 0xd8c0, 0xfffffff0, 0x00000100
1083 0x353c, 0xffffffff, 0x40000,
1084 0x3538, 0xffffffff, 0x200010ff,
1085 0x353c, 0xffffffff, 0x0,
1086 0x353c, 0xffffffff, 0x0,
1087 0x353c, 0xffffffff, 0x0,
1088 0x353c, 0xffffffff, 0x0,
1089 0x353c, 0xffffffff, 0x0,
1090 0x353c, 0xffffffff, 0x7007,
1091 0x3538, 0xffffffff, 0x300010ff,
1092 0x353c, 0xffffffff, 0x0,
1093 0x353c, 0xffffffff, 0x0,
1094 0x353c, 0xffffffff, 0x0,
1095 0x353c, 0xffffffff, 0x0,
1096 0x353c, 0xffffffff, 0x0,
1097 0x353c, 0xffffffff, 0x400000,
1098 0x3538, 0xffffffff, 0x100010ff,
1099 0x353c, 0xffffffff, 0x0,
1100 0x353c, 0xffffffff, 0x0,
1101 0x353c, 0xffffffff, 0x0,
1102 0x353c, 0xffffffff, 0x0,
1103 0x353c, 0xffffffff, 0x0,
1104 0x353c, 0xffffffff, 0x120200,
1105 0x3538, 0xffffffff, 0x500010ff,
1106 0x353c, 0xffffffff, 0x0,
1107 0x353c, 0xffffffff, 0x0,
1108 0x353c, 0xffffffff, 0x0,
1109 0x353c, 0xffffffff, 0x0,
1110 0x353c, 0xffffffff, 0x0,
1111 0x353c, 0xffffffff, 0x1e1e16,
1112 0x3538, 0xffffffff, 0x600010ff,
1113 0x353c, 0xffffffff, 0x0,
1114 0x353c, 0xffffffff, 0x0,
1115 0x353c, 0xffffffff, 0x0,
1116 0x353c, 0xffffffff, 0x0,
1117 0x353c, 0xffffffff, 0x0,
1118 0x353c, 0xffffffff, 0x171f1e,
1119 0x3538, 0xffffffff, 0x700010ff,
1120 0x353c, 0xffffffff, 0x0,
1121 0x353c, 0xffffffff, 0x0,
1122 0x353c, 0xffffffff, 0x0,
1123 0x353c, 0xffffffff, 0x0,
1124 0x353c, 0xffffffff, 0x0,
1125 0x353c, 0xffffffff, 0x0,
1126 0x3538, 0xffffffff, 0x9ff,
1127 0x3500, 0xffffffff, 0x0,
1128 0x3504, 0xffffffff, 0x10000800,
1129 0x3504, 0xffffffff, 0xf,
1130 0x3504, 0xffffffff, 0xf,
1131 0x3500, 0xffffffff, 0x4,
1132 0x3504, 0xffffffff, 0x1000051e,
1133 0x3504, 0xffffffff, 0xffff,
1134 0x3504, 0xffffffff, 0xffff,
1135 0x3500, 0xffffffff, 0x8,
1136 0x3504, 0xffffffff, 0x80500,
1137 0x3500, 0xffffffff, 0x12,
1138 0x3504, 0xffffffff, 0x9050c,
1139 0x3500, 0xffffffff, 0x1d,
1140 0x3504, 0xffffffff, 0xb052c,
1141 0x3500, 0xffffffff, 0x2a,
1142 0x3504, 0xffffffff, 0x1053e,
1143 0x3500, 0xffffffff, 0x2d,
1144 0x3504, 0xffffffff, 0x10546,
1145 0x3500, 0xffffffff, 0x30,
1146 0x3504, 0xffffffff, 0xa054e,
1147 0x3500, 0xffffffff, 0x3c,
1148 0x3504, 0xffffffff, 0x1055f,
1149 0x3500, 0xffffffff, 0x3f,
1150 0x3504, 0xffffffff, 0x10567,
1151 0x3500, 0xffffffff, 0x42,
1152 0x3504, 0xffffffff, 0x1056f,
1153 0x3500, 0xffffffff, 0x45,
1154 0x3504, 0xffffffff, 0x10572,
1155 0x3500, 0xffffffff, 0x48,
1156 0x3504, 0xffffffff, 0x20575,
1157 0x3500, 0xffffffff, 0x4c,
1158 0x3504, 0xffffffff, 0x190801,
1159 0x3500, 0xffffffff, 0x67,
1160 0x3504, 0xffffffff, 0x1082a,
1161 0x3500, 0xffffffff, 0x6a,
1162 0x3504, 0xffffffff, 0x1b082d,
1163 0x3500, 0xffffffff, 0x87,
1164 0x3504, 0xffffffff, 0x310851,
1165 0x3500, 0xffffffff, 0xba,
1166 0x3504, 0xffffffff, 0x891,
1167 0x3500, 0xffffffff, 0xbc,
1168 0x3504, 0xffffffff, 0x893,
1169 0x3500, 0xffffffff, 0xbe,
1170 0x3504, 0xffffffff, 0x20895,
1171 0x3500, 0xffffffff, 0xc2,
1172 0x3504, 0xffffffff, 0x20899,
1173 0x3500, 0xffffffff, 0xc6,
1174 0x3504, 0xffffffff, 0x2089d,
1175 0x3500, 0xffffffff, 0xca,
1176 0x3504, 0xffffffff, 0x8a1,
1177 0x3500, 0xffffffff, 0xcc,
1178 0x3504, 0xffffffff, 0x8a3,
1179 0x3500, 0xffffffff, 0xce,
1180 0x3504, 0xffffffff, 0x308a5,
1181 0x3500, 0xffffffff, 0xd3,
1182 0x3504, 0xffffffff, 0x6d08cd,
1183 0x3500, 0xffffffff, 0x142,
1184 0x3504, 0xffffffff, 0x2000095a,
1185 0x3504, 0xffffffff, 0x1,
1186 0x3500, 0xffffffff, 0x144,
1187 0x3504, 0xffffffff, 0x301f095b,
1188 0x3500, 0xffffffff, 0x165,
1189 0x3504, 0xffffffff, 0xc094d,
1190 0x3500, 0xffffffff, 0x173,
1191 0x3504, 0xffffffff, 0xf096d,
1192 0x3500, 0xffffffff, 0x184,
1193 0x3504, 0xffffffff, 0x15097f,
1194 0x3500, 0xffffffff, 0x19b,
1195 0x3504, 0xffffffff, 0xc0998,
1196 0x3500, 0xffffffff, 0x1a9,
1197 0x3504, 0xffffffff, 0x409a7,
1198 0x3500, 0xffffffff, 0x1af,
1199 0x3504, 0xffffffff, 0xcdc,
1200 0x3500, 0xffffffff, 0x1b1,
1201 0x3504, 0xffffffff, 0x800,
1202 0x3508, 0xffffffff, 0x6c9b2000,
1203 0x3510, 0xfc00, 0x2000,
1204 0x3544, 0xffffffff, 0xfc0,
1205 0x28d4, 0x00000100, 0x100
1210 switch (rdev->family) { in si_init_golden_registers()
1278 * si_get_allowed_info_register - fetch the register for the info ioctl
1284 * Returns 0 for success or -EINVAL for an invalid register
1301 return 0; in si_get_allowed_info_register()
1303 return -EINVAL; in si_get_allowed_info_register()
1311 * si_get_xclk - get the xclk
1320 u32 reference_clock = rdev->clock.spll.reference_freq; in si_get_xclk()
1338 int actual_temp = 0; in si_get_temp()
1343 if (temp & 0x200) in si_get_temp()
1346 actual_temp = temp & 0x1ff; in si_get_temp()
1356 {0x0000006f, 0x03044000},
1357 {0x00000070, 0x0480c018},
1358 {0x00000071, 0x00000040},
1359 {0x00000072, 0x01000000},
1360 {0x00000074, 0x000000ff},
1361 {0x00000075, 0x00143400},
1362 {0x00000076, 0x08ec0800},
1363 {0x00000077, 0x040000cc},
1364 {0x00000079, 0x00000000},
1365 {0x0000007a, 0x21000409},
1366 {0x0000007c, 0x00000000},
1367 {0x0000007d, 0xe8000000},
1368 {0x0000007e, 0x044408a8},
1369 {0x0000007f, 0x00000003},
1370 {0x00000080, 0x00000000},
1371 {0x00000081, 0x01000000},
1372 {0x00000082, 0x02000000},
1373 {0x00000083, 0x00000000},
1374 {0x00000084, 0xe3f3e4f4},
1375 {0x00000085, 0x00052024},
1376 {0x00000087, 0x00000000},
1377 {0x00000088, 0x66036603},
1378 {0x00000089, 0x01000000},
1379 {0x0000008b, 0x1c0a0000},
1380 {0x0000008c, 0xff010000},
1381 {0x0000008e, 0xffffefff},
1382 {0x0000008f, 0xfff3efff},
1383 {0x00000090, 0xfff3efbf},
1384 {0x00000094, 0x00101101},
1385 {0x00000095, 0x00000fff},
1386 {0x00000096, 0x00116fff},
1387 {0x00000097, 0x60010000},
1388 {0x00000098, 0x10010000},
1389 {0x00000099, 0x00006000},
1390 {0x0000009a, 0x00001000},
1391 {0x0000009f, 0x00a77400}
1395 {0x0000006f, 0x03044000},
1396 {0x00000070, 0x0480c018},
1397 {0x00000071, 0x00000040},
1398 {0x00000072, 0x01000000},
1399 {0x00000074, 0x000000ff},
1400 {0x00000075, 0x00143400},
1401 {0x00000076, 0x08ec0800},
1402 {0x00000077, 0x040000cc},
1403 {0x00000079, 0x00000000},
1404 {0x0000007a, 0x21000409},
1405 {0x0000007c, 0x00000000},
1406 {0x0000007d, 0xe8000000},
1407 {0x0000007e, 0x044408a8},
1408 {0x0000007f, 0x00000003},
1409 {0x00000080, 0x00000000},
1410 {0x00000081, 0x01000000},
1411 {0x00000082, 0x02000000},
1412 {0x00000083, 0x00000000},
1413 {0x00000084, 0xe3f3e4f4},
1414 {0x00000085, 0x00052024},
1415 {0x00000087, 0x00000000},
1416 {0x00000088, 0x66036603},
1417 {0x00000089, 0x01000000},
1418 {0x0000008b, 0x1c0a0000},
1419 {0x0000008c, 0xff010000},
1420 {0x0000008e, 0xffffefff},
1421 {0x0000008f, 0xfff3efff},
1422 {0x00000090, 0xfff3efbf},
1423 {0x00000094, 0x00101101},
1424 {0x00000095, 0x00000fff},
1425 {0x00000096, 0x00116fff},
1426 {0x00000097, 0x60010000},
1427 {0x00000098, 0x10010000},
1428 {0x00000099, 0x00006000},
1429 {0x0000009a, 0x00001000},
1430 {0x0000009f, 0x00a47400}
1434 {0x0000006f, 0x03044000},
1435 {0x00000070, 0x0480c018},
1436 {0x00000071, 0x00000040},
1437 {0x00000072, 0x01000000},
1438 {0x00000074, 0x000000ff},
1439 {0x00000075, 0x00143400},
1440 {0x00000076, 0x08ec0800},
1441 {0x00000077, 0x040000cc},
1442 {0x00000079, 0x00000000},
1443 {0x0000007a, 0x21000409},
1444 {0x0000007c, 0x00000000},
1445 {0x0000007d, 0xe8000000},
1446 {0x0000007e, 0x044408a8},
1447 {0x0000007f, 0x00000003},
1448 {0x00000080, 0x00000000},
1449 {0x00000081, 0x01000000},
1450 {0x00000082, 0x02000000},
1451 {0x00000083, 0x00000000},
1452 {0x00000084, 0xe3f3e4f4},
1453 {0x00000085, 0x00052024},
1454 {0x00000087, 0x00000000},
1455 {0x00000088, 0x66036603},
1456 {0x00000089, 0x01000000},
1457 {0x0000008b, 0x1c0a0000},
1458 {0x0000008c, 0xff010000},
1459 {0x0000008e, 0xffffefff},
1460 {0x0000008f, 0xfff3efff},
1461 {0x00000090, 0xfff3efbf},
1462 {0x00000094, 0x00101101},
1463 {0x00000095, 0x00000fff},
1464 {0x00000096, 0x00116fff},
1465 {0x00000097, 0x60010000},
1466 {0x00000098, 0x10010000},
1467 {0x00000099, 0x00006000},
1468 {0x0000009a, 0x00001000},
1469 {0x0000009f, 0x00a37400}
1473 {0x0000006f, 0x03044000},
1474 {0x00000070, 0x0480c018},
1475 {0x00000071, 0x00000040},
1476 {0x00000072, 0x01000000},
1477 {0x00000074, 0x000000ff},
1478 {0x00000075, 0x00143400},
1479 {0x00000076, 0x08ec0800},
1480 {0x00000077, 0x040000cc},
1481 {0x00000079, 0x00000000},
1482 {0x0000007a, 0x21000409},
1483 {0x0000007c, 0x00000000},
1484 {0x0000007d, 0xe8000000},
1485 {0x0000007e, 0x044408a8},
1486 {0x0000007f, 0x00000003},
1487 {0x00000080, 0x00000000},
1488 {0x00000081, 0x01000000},
1489 {0x00000082, 0x02000000},
1490 {0x00000083, 0x00000000},
1491 {0x00000084, 0xe3f3e4f4},
1492 {0x00000085, 0x00052024},
1493 {0x00000087, 0x00000000},
1494 {0x00000088, 0x66036603},
1495 {0x00000089, 0x01000000},
1496 {0x0000008b, 0x1c0a0000},
1497 {0x0000008c, 0xff010000},
1498 {0x0000008e, 0xffffefff},
1499 {0x0000008f, 0xfff3efff},
1500 {0x00000090, 0xfff3efbf},
1501 {0x00000094, 0x00101101},
1502 {0x00000095, 0x00000fff},
1503 {0x00000096, 0x00116fff},
1504 {0x00000097, 0x60010000},
1505 {0x00000098, 0x10010000},
1506 {0x00000099, 0x00006000},
1507 {0x0000009a, 0x00001000},
1508 {0x0000009f, 0x00a17730}
1512 {0x0000006f, 0x03044000},
1513 {0x00000070, 0x0480c018},
1514 {0x00000071, 0x00000040},
1515 {0x00000072, 0x01000000},
1516 {0x00000074, 0x000000ff},
1517 {0x00000075, 0x00143400},
1518 {0x00000076, 0x08ec0800},
1519 {0x00000077, 0x040000cc},
1520 {0x00000079, 0x00000000},
1521 {0x0000007a, 0x21000409},
1522 {0x0000007c, 0x00000000},
1523 {0x0000007d, 0xe8000000},
1524 {0x0000007e, 0x044408a8},
1525 {0x0000007f, 0x00000003},
1526 {0x00000080, 0x00000000},
1527 {0x00000081, 0x01000000},
1528 {0x00000082, 0x02000000},
1529 {0x00000083, 0x00000000},
1530 {0x00000084, 0xe3f3e4f4},
1531 {0x00000085, 0x00052024},
1532 {0x00000087, 0x00000000},
1533 {0x00000088, 0x66036603},
1534 {0x00000089, 0x01000000},
1535 {0x0000008b, 0x1c0a0000},
1536 {0x0000008c, 0xff010000},
1537 {0x0000008e, 0xffffefff},
1538 {0x0000008f, 0xfff3efff},
1539 {0x00000090, 0xfff3efbf},
1540 {0x00000094, 0x00101101},
1541 {0x00000095, 0x00000fff},
1542 {0x00000096, 0x00116fff},
1543 {0x00000097, 0x60010000},
1544 {0x00000098, 0x10010000},
1545 {0x00000099, 0x00006000},
1546 {0x0000009a, 0x00001000},
1547 {0x0000009f, 0x00a07730}
1560 if (!rdev->mc_fw) in si_mc_load_microcode()
1561 return -EINVAL; in si_mc_load_microcode()
1563 if (rdev->new_fw) { in si_mc_load_microcode()
1565 (const struct mc_firmware_header_v1_0 *)rdev->mc_fw->data; in si_mc_load_microcode()
1567 radeon_ucode_print_mc_hdr(&hdr->header); in si_mc_load_microcode()
1568 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); in si_mc_load_microcode()
1570 (rdev->mc_fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in si_mc_load_microcode()
1571 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; in si_mc_load_microcode()
1573 (rdev->mc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in si_mc_load_microcode()
1575 ucode_size = rdev->mc_fw->size / 4; in si_mc_load_microcode()
1577 switch (rdev->family) { in si_mc_load_microcode()
1600 fw_data = (const __be32 *)rdev->mc_fw->data; in si_mc_load_microcode()
1605 if (running == 0) { in si_mc_load_microcode()
1607 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1608 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in si_mc_load_microcode()
1611 for (i = 0; i < regs_size; i++) { in si_mc_load_microcode()
1612 if (rdev->new_fw) { in si_mc_load_microcode()
1621 for (i = 0; i < ucode_size; i++) { in si_mc_load_microcode()
1622 if (rdev->new_fw) in si_mc_load_microcode()
1629 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1630 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in si_mc_load_microcode()
1631 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in si_mc_load_microcode()
1634 for (i = 0; i < rdev->usec_timeout; i++) { in si_mc_load_microcode()
1639 for (i = 0; i < rdev->usec_timeout; i++) { in si_mc_load_microcode()
1646 return 0; in si_mc_load_microcode()
1657 int new_fw = 0; in si_init_microcode()
1664 switch (rdev->family) { in si_init_microcode()
1678 if ((rdev->pdev->revision == 0x81) && in si_init_microcode()
1679 ((rdev->pdev->device == 0x6810) || in si_init_microcode()
1680 (rdev->pdev->device == 0x6811))) in si_init_microcode()
1693 if (((rdev->pdev->device == 0x6820) && in si_init_microcode()
1694 ((rdev->pdev->revision == 0x81) || in si_init_microcode()
1695 (rdev->pdev->revision == 0x83))) || in si_init_microcode()
1696 ((rdev->pdev->device == 0x6821) && in si_init_microcode()
1697 ((rdev->pdev->revision == 0x83) || in si_init_microcode()
1698 (rdev->pdev->revision == 0x87))) || in si_init_microcode()
1699 ((rdev->pdev->revision == 0x87) && in si_init_microcode()
1700 ((rdev->pdev->device == 0x6823) || in si_init_microcode()
1701 (rdev->pdev->device == 0x682b)))) in si_init_microcode()
1714 if (((rdev->pdev->revision == 0x81) && in si_init_microcode()
1715 ((rdev->pdev->device == 0x6600) || in si_init_microcode()
1716 (rdev->pdev->device == 0x6604) || in si_init_microcode()
1717 (rdev->pdev->device == 0x6605) || in si_init_microcode()
1718 (rdev->pdev->device == 0x6610))) || in si_init_microcode()
1719 ((rdev->pdev->revision == 0x83) && in si_init_microcode()
1720 (rdev->pdev->device == 0x6610))) in si_init_microcode()
1732 if (((rdev->pdev->revision == 0x81) && in si_init_microcode()
1733 (rdev->pdev->device == 0x6660)) || in si_init_microcode()
1734 ((rdev->pdev->revision == 0x83) && in si_init_microcode()
1735 ((rdev->pdev->device == 0x6660) || in si_init_microcode()
1736 (rdev->pdev->device == 0x6663) || in si_init_microcode()
1737 (rdev->pdev->device == 0x6665) || in si_init_microcode()
1738 (rdev->pdev->device == 0x6667)))) in si_init_microcode()
1740 else if ((rdev->pdev->revision == 0xc3) && in si_init_microcode()
1741 (rdev->pdev->device == 0x6665)) in si_init_microcode()
1756 if (((RREG32(MC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58) in si_init_microcode()
1762 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in si_init_microcode()
1765 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in si_init_microcode()
1768 if (rdev->pfp_fw->size != pfp_req_size) { in si_init_microcode()
1770 rdev->pfp_fw->size, fw_name); in si_init_microcode()
1771 err = -EINVAL; in si_init_microcode()
1775 err = radeon_ucode_validate(rdev->pfp_fw); in si_init_microcode()
1786 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in si_init_microcode()
1789 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in si_init_microcode()
1792 if (rdev->me_fw->size != me_req_size) { in si_init_microcode()
1794 rdev->me_fw->size, fw_name); in si_init_microcode()
1795 err = -EINVAL; in si_init_microcode()
1798 err = radeon_ucode_validate(rdev->me_fw); in si_init_microcode()
1809 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev); in si_init_microcode()
1812 err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev); in si_init_microcode()
1815 if (rdev->ce_fw->size != ce_req_size) { in si_init_microcode()
1817 rdev->ce_fw->size, fw_name); in si_init_microcode()
1818 err = -EINVAL; in si_init_microcode()
1821 err = radeon_ucode_validate(rdev->ce_fw); in si_init_microcode()
1832 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in si_init_microcode()
1835 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in si_init_microcode()
1838 if (rdev->rlc_fw->size != rlc_req_size) { in si_init_microcode()
1840 rdev->rlc_fw->size, fw_name); in si_init_microcode()
1841 err = -EINVAL; in si_init_microcode()
1844 err = radeon_ucode_validate(rdev->rlc_fw); in si_init_microcode()
1858 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in si_init_microcode()
1861 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in si_init_microcode()
1864 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in si_init_microcode()
1868 if ((rdev->mc_fw->size != mc_req_size) && in si_init_microcode()
1869 (rdev->mc_fw->size != mc2_req_size)) { in si_init_microcode()
1871 rdev->mc_fw->size, fw_name); in si_init_microcode()
1872 err = -EINVAL; in si_init_microcode()
1874 DRM_INFO("%s: %zu bytes\n", fw_name, rdev->mc_fw->size); in si_init_microcode()
1876 err = radeon_ucode_validate(rdev->mc_fw); in si_init_microcode()
1892 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in si_init_microcode()
1895 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in si_init_microcode()
1898 release_firmware(rdev->smc_fw); in si_init_microcode()
1899 rdev->smc_fw = NULL; in si_init_microcode()
1900 err = 0; in si_init_microcode()
1901 } else if (rdev->smc_fw->size != smc_req_size) { in si_init_microcode()
1903 rdev->smc_fw->size, fw_name); in si_init_microcode()
1904 err = -EINVAL; in si_init_microcode()
1907 err = radeon_ucode_validate(rdev->smc_fw); in si_init_microcode()
1917 if (new_fw == 0) { in si_init_microcode()
1918 rdev->new_fw = false; in si_init_microcode()
1921 err = -EINVAL; in si_init_microcode()
1923 rdev->new_fw = true; in si_init_microcode()
1927 if (err != -EINVAL) in si_init_microcode()
1930 release_firmware(rdev->pfp_fw); in si_init_microcode()
1931 rdev->pfp_fw = NULL; in si_init_microcode()
1932 release_firmware(rdev->me_fw); in si_init_microcode()
1933 rdev->me_fw = NULL; in si_init_microcode()
1934 release_firmware(rdev->ce_fw); in si_init_microcode()
1935 rdev->ce_fw = NULL; in si_init_microcode()
1936 release_firmware(rdev->rlc_fw); in si_init_microcode()
1937 rdev->rlc_fw = NULL; in si_init_microcode()
1938 release_firmware(rdev->mc_fw); in si_init_microcode()
1939 rdev->mc_fw = NULL; in si_init_microcode()
1940 release_firmware(rdev->smc_fw); in si_init_microcode()
1941 rdev->smc_fw = NULL; in si_init_microcode()
1953 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust()
1960 * 0 - half lb in dce6_line_buffer_adjust()
1961 * 2 - whole lb, other crtc must be disabled in dce6_line_buffer_adjust()
1965 * non-linked crtcs for maximum line buffer allocation. in dce6_line_buffer_adjust()
1967 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
1969 tmp = 0; /* 1/2 */ in dce6_line_buffer_adjust()
1976 tmp = 0; in dce6_line_buffer_adjust()
1977 buffer_alloc = 0; in dce6_line_buffer_adjust()
1980 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
1985 for (i = 0; i < rdev->usec_timeout; i++) { in dce6_line_buffer_adjust()
1992 if (radeon_crtc->base.enabled && mode) { in dce6_line_buffer_adjust()
1994 case 0: in dce6_line_buffer_adjust()
2003 return 0; in dce6_line_buffer_adjust()
2011 case 0: in si_get_number_of_dram_channels()
2057 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth()
2059 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth()
2077 yclk.full = dfixed_const(wm->yclk); in dce6_dram_bandwidth_for_display()
2079 dram_channels.full = dfixed_const(wm->dram_channels * 4); in dce6_dram_bandwidth_for_display()
2097 sclk.full = dfixed_const(wm->sclk); in dce6_data_return_bandwidth()
2123 disp_clk.full = dfixed_const(wm->disp_clk); in dce6_dmif_request_bandwidth()
2129 sclk.full = dfixed_const(wm->sclk); in dce6_dmif_request_bandwidth()
2169 line_time.full = dfixed_const(wm->active_time + wm->blank_time); in dce6_average_bandwidth()
2171 bpp.full = dfixed_const(wm->bytes_per_pixel); in dce6_average_bandwidth()
2172 src_width.full = dfixed_const(wm->src_width); in dce6_average_bandwidth()
2174 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce6_average_bandwidth()
2187 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ in dce6_latency_watermark()
2188 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce6_latency_watermark()
2189 (wm->num_heads * cursor_line_pair_return_time); in dce6_latency_watermark()
2195 if (wm->num_heads == 0) in dce6_latency_watermark()
2196 return 0; in dce6_latency_watermark()
2200 if ((wm->vsc.full > a.full) || in dce6_latency_watermark()
2201 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce6_latency_watermark()
2202 (wm->vtaps >= 5) || in dce6_latency_watermark()
2203 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce6_latency_watermark()
2209 b.full = dfixed_const(wm->num_heads); in dce6_latency_watermark()
2211 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); in dce6_latency_watermark()
2214 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); in dce6_latency_watermark()
2216 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); in dce6_latency_watermark()
2223 if (line_fill_time < wm->active_time) in dce6_latency_watermark()
2226 return latency + (line_fill_time - wm->active_time); in dce6_latency_watermark()
2233 (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_dram_bandwidth_for_display()
2242 (dce6_available_bandwidth(wm) / wm->num_heads)) in dce6_average_bandwidth_vs_available_bandwidth()
2250 u32 lb_partitions = wm->lb_size / wm->src_width; in dce6_check_latency_hiding()
2251 u32 line_time = wm->active_time + wm->blank_time; in dce6_check_latency_hiding()
2257 if (wm->vsc.full > a.full) in dce6_check_latency_hiding()
2260 if (lb_partitions <= (wm->vtaps + 1)) in dce6_check_latency_hiding()
2266 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); in dce6_check_latency_hiding()
2278 struct drm_display_mode *mode = &radeon_crtc->base.mode; in dce6_program_watermarks()
2282 u32 line_time = 0; in dce6_program_watermarks()
2283 u32 latency_watermark_a = 0, latency_watermark_b = 0; in dce6_program_watermarks()
2284 u32 priority_a_mark = 0, priority_b_mark = 0; in dce6_program_watermarks()
2290 if (radeon_crtc->base.enabled && num_heads && mode) { in dce6_program_watermarks()
2291 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, in dce6_program_watermarks()
2292 (u32)mode->clock); in dce6_program_watermarks()
2293 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, in dce6_program_watermarks()
2294 (u32)mode->clock); in dce6_program_watermarks()
2296 priority_a_cnt = 0; in dce6_program_watermarks()
2297 priority_b_cnt = 0; in dce6_program_watermarks()
2299 if (rdev->family == CHIP_ARUBA) in dce6_program_watermarks()
2305 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in dce6_program_watermarks()
2311 wm_high.yclk = rdev->pm.current_mclk * 10; in dce6_program_watermarks()
2312 wm_high.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()
2315 wm_high.disp_clk = mode->clock; in dce6_program_watermarks()
2316 wm_high.src_width = mode->crtc_hdisplay; in dce6_program_watermarks()
2318 wm_high.blank_time = line_time - wm_high.active_time; in dce6_program_watermarks()
2320 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce6_program_watermarks()
2322 wm_high.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2324 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
2332 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in dce6_program_watermarks()
2338 wm_low.yclk = rdev->pm.current_mclk * 10; in dce6_program_watermarks()
2339 wm_low.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()
2342 wm_low.disp_clk = mode->clock; in dce6_program_watermarks()
2343 wm_low.src_width = mode->crtc_hdisplay; in dce6_program_watermarks()
2345 wm_low.blank_time = line_time - wm_low.active_time; in dce6_program_watermarks()
2347 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dce6_program_watermarks()
2349 wm_low.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2351 if (radeon_crtc->rmx_type != RMX_OFF) in dce6_program_watermarks()
2368 (rdev->disp_priority == 2)) { in dce6_program_watermarks()
2376 (rdev->disp_priority == 2)) { in dce6_program_watermarks()
2383 b.full = dfixed_const(mode->clock); in dce6_program_watermarks()
2387 c.full = dfixed_mul(c, radeon_crtc->hsc); in dce6_program_watermarks()
2395 b.full = dfixed_const(mode->clock); in dce6_program_watermarks()
2399 c.full = dfixed_mul(c, radeon_crtc->hsc); in dce6_program_watermarks()
2407 radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); in dce6_program_watermarks()
2411 arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2415 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2416 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2420 tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset); in dce6_program_watermarks()
2423 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2424 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2428 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); in dce6_program_watermarks()
2431 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in dce6_program_watermarks()
2432 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in dce6_program_watermarks()
2435 radeon_crtc->line_time = line_time; in dce6_program_watermarks()
2436 radeon_crtc->wm_high = latency_watermark_a; in dce6_program_watermarks()
2437 radeon_crtc->wm_low = latency_watermark_b; in dce6_program_watermarks()
2444 u32 num_heads = 0, lb_size; in dce6_bandwidth_update()
2447 if (!rdev->mode_info.mode_config_initialized) in dce6_bandwidth_update()
2452 for (i = 0; i < rdev->num_crtc; i++) { in dce6_bandwidth_update()
2453 if (rdev->mode_info.crtcs[i]->base.enabled) in dce6_bandwidth_update()
2456 for (i = 0; i < rdev->num_crtc; i += 2) { in dce6_bandwidth_update()
2457 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in dce6_bandwidth_update()
2458 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; in dce6_bandwidth_update()
2459 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in dce6_bandwidth_update()
2460 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in dce6_bandwidth_update()
2461 lb_size = dce6_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in dce6_bandwidth_update()
2462 dce6_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); in dce6_bandwidth_update()
2471 u32 *tile = rdev->config.si.tile_mode_array; in si_tiling_mode_table_init()
2473 ARRAY_SIZE(rdev->config.si.tile_mode_array); in si_tiling_mode_table_init()
2476 switch (rdev->config.si.mem_row_size_in_kb) { in si_tiling_mode_table_init()
2489 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2490 tile[reg_offset] = 0; in si_tiling_mode_table_init()
2492 switch(rdev->family) { in si_tiling_mode_table_init()
2495 /* non-AA compressed depth or any compressed stencil */ in si_tiling_mode_table_init()
2496 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2531 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ in si_tiling_mode_table_init()
2540 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ in si_tiling_mode_table_init()
2549 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ in si_tiling_mode_table_init()
2703 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2710 /* non-AA compressed depth or any compressed stencil */ in si_tiling_mode_table_init()
2711 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2746 /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */ in si_tiling_mode_table_init()
2755 /* Uncompressed 16bpp depth - and stencil buffer allocated with it */ in si_tiling_mode_table_init()
2764 /* Uncompressed 32bpp depth - and stencil buffer allocated with it */ in si_tiling_mode_table_init()
2918 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2923 DRM_ERROR("unknown asic: 0x%x\n", rdev->family); in si_tiling_mode_table_init()
2932 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2934 else if (se_num == 0xffffffff) in si_select_se_sh()
2936 else if (sh_num == 0xffffffff) in si_select_se_sh()
2945 u32 i, mask = 0; in si_create_bitmask()
2947 for (i = 0; i < bit_width; i++) { in si_create_bitmask()
2962 data = 0; in si_get_cu_enabled()
2979 for (i = 0; i < se_num; i++) { in si_setup_spi()
2980 for (j = 0; j < sh_per_se; j++) { in si_setup_spi()
2986 for (k = 0; k < 16; k++) { in si_setup_spi()
2996 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_setup_spi()
3009 data = 0; in si_get_rb_disabled()
3025 u32 disabled_rbs = 0; in si_setup_rb()
3026 u32 enabled_rbs = 0; in si_setup_rb()
3028 for (i = 0; i < se_num; i++) { in si_setup_rb()
3029 for (j = 0; j < sh_per_se; j++) { in si_setup_rb()
3035 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_setup_rb()
3038 for (i = 0; i < max_rb_num_per_se * se_num; i++) { in si_setup_rb()
3044 rdev->config.si.backend_enable_mask = enabled_rbs; in si_setup_rb()
3046 for (i = 0; i < se_num; i++) { in si_setup_rb()
3047 si_select_se_sh(rdev, i, 0xffffffff); in si_setup_rb()
3048 data = 0; in si_setup_rb()
3049 for (j = 0; j < sh_per_se; j++) { in si_setup_rb()
3066 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_setup_rb()
3071 u32 gb_addr_config = 0; in si_gpu_init()
3078 switch (rdev->family) { in si_gpu_init()
3080 rdev->config.si.max_shader_engines = 2; in si_gpu_init()
3081 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()
3082 rdev->config.si.max_cu_per_sh = 8; in si_gpu_init()
3083 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3084 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3085 rdev->config.si.max_texture_channel_caches = 12; in si_gpu_init()
3086 rdev->config.si.max_gprs = 256; in si_gpu_init()
3087 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3088 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3090 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3091 rdev->config.si.sc_prim_fifo_size_backend = 0x100; in si_gpu_init()
3092 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3093 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3097 rdev->config.si.max_shader_engines = 2; in si_gpu_init()
3098 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()
3099 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3100 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3101 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3102 rdev->config.si.max_texture_channel_caches = 8; in si_gpu_init()
3103 rdev->config.si.max_gprs = 256; in si_gpu_init()
3104 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3105 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3107 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3108 rdev->config.si.sc_prim_fifo_size_backend = 0x100; in si_gpu_init()
3109 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3110 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3115 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3116 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3117 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3118 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3119 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3120 rdev->config.si.max_texture_channel_caches = 4; in si_gpu_init()
3121 rdev->config.si.max_gprs = 256; in si_gpu_init()
3122 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3123 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3125 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3126 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3127 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3128 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3132 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3133 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3134 rdev->config.si.max_cu_per_sh = 6; in si_gpu_init()
3135 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3136 rdev->config.si.max_backends_per_se = 2; in si_gpu_init()
3137 rdev->config.si.max_texture_channel_caches = 4; in si_gpu_init()
3138 rdev->config.si.max_gprs = 256; in si_gpu_init()
3139 rdev->config.si.max_gs_threads = 16; in si_gpu_init()
3140 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3142 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3143 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3144 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3145 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3149 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3150 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3151 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3152 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3153 rdev->config.si.max_backends_per_se = 1; in si_gpu_init()
3154 rdev->config.si.max_texture_channel_caches = 2; in si_gpu_init()
3155 rdev->config.si.max_gprs = 256; in si_gpu_init()
3156 rdev->config.si.max_gs_threads = 16; in si_gpu_init()
3157 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3159 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3160 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3161 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3162 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3168 for (i = 0, j = 0; i < 32; i++, j += 0x18) { in si_gpu_init()
3169 WREG32((0x2c14 + j), 0x00000000); in si_gpu_init()
3170 WREG32((0x2c18 + j), 0x00000000); in si_gpu_init()
3171 WREG32((0x2c1c + j), 0x00000000); in si_gpu_init()
3172 WREG32((0x2c20 + j), 0x00000000); in si_gpu_init()
3173 WREG32((0x2c24 + j), 0x00000000); in si_gpu_init()
3176 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in si_gpu_init()
3187 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
3188 rdev->config.si.mem_max_burst_length_bytes = 256; in si_gpu_init()
3190 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in si_gpu_init()
3191 if (rdev->config.si.mem_row_size_in_kb > 4) in si_gpu_init()
3192 rdev->config.si.mem_row_size_in_kb = 4; in si_gpu_init()
3194 rdev->config.si.shader_engine_tile_size = 32; in si_gpu_init()
3195 rdev->config.si.num_gpus = 1; in si_gpu_init()
3196 rdev->config.si.multi_gpu_tile_size = 64; in si_gpu_init()
3200 switch (rdev->config.si.mem_row_size_in_kb) { in si_gpu_init()
3203 gb_addr_config |= ROW_SIZE(0); in si_gpu_init()
3215 * bits 3:0 num_pipes in si_gpu_init()
3220 rdev->config.si.tile_config = 0; in si_gpu_init()
3221 switch (rdev->config.si.num_tile_pipes) { in si_gpu_init()
3223 rdev->config.si.tile_config |= (0 << 0); in si_gpu_init()
3226 rdev->config.si.tile_config |= (1 << 0); in si_gpu_init()
3229 rdev->config.si.tile_config |= (2 << 0); in si_gpu_init()
3234 rdev->config.si.tile_config |= (3 << 0); in si_gpu_init()
3238 case 0: /* four banks */ in si_gpu_init()
3239 rdev->config.si.tile_config |= 0 << 4; in si_gpu_init()
3242 rdev->config.si.tile_config |= 1 << 4; in si_gpu_init()
3246 rdev->config.si.tile_config |= 2 << 4; in si_gpu_init()
3249 rdev->config.si.tile_config |= in si_gpu_init()
3251 rdev->config.si.tile_config |= in si_gpu_init()
3260 if (rdev->has_uvd) { in si_gpu_init()
3268 si_setup_rb(rdev, rdev->config.si.max_shader_engines, in si_gpu_init()
3269 rdev->config.si.max_sh_per_se, in si_gpu_init()
3270 rdev->config.si.max_backends_per_se); in si_gpu_init()
3272 si_setup_spi(rdev, rdev->config.si.max_shader_engines, in si_gpu_init()
3273 rdev->config.si.max_sh_per_se, in si_gpu_init()
3274 rdev->config.si.max_cu_per_sh); in si_gpu_init()
3276 rdev->config.si.active_cus = 0; in si_gpu_init()
3277 for (i = 0; i < rdev->config.si.max_shader_engines; i++) { in si_gpu_init()
3278 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
3279 rdev->config.si.active_cus += in si_gpu_init()
3285 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in si_gpu_init()
3286 ROQ_IB2_START(0x2b))); in si_gpu_init()
3287 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in si_gpu_init()
3294 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | in si_gpu_init()
3295 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) | in si_gpu_init()
3296 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) | in si_gpu_init()
3297 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size))); in si_gpu_init()
3301 WREG32(CP_PERFMON_CNTL, 0); in si_gpu_init()
3303 WREG32(SQ_CONFIG, 0); in si_gpu_init()
3312 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in si_gpu_init()
3314 WREG32(CB_PERFCOUNTER0_SELECT0, 0); in si_gpu_init()
3315 WREG32(CB_PERFCOUNTER0_SELECT1, 0); in si_gpu_init()
3316 WREG32(CB_PERFCOUNTER1_SELECT0, 0); in si_gpu_init()
3317 WREG32(CB_PERFCOUNTER1_SELECT1, 0); in si_gpu_init()
3318 WREG32(CB_PERFCOUNTER2_SELECT0, 0); in si_gpu_init()
3319 WREG32(CB_PERFCOUNTER2_SELECT1, 0); in si_gpu_init()
3320 WREG32(CB_PERFCOUNTER3_SELECT0, 0); in si_gpu_init()
3321 WREG32(CB_PERFCOUNTER3_SELECT1, 0); in si_gpu_init()
3342 rdev->scratch.num_reg = 7; in si_scratch_init()
3343 rdev->scratch.reg_base = SCRATCH_REG0; in si_scratch_init()
3344 for (i = 0; i < rdev->scratch.num_reg; i++) { in si_scratch_init()
3345 rdev->scratch.free[i] = true; in si_scratch_init()
3346 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in si_scratch_init()
3353 struct radeon_ring *ring = &rdev->ring[fence->ring]; in si_fence_ring_emit()
3354 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in si_fence_ring_emit()
3358 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_fence_ring_emit()
3359 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3365 radeon_ring_write(ring, 0xFFFFFFFF); in si_fence_ring_emit()
3366 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3368 /* EVENT_WRITE_EOP - flush caches, send int */ in si_fence_ring_emit()
3372 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()
3373 radeon_ring_write(ring, fence->seq); in si_fence_ring_emit()
3374 radeon_ring_write(ring, 0); in si_fence_ring_emit()
3382 struct radeon_ring *ring = &rdev->ring[ib->ring]; in si_ring_ib_execute()
3383 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in si_ring_ib_execute()
3386 if (ib->is_const_ib) { in si_ring_ib_execute()
3388 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3389 radeon_ring_write(ring, 0); in si_ring_ib_execute()
3394 if (ring->rptr_save_reg) { in si_ring_ib_execute()
3395 next_rptr = ring->wptr + 3 + 4 + 8; in si_ring_ib_execute()
3397 radeon_ring_write(ring, ((ring->rptr_save_reg - in si_ring_ib_execute()
3400 } else if (rdev->wb.enabled) { in si_ring_ib_execute()
3401 next_rptr = ring->wptr + 5 + 4 + 8; in si_ring_ib_execute()
3404 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in si_ring_ib_execute()
3405 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in si_ring_ib_execute()
3415 (2 << 0) | in si_ring_ib_execute()
3417 (ib->gpu_addr & 0xFFFFFFFC)); in si_ring_ib_execute()
3418 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in si_ring_ib_execute()
3419 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); in si_ring_ib_execute()
3421 if (!ib->is_const_ib) { in si_ring_ib_execute()
3424 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); in si_ring_ib_execute()
3431 radeon_ring_write(ring, 0xFFFFFFFF); in si_ring_ib_execute()
3432 radeon_ring_write(ring, 0); in si_ring_ib_execute()
3443 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3445 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in si_cp_enable()
3446 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in si_cp_enable()
3448 WREG32(SCRATCH_UMSK, 0); in si_cp_enable()
3449 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in si_cp_enable()
3450 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_enable()
3451 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_enable()
3460 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw) in si_cp_load_microcode()
3461 return -EINVAL; in si_cp_load_microcode()
3465 if (rdev->new_fw) { in si_cp_load_microcode()
3467 (const struct gfx_firmware_header_v1_0 *)rdev->pfp_fw->data; in si_cp_load_microcode()
3469 (const struct gfx_firmware_header_v1_0 *)rdev->ce_fw->data; in si_cp_load_microcode()
3471 (const struct gfx_firmware_header_v1_0 *)rdev->me_fw->data; in si_cp_load_microcode()
3475 radeon_ucode_print_gfx_hdr(&pfp_hdr->header); in si_cp_load_microcode()
3476 radeon_ucode_print_gfx_hdr(&ce_hdr->header); in si_cp_load_microcode()
3477 radeon_ucode_print_gfx_hdr(&me_hdr->header); in si_cp_load_microcode()
3481 (rdev->pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()
3482 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()
3483 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3484 for (i = 0; i < fw_size; i++) in si_cp_load_microcode()
3486 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3490 (rdev->ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()
3491 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()
3492 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3493 for (i = 0; i < fw_size; i++) in si_cp_load_microcode()
3495 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3499 (rdev->me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); in si_cp_load_microcode()
3500 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4; in si_cp_load_microcode()
3501 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3502 for (i = 0; i < fw_size; i++) in si_cp_load_microcode()
3504 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3509 fw_data = (const __be32 *)rdev->pfp_fw->data; in si_cp_load_microcode()
3510 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3511 for (i = 0; i < SI_PFP_UCODE_SIZE; i++) in si_cp_load_microcode()
3513 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3516 fw_data = (const __be32 *)rdev->ce_fw->data; in si_cp_load_microcode()
3517 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3518 for (i = 0; i < SI_CE_UCODE_SIZE; i++) in si_cp_load_microcode()
3520 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3523 fw_data = (const __be32 *)rdev->me_fw->data; in si_cp_load_microcode()
3524 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3525 for (i = 0; i < SI_PM4_UCODE_SIZE; i++) in si_cp_load_microcode()
3527 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3530 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3531 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3532 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3533 WREG32(CP_ME_RAM_RADDR, 0); in si_cp_load_microcode()
3534 return 0; in si_cp_load_microcode()
3539 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_start()
3549 radeon_ring_write(ring, 0x1); in si_cp_start()
3550 radeon_ring_write(ring, 0x0); in si_cp_start()
3551 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); in si_cp_start()
3553 radeon_ring_write(ring, 0); in si_cp_start()
3554 radeon_ring_write(ring, 0); in si_cp_start()
3559 radeon_ring_write(ring, 0xc000); in si_cp_start()
3560 radeon_ring_write(ring, 0xe000); in si_cp_start()
3572 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3575 for (i = 0; i < si_default_size; i++) in si_cp_start()
3578 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_cp_start()
3582 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3583 radeon_ring_write(ring, 0); in si_cp_start()
3586 radeon_ring_write(ring, 0x00000316); in si_cp_start()
3587 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in si_cp_start()
3588 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in si_cp_start()
3593 ring = &rdev->ring[i]; in si_cp_start()
3601 radeon_ring_write(ring, PACKET3_COMPUTE(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
3602 radeon_ring_write(ring, 0); in si_cp_start()
3607 return 0; in si_cp_start()
3615 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_fini()
3617 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3619 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_cp_fini()
3621 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3623 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_cp_fini()
3625 radeon_scratch_free(rdev, ring->rptr_save_reg); in si_cp_fini()
3637 WREG32(CP_SEM_WAIT_TIMER, 0x0); in si_cp_resume()
3638 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in si_cp_resume()
3641 WREG32(CP_RB_WPTR_DELAY, 0); in si_cp_resume()
3643 WREG32(CP_DEBUG, 0); in si_cp_resume()
3644 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in si_cp_resume()
3646 /* ring 0 - compute and gfx */ in si_cp_resume()
3648 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_cp_resume()
3649 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3658 ring->wptr = 0; in si_cp_resume()
3659 WREG32(CP_RB0_WPTR, ring->wptr); in si_cp_resume()
3662 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3663 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3665 if (rdev->wb.enabled) in si_cp_resume()
3666 WREG32(SCRATCH_UMSK, 0xff); in si_cp_resume()
3669 WREG32(SCRATCH_UMSK, 0); in si_cp_resume()
3675 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3677 /* ring1 - compute only */ in si_cp_resume()
3679 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_cp_resume()
3680 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3689 ring->wptr = 0; in si_cp_resume()
3690 WREG32(CP_RB1_WPTR, ring->wptr); in si_cp_resume()
3693 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3694 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3699 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3701 /* ring2 - compute only */ in si_cp_resume()
3703 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_cp_resume()
3704 rb_bufsz = order_base_2(ring->ring_size / 8); in si_cp_resume()
3713 ring->wptr = 0; in si_cp_resume()
3714 WREG32(CP_RB2_WPTR, ring->wptr); in si_cp_resume()
3717 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3718 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3723 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3727 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in si_cp_resume()
3728 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = true; in si_cp_resume()
3729 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = true; in si_cp_resume()
3730 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in si_cp_resume()
3732 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in si_cp_resume()
3733 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_resume()
3734 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_resume()
3737 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP1_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); in si_cp_resume()
3739 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in si_cp_resume()
3741 r = radeon_ring_test(rdev, CAYMAN_RING_TYPE_CP2_INDEX, &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); in si_cp_resume()
3743 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in si_cp_resume()
3748 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in si_cp_resume()
3749 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in si_cp_resume()
3751 return 0; in si_cp_resume()
3756 u32 reset_mask = 0; in si_gpu_check_soft_reset()
3781 /* DMA_STATUS_REG 0 */ in si_gpu_check_soft_reset()
3828 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); in si_gpu_check_soft_reset()
3838 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; in si_gpu_soft_reset()
3841 if (reset_mask == 0) in si_gpu_soft_reset()
3844 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in si_gpu_soft_reset()
3847 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in si_gpu_soft_reset()
3849 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in si_gpu_soft_reset()
3879 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in si_gpu_soft_reset()
3933 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in si_gpu_soft_reset()
3947 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in si_gpu_soft_reset()
3979 for (i = 0; i < rdev->usec_timeout; i++) { in si_set_clk_bypass_mode()
4020 dev_info(rdev->dev, "GPU pci config reset\n"); in si_gpu_pci_config_reset()
4048 dev_warn(rdev->dev, "Wait for MC idle timed out !\n"); in si_gpu_pci_config_reset()
4056 pci_clear_master(rdev->pdev); in si_gpu_pci_config_reset()
4060 for (i = 0; i < rdev->usec_timeout; i++) { in si_gpu_pci_config_reset()
4061 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in si_gpu_pci_config_reset()
4073 return 0; in si_asic_reset()
4095 return 0; in si_asic_reset()
4099 * si_gfx_is_lockup - Check if the GFX engine is locked up
4128 for (i = 0, j = 0; i < 32; i++, j += 0x18) { in si_mc_program()
4129 WREG32((0x2c14 + j), 0x00000000); in si_mc_program()
4130 WREG32((0x2c18 + j), 0x00000000); in si_mc_program()
4131 WREG32((0x2c1c + j), 0x00000000); in si_mc_program()
4132 WREG32((0x2c20 + j), 0x00000000); in si_mc_program()
4133 WREG32((0x2c24 + j), 0x00000000); in si_mc_program()
4135 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in si_mc_program()
4139 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in si_mc_program()
4146 rdev->mc.vram_start >> 12); in si_mc_program()
4148 rdev->mc.vram_end >> 12); in si_mc_program()
4150 rdev->vram_scratch.gpu_addr >> 12); in si_mc_program()
4151 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in si_mc_program()
4152 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in si_mc_program()
4155 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in si_mc_program()
4157 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in si_mc_program()
4158 WREG32(MC_VM_AGP_BASE, 0); in si_mc_program()
4159 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in si_mc_program()
4160 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in si_mc_program()
4162 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in si_mc_program()
4175 if (mc->mc_vram_size > 0xFFC0000000ULL) { in si_vram_gtt_location()
4177 dev_warn(rdev->dev, "limiting VRAM\n"); in si_vram_gtt_location()
4178 mc->real_vram_size = 0xFFC0000000ULL; in si_vram_gtt_location()
4179 mc->mc_vram_size = 0xFFC0000000ULL; in si_vram_gtt_location()
4181 radeon_vram_location(rdev, &rdev->mc, 0); in si_vram_gtt_location()
4182 rdev->mc.gtt_base_align = 0; in si_vram_gtt_location()
4192 rdev->mc.vram_is_ddr = true; in si_mc_init()
4203 case 0: in si_mc_init()
4232 rdev->mc.vram_width = numchan * chansize; in si_mc_init()
4233 /* Could aper size report 0 ? */ in si_mc_init()
4234 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in si_mc_init()
4235 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in si_mc_init()
4239 if (tmp & 0xffff0000) { in si_mc_init()
4240 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp); in si_mc_init()
4241 if (tmp & 0xffff) in si_mc_init()
4242 tmp &= 0xffff; in si_mc_init()
4244 rdev->mc.mc_vram_size = tmp * 1024ULL * 1024ULL; in si_mc_init()
4245 rdev->mc.real_vram_size = rdev->mc.mc_vram_size; in si_mc_init()
4246 rdev->mc.visible_vram_size = rdev->mc.aper_size; in si_mc_init()
4247 si_vram_gtt_location(rdev, &rdev->mc); in si_mc_init()
4250 return 0; in si_mc_init()
4259 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in si_pcie_gart_tlb_flush()
4261 /* bits 0-15 are the VM contexts0-15 */ in si_pcie_gart_tlb_flush()
4269 if (rdev->gart.robj == NULL) { in si_pcie_gart_enable()
4270 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in si_pcie_gart_enable()
4271 return -EINVAL; in si_pcie_gart_enable()
4278 (0xA << 7) | in si_pcie_gart_enable()
4296 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in si_pcie_gart_enable()
4297 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in si_pcie_gart_enable()
4298 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in si_pcie_gart_enable()
4300 (u32)(rdev->dummy_page.addr >> 12)); in si_pcie_gart_enable()
4301 WREG32(VM_CONTEXT0_CNTL2, 0); in si_pcie_gart_enable()
4302 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4305 WREG32(0x15D4, 0); in si_pcie_gart_enable()
4306 WREG32(0x15D8, 0); in si_pcie_gart_enable()
4307 WREG32(0x15DC, 0); in si_pcie_gart_enable()
4309 /* empty context1-15 */ in si_pcie_gart_enable()
4311 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in si_pcie_gart_enable()
4312 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in si_pcie_gart_enable()
4320 rdev->vm_manager.saved_table_addr[i]); in si_pcie_gart_enable()
4322 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in si_pcie_gart_enable()
4323 rdev->vm_manager.saved_table_addr[i]); in si_pcie_gart_enable()
4326 /* enable context1-15 */ in si_pcie_gart_enable()
4328 (u32)(rdev->dummy_page.addr >> 12)); in si_pcie_gart_enable()
4331 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | in si_pcie_gart_enable()
4346 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in si_pcie_gart_enable()
4347 (unsigned)(rdev->mc.gtt_size >> 20), in si_pcie_gart_enable()
4348 (unsigned long long)rdev->gart.table_addr); in si_pcie_gart_enable()
4349 rdev->gart.ready = true; in si_pcie_gart_enable()
4350 return 0; in si_pcie_gart_enable()
4362 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2); in si_pcie_gart_disable()
4363 rdev->vm_manager.saved_table_addr[i] = RREG32(reg); in si_pcie_gart_disable()
4367 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
4368 WREG32(VM_CONTEXT1_CNTL, 0); in si_pcie_gart_disable()
4377 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
4379 L2_CACHE_BIGK_FRAGMENT_SIZE(0)); in si_pcie_gart_disable()
4394 if (reg >= 0x28000) in si_vm_reg_valid()
4398 if (reg >= 0xB000 && reg < 0xC000) in si_vm_reg_valid()
4432 DRM_ERROR("Invalid register 0x%x in CS\n", reg); in si_vm_reg_valid()
4440 switch (pkt->opcode) { in si_vm_packet3_ce_check()
4453 DRM_ERROR("Invalid CE packet3: 0x%x\n", pkt->opcode); in si_vm_packet3_ce_check()
4454 return -EINVAL; in si_vm_packet3_ce_check()
4456 return 0; in si_vm_packet3_ce_check()
4467 if (((info & 0x60000000) >> 29) == 0) { in si_vm_packet3_cp_dma_check()
4473 return -EINVAL; in si_vm_packet3_cp_dma_check()
4476 for (i = 0; i < (command & 0x1fffff); i++) { in si_vm_packet3_cp_dma_check()
4480 return -EINVAL; in si_vm_packet3_cp_dma_check()
4488 if (((info & 0x00300000) >> 20) == 0) { in si_vm_packet3_cp_dma_check()
4494 return -EINVAL; in si_vm_packet3_cp_dma_check()
4497 for (i = 0; i < (command & 0x1fffff); i++) { in si_vm_packet3_cp_dma_check()
4501 return -EINVAL; in si_vm_packet3_cp_dma_check()
4507 return 0; in si_vm_packet3_cp_dma_check()
4514 u32 idx = pkt->idx + 1; in si_vm_packet3_gfx_check()
4518 switch (pkt->opcode) { in si_vm_packet3_gfx_check()
4566 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4569 return -EINVAL; in si_vm_packet3_gfx_check()
4573 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4575 if (idx_value & 0x10000) { in si_vm_packet3_gfx_check()
4577 return -EINVAL; in si_vm_packet3_gfx_check()
4579 for (i = 0; i < (pkt->count - 2); i++) { in si_vm_packet3_gfx_check()
4582 return -EINVAL; in si_vm_packet3_gfx_check()
4588 if (idx_value & 0x100) { in si_vm_packet3_gfx_check()
4591 return -EINVAL; in si_vm_packet3_gfx_check()
4595 if (idx_value & 0x2) { in si_vm_packet3_gfx_check()
4598 return -EINVAL; in si_vm_packet3_gfx_check()
4603 end_reg = 4 * pkt->count + start_reg - 4; in si_vm_packet3_gfx_check()
4608 return -EINVAL; in si_vm_packet3_gfx_check()
4610 for (i = 0; i < pkt->count; i++) { in si_vm_packet3_gfx_check()
4613 return -EINVAL; in si_vm_packet3_gfx_check()
4622 DRM_ERROR("Invalid GFX packet3: 0x%x\n", pkt->opcode); in si_vm_packet3_gfx_check()
4623 return -EINVAL; in si_vm_packet3_gfx_check()
4625 return 0; in si_vm_packet3_gfx_check()
4632 u32 idx = pkt->idx + 1; in si_vm_packet3_compute_check()
4636 switch (pkt->opcode) { in si_vm_packet3_compute_check()
4669 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_compute_check()
4672 return -EINVAL; in si_vm_packet3_compute_check()
4676 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_compute_check()
4678 if (idx_value & 0x10000) { in si_vm_packet3_compute_check()
4680 return -EINVAL; in si_vm_packet3_compute_check()
4682 for (i = 0; i < (pkt->count - 2); i++) { in si_vm_packet3_compute_check()
4685 return -EINVAL; in si_vm_packet3_compute_check()
4691 if (idx_value & 0x100) { in si_vm_packet3_compute_check()
4694 return -EINVAL; in si_vm_packet3_compute_check()
4698 if (idx_value & 0x2) { in si_vm_packet3_compute_check()
4701 return -EINVAL; in si_vm_packet3_compute_check()
4710 DRM_ERROR("Invalid Compute packet3: 0x%x\n", pkt->opcode); in si_vm_packet3_compute_check()
4711 return -EINVAL; in si_vm_packet3_compute_check()
4713 return 0; in si_vm_packet3_compute_check()
4718 int ret = 0; in si_ib_parse()
4719 u32 idx = 0, i; in si_ib_parse()
4724 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in si_ib_parse()
4725 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in si_ib_parse()
4726 pkt.one_reg_wr = 0; in si_ib_parse()
4729 dev_err(rdev->dev, "Packet0 not allowed!\n"); in si_ib_parse()
4730 ret = -EINVAL; in si_ib_parse()
4736 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in si_ib_parse()
4737 if (ib->is_const_ib) in si_ib_parse()
4738 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); in si_ib_parse()
4740 switch (ib->ring) { in si_ib_parse()
4742 ret = si_vm_packet3_gfx_check(rdev, ib->ptr, &pkt); in si_ib_parse()
4746 ret = si_vm_packet3_compute_check(rdev, ib->ptr, &pkt); in si_ib_parse()
4749 dev_err(rdev->dev, "Non-PM4 ring %d !\n", ib->ring); in si_ib_parse()
4750 ret = -EINVAL; in si_ib_parse()
4757 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); in si_ib_parse()
4758 ret = -EINVAL; in si_ib_parse()
4762 for (i = 0; i < ib->length_dw; i++) { in si_ib_parse()
4764 printk("\t0x%08x <---\n", ib->ptr[i]); in si_ib_parse()
4766 printk("\t0x%08x\n", ib->ptr[i]); in si_ib_parse()
4770 } while (idx < ib->length_dw); in si_ib_parse()
4781 rdev->vm_manager.nvm = 16; in si_vm_init()
4783 rdev->vm_manager.vram_base_offset = 0; in si_vm_init()
4785 return 0; in si_vm_init()
4793 * si_vm_decode_fault - print human readable fault info
4809 if (rdev->family == CHIP_TAHITI) { in si_vm_decode_fault()
4886 case 0: in si_vm_decode_fault()
5050 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n", in si_vm_decode_fault()
5062 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5069 (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); in si_vm_flush()
5071 radeon_ring_write(ring, 0); in si_vm_flush()
5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5079 radeon_ring_write(ring, 0); in si_vm_flush()
5080 radeon_ring_write(ring, 0x1); in si_vm_flush()
5082 /* bits 0-15 are the VM contexts0-15 */ in si_vm_flush()
5085 WRITE_DATA_DST_SEL(0))); in si_vm_flush()
5087 radeon_ring_write(ring, 0); in si_vm_flush()
5092 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in si_vm_flush()
5093 WAIT_REG_MEM_ENGINE(0))); /* me */ in si_vm_flush()
5095 radeon_ring_write(ring, 0); in si_vm_flush()
5096 radeon_ring_write(ring, 0); /* ref */ in si_vm_flush()
5097 radeon_ring_write(ring, 0); /* mask */ in si_vm_flush()
5098 radeon_ring_write(ring, 0x20); /* poll interval */ in si_vm_flush()
5101 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in si_vm_flush()
5102 radeon_ring_write(ring, 0x0); in si_vm_flush()
5112 for (i = 0; i < rdev->usec_timeout; i++) { in si_wait_for_rlc_serdes()
5113 if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0) in si_wait_for_rlc_serdes()
5118 for (i = 0; i < rdev->usec_timeout; i++) { in si_wait_for_rlc_serdes()
5119 if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0) in si_wait_for_rlc_serdes()
5143 for (i = 0; i < rdev->usec_timeout; i++) { in si_enable_gui_idle_interrupt()
5161 tmp &= ~0x7ffff800; in si_set_uvd_dcm()
5164 tmp |= 0x7ffff800; in si_set_uvd_dcm()
5165 tmp2 = 0; in si_set_uvd_dcm()
5215 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA)) in si_enable_dma_pg()
5227 WREG32(DMA_PGFSM_WRITE, 0x00002000); in si_init_dma_pg()
5228 WREG32(DMA_PGFSM_CONFIG, 0x100010ff); in si_init_dma_pg()
5230 for (tmp = 0; tmp < 5; tmp++) in si_init_dma_pg()
5231 WREG32(DMA_PGFSM_WRITE, 0); in si_init_dma_pg()
5239 if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) { in si_enable_gfx_cgpg()
5240 tmp = RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10); in si_enable_gfx_cgpg()
5263 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5269 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5274 tmp |= GRBM_REG_SGIT(0x700); in si_init_gfx_cgpg()
5281 u32 mask = 0, tmp, tmp1; in si_get_cu_active_bitmap()
5287 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_get_cu_active_bitmap()
5289 tmp &= 0xffff0000; in si_get_cu_active_bitmap()
5294 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) { in si_get_cu_active_bitmap()
5304 u32 i, j, k, active_cu_number = 0; in si_init_ao_cu_mask()
5306 u32 tmp = 0; in si_init_ao_cu_mask()
5308 for (i = 0; i < rdev->config.si.max_shader_engines; i++) { in si_init_ao_cu_mask()
5309 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
5311 cu_bitmap = 0; in si_init_ao_cu_mask()
5312 counter = 0; in si_init_ao_cu_mask()
5313 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { in si_init_ao_cu_mask()
5342 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) { in si_enable_cgcg()
5345 WREG32(RLC_GCPM_GENERAL_3, 0x00000080); in si_enable_cgcg()
5349 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_cgcg()
5350 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_cgcg()
5351 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); in si_enable_cgcg()
5357 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); in si_enable_cgcg()
5378 u32 data, orig, tmp = 0; in si_enable_mgcg()
5380 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) { in si_enable_mgcg()
5382 data = 0x96940200; in si_enable_mgcg()
5386 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) { in si_enable_mgcg()
5394 data &= 0xffffffc0; in si_enable_mgcg()
5400 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5401 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5402 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); in si_enable_mgcg()
5407 data |= 0x00000003; in si_enable_mgcg()
5423 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5424 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5425 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); in si_enable_mgcg()
5436 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) { in si_enable_uvd_mgcg()
5438 tmp |= 0x3fff; in si_enable_uvd_mgcg()
5446 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5447 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5450 tmp &= ~0x3fff; in si_enable_uvd_mgcg()
5458 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5459 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
5482 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { in si_enable_mc_ls()
5484 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS)) in si_enable_mc_ls()
5499 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) { in si_enable_mc_mgcg()
5501 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG)) in si_enable_mc_mgcg()
5516 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) { in si_enable_dma_mgcg()
5517 for (i = 0; i < 2; i++) { in si_enable_dma_mgcg()
5518 if (i == 0) in si_enable_dma_mgcg()
5526 WREG32(DMA_CLK_CTRL + offset, 0x00000100); in si_enable_dma_mgcg()
5529 for (i = 0; i < 2; i++) { in si_enable_dma_mgcg()
5530 if (i == 0) in si_enable_dma_mgcg()
5540 data = 0xff000000; in si_enable_dma_mgcg()
5554 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS)) in si_enable_bif_mgls()
5572 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG)) in si_enable_hdp_mgcg()
5588 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS)) in si_enable_hdp_ls()
5627 if (rdev->has_uvd) { in si_update_cg()
5645 if (rdev->has_uvd) { in si_init_cg()
5653 if (rdev->has_uvd) { in si_fini_cg()
5665 u32 count = 0; in si_get_csb_size()
5669 if (rdev->rlc.cs_data == NULL) in si_get_csb_size()
5670 return 0; in si_get_csb_size()
5677 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_size()
5678 for (ext = sect->section; ext->extent != NULL; ++ext) { in si_get_csb_size()
5679 if (sect->id == SECT_CONTEXT) in si_get_csb_size()
5680 count += 2 + ext->reg_count; in si_get_csb_size()
5682 return 0; in si_get_csb_size()
5697 u32 count = 0, i; in si_get_csb_buffer()
5701 if (rdev->rlc.cs_data == NULL) in si_get_csb_buffer()
5706 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_get_csb_buffer()
5710 buffer[count++] = cpu_to_le32(0x80000000); in si_get_csb_buffer()
5711 buffer[count++] = cpu_to_le32(0x80000000); in si_get_csb_buffer()
5713 for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) { in si_get_csb_buffer()
5714 for (ext = sect->section; ext->extent != NULL; ++ext) { in si_get_csb_buffer()
5715 if (sect->id == SECT_CONTEXT) { in si_get_csb_buffer()
5717 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in si_get_csb_buffer()
5718 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000); in si_get_csb_buffer()
5719 for (i = 0; i < ext->reg_count; i++) in si_get_csb_buffer()
5720 buffer[count++] = cpu_to_le32(ext->extent[i]); in si_get_csb_buffer()
5728 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in si_get_csb_buffer()
5729 switch (rdev->family) { in si_get_csb_buffer()
5732 buffer[count++] = cpu_to_le32(0x2a00126a); in si_get_csb_buffer()
5735 buffer[count++] = cpu_to_le32(0x0000124a); in si_get_csb_buffer()
5738 buffer[count++] = cpu_to_le32(0x00000082); in si_get_csb_buffer()
5741 buffer[count++] = cpu_to_le32(0x00000000); in si_get_csb_buffer()
5744 buffer[count++] = cpu_to_le32(0x00000000); in si_get_csb_buffer()
5748 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in si_get_csb_buffer()
5751 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in si_get_csb_buffer()
5752 buffer[count++] = cpu_to_le32(0); in si_get_csb_buffer()
5757 if (rdev->pg_flags) { in si_init_pg()
5758 if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA) { in si_init_pg()
5762 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) { in si_init_pg()
5765 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5766 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5771 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5772 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5778 if (rdev->pg_flags) { in si_fini_pg()
5801 WREG32(RLC_CNTL, 0); in si_rlc_stop()
5823 if ((tmp & 0xF0000000) == 0xB0000000) in si_lbpw_supported()
5840 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); in si_enable_lbpw()
5841 WREG32(SPI_LB_CU_MASK, 0x00ff); in si_enable_lbpw()
5849 if (!rdev->rlc_fw) in si_rlc_resume()
5850 return -EINVAL; in si_rlc_resume()
5860 WREG32(RLC_RL_BASE, 0); in si_rlc_resume()
5861 WREG32(RLC_RL_SIZE, 0); in si_rlc_resume()
5862 WREG32(RLC_LB_CNTL, 0); in si_rlc_resume()
5863 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); in si_rlc_resume()
5864 WREG32(RLC_LB_CNTR_INIT, 0); in si_rlc_resume()
5865 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in si_rlc_resume()
5867 WREG32(RLC_MC_CNTL, 0); in si_rlc_resume()
5868 WREG32(RLC_UCODE_CNTL, 0); in si_rlc_resume()
5870 if (rdev->new_fw) { in si_rlc_resume()
5872 (const struct rlc_firmware_header_v1_0 *)rdev->rlc_fw->data; in si_rlc_resume()
5873 u32 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; in si_rlc_resume()
5875 (rdev->rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in si_rlc_resume()
5877 radeon_ucode_print_rlc_hdr(&hdr->header); in si_rlc_resume()
5879 for (i = 0; i < fw_size; i++) { in si_rlc_resume()
5885 (const __be32 *)rdev->rlc_fw->data; in si_rlc_resume()
5886 for (i = 0; i < SI_RLC_UCODE_SIZE; i++) { in si_rlc_resume()
5891 WREG32(RLC_UCODE_ADDR, 0); in si_rlc_resume()
5897 return 0; in si_rlc_resume()
5909 rdev->ih.enabled = true; in si_enable_interrupts()
5921 /* set rptr, wptr to 0 */ in si_disable_interrupts()
5922 WREG32(IH_RB_RPTR, 0); in si_disable_interrupts()
5923 WREG32(IH_RB_WPTR, 0); in si_disable_interrupts()
5924 rdev->ih.enabled = false; in si_disable_interrupts()
5925 rdev->ih.rptr = 0; in si_disable_interrupts()
5936 WREG32(CP_INT_CNTL_RING1, 0); in si_disable_interrupt_state()
5937 WREG32(CP_INT_CNTL_RING2, 0); in si_disable_interrupt_state()
5942 WREG32(GRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5943 WREG32(SRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5944 for (i = 0; i < rdev->num_crtc; i++) in si_disable_interrupt_state()
5945 WREG32(INT_MASK + crtc_offsets[i], 0); in si_disable_interrupt_state()
5946 for (i = 0; i < rdev->num_crtc; i++) in si_disable_interrupt_state()
5947 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in si_disable_interrupt_state()
5950 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in si_disable_interrupt_state()
5952 for (i = 0; i < 6; i++) in si_disable_interrupt_state()
5960 int ret = 0; in si_irq_init()
5981 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); in si_irq_init()
5983 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi in si_irq_init()
5984 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN in si_irq_init()
5987 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ in si_irq_init()
5991 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in si_irq_init()
5992 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in si_irq_init()
5998 if (rdev->wb.enabled) in si_irq_init()
6002 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in si_irq_init()
6003 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in si_irq_init()
6007 /* set rptr, wptr to 0 */ in si_irq_init()
6008 WREG32(IH_RB_RPTR, 0); in si_irq_init()
6009 WREG32(IH_RB_WPTR, 0); in si_irq_init()
6012 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); in si_irq_init()
6014 if (rdev->msi_enabled) in si_irq_init()
6021 pci_set_master(rdev->pdev); in si_irq_init()
6034 u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; in si_irq_set()
6035 u32 grbm_int_cntl = 0; in si_irq_set()
6037 u32 thermal_int = 0; in si_irq_set()
6039 if (!rdev->irq.installed) { in si_irq_set()
6041 return -EINVAL; in si_irq_set()
6044 if (!rdev->ih.enabled) { in si_irq_set()
6048 return 0; in si_irq_set()
6061 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in si_irq_set()
6065 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { in si_irq_set()
6069 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { in si_irq_set()
6073 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in si_irq_set()
6078 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { in si_irq_set()
6092 if (rdev->irq.dpm_thermal) { in si_irq_set()
6097 for (i = 0; i < rdev->num_crtc; i++) { in si_irq_set()
6100 rdev->irq.crtc_vblank_int[i] || in si_irq_set()
6101 atomic_read(&rdev->irq.pflip[i]), "vblank", i); in si_irq_set()
6104 for (i = 0; i < rdev->num_crtc; i++) in si_irq_set()
6108 for (i = 0; i < 6; i++) { in si_irq_set()
6112 rdev->irq.hpd[i], "HPD", i); in si_irq_set()
6121 return 0; in si_irq_set()
6128 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_ack()
6129 u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int; in si_irq_ack()
6134 for (i = 0; i < 6; i++) { in si_irq_ack()
6136 if (i < rdev->num_crtc) in si_irq_ack()
6141 for (i = 0; i < rdev->num_crtc; i += 2) { in si_irq_ack()
6158 for (i = 0; i < 6; i++) { in si_irq_ack()
6163 for (i = 0; i < 6; i++) { in si_irq_ack()
6194 if (rdev->wb.enabled) in si_get_ih_wptr()
6195 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in si_get_ih_wptr()
6205 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in si_get_ih_wptr()
6206 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in si_get_ih_wptr()
6207 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in si_get_ih_wptr()
6212 return (wptr & rdev->ih.ptr_mask); in si_get_ih_wptr()
6217 * [7:0] - interrupt source id
6218 * [31:8] - reserved
6219 * [59:32] - interrupt source data
6220 * [63:60] - reserved
6221 * [71:64] - RINGID
6222 * [79:72] - VMID
6223 * [127:80] - reserved
6227 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in si_irq_process()
6240 if (!rdev->ih.enabled || rdev->shutdown) in si_irq_process()
6247 if (atomic_xchg(&rdev->ih.lock, 1)) in si_irq_process()
6250 rptr = rdev->ih.rptr; in si_irq_process()
6262 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in si_irq_process()
6263 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in si_irq_process()
6264 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; in si_irq_process()
6273 crtc_idx = src_id - 1; in si_irq_process()
6275 if (src_data == 0) { /* vblank */ in si_irq_process()
6279 if (rdev->irq.crtc_vblank_int[crtc_idx]) { in si_irq_process()
6281 rdev->pm.vblank_sync = true; in si_irq_process()
6282 wake_up(&rdev->irq.vblank_queue); in si_irq_process()
6284 if (atomic_read(&rdev->irq.pflip[crtc_idx])) { in si_irq_process()
6299 DRM_DEBUG("IH: D%d %s - IH event w/o asserted irq bit?\n", in si_irq_process()
6313 DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); in si_irq_process()
6314 if (radeon_use_pflipirq > 0) in si_irq_process()
6315 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); in si_irq_process()
6325 hpd_idx = src_data - 6; in si_irq_process()
6343 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in si_irq_process()
6344 WREG32(SRBM_INT_ACK, 0x1); in si_irq_process()
6347 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); in si_irq_process()
6356 if (addr == 0x0 && status == 0x0) in si_irq_process()
6358 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); in si_irq_process()
6359 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in si_irq_process()
6361 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in si_irq_process()
6377 case 0: in si_irq_process()
6394 rdev->pm.dpm.thermal.high_to_low = false; in si_irq_process()
6399 rdev->pm.dpm.thermal.high_to_low = true; in si_irq_process()
6416 rptr &= rdev->ih.ptr_mask; in si_irq_process()
6420 schedule_work(&rdev->dp_work); in si_irq_process()
6422 schedule_delayed_work(&rdev->hotplug_work, 0); in si_irq_process()
6423 if (queue_thermal && rdev->pm.dpm_enabled) in si_irq_process()
6424 schedule_work(&rdev->pm.dpm.thermal.work); in si_irq_process()
6425 rdev->ih.rptr = rptr; in si_irq_process()
6426 atomic_set(&rdev->ih.lock, 0); in si_irq_process()
6443 if (!rdev->has_uvd) in si_uvd_init()
6448 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in si_uvd_init()
6450 * At this point rdev->uvd.vcpu_bo is NULL which trickles down in si_uvd_init()
6455 rdev->has_uvd = false; in si_uvd_init()
6458 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in si_uvd_init()
6459 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in si_uvd_init()
6466 if (!rdev->has_uvd) in si_uvd_start()
6471 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in si_uvd_start()
6476 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in si_uvd_start()
6482 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in si_uvd_start()
6490 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in si_uvd_resume()
6493 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in si_uvd_resume()
6494 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in si_uvd_resume()
6496 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in si_uvd_resume()
6501 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in si_uvd_resume()
6510 if (!rdev->has_vce) in si_vce_init()
6515 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); in si_vce_init()
6517 * At this point rdev->vce.vcpu_bo is NULL which trickles down in si_vce_init()
6522 rdev->has_vce = false; in si_vce_init()
6525 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; in si_vce_init()
6526 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); in si_vce_init()
6527 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; in si_vce_init()
6528 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); in si_vce_init()
6535 if (!rdev->has_vce) in si_vce_start()
6540 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in si_vce_start()
6545 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in si_vce_start()
6550 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); in si_vce_start()
6555 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); in si_vce_start()
6561 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in si_vce_start()
6562 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in si_vce_start()
6570 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) in si_vce_resume()
6573 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in si_vce_resume()
6574 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP); in si_vce_resume()
6576 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in si_vce_resume()
6579 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in si_vce_resume()
6580 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, VCE_CMD_NO_OP); in si_vce_resume()
6582 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in si_vce_resume()
6587 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); in si_vce_resume()
6609 if (!rdev->pm.dpm_enabled) { in si_startup()
6623 if (rdev->family == CHIP_VERDE) { in si_startup()
6624 rdev->rlc.reg_list = verde_rlc_save_restore_register_list; in si_startup()
6625 rdev->rlc.reg_list_size = in si_startup()
6628 rdev->rlc.cs_data = si_cs_data; in si_startup()
6642 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in si_startup()
6648 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in si_startup()
6654 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in si_startup()
6660 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in si_startup()
6666 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in si_startup()
6674 if (!rdev->irq.installed) { in si_startup()
6688 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_startup()
6689 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in si_startup()
6694 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_startup()
6695 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, in si_startup()
6700 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_startup()
6701 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, in si_startup()
6706 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in si_startup()
6707 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in si_startup()
6708 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_startup()
6712 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in si_startup()
6713 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in si_startup()
6714 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0)); in si_startup()
6734 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in si_startup()
6740 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); in si_startup()
6748 return 0; in si_startup()
6760 atom_asic_init(rdev->mode_info.atom_context); in si_resume()
6765 if (rdev->pm.pm_method == PM_METHOD_DPM) in si_resume()
6768 rdev->accel_working = true; in si_resume()
6772 rdev->accel_working = false; in si_resume()
6787 if (rdev->has_uvd) { in si_suspend()
6791 if (rdev->has_vce) in si_suspend()
6798 return 0; in si_suspend()
6809 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_init()
6815 return -EINVAL; in si_init()
6818 if (!rdev->is_atom_bios) { in si_init()
6819 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); in si_init()
6820 return -EINVAL; in si_init()
6828 if (!rdev->bios) { in si_init()
6829 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in si_init()
6830 return -EINVAL; in si_init()
6833 atom_asic_init(rdev->mode_info.atom_context); in si_init()
6856 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw || in si_init()
6857 !rdev->rlc_fw || !rdev->mc_fw) { in si_init()
6868 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in si_init()
6869 ring->ring_obj = NULL; in si_init()
6872 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in si_init()
6873 ring->ring_obj = NULL; in si_init()
6876 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in si_init()
6877 ring->ring_obj = NULL; in si_init()
6880 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in si_init()
6881 ring->ring_obj = NULL; in si_init()
6884 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in si_init()
6885 ring->ring_obj = NULL; in si_init()
6891 rdev->ih.ring_obj = NULL; in si_init()
6898 rdev->accel_working = true; in si_init()
6901 dev_err(rdev->dev, "disabling GPU acceleration\n"); in si_init()
6911 rdev->accel_working = false; in si_init()
6918 if (!rdev->mc_fw) { in si_init()
6920 return -EINVAL; in si_init()
6923 return 0; in si_init()
6939 if (rdev->has_uvd) { in si_fini()
6943 if (rdev->has_vce) in si_fini()
6951 kfree(rdev->bios); in si_fini()
6952 rdev->bios = NULL; in si_fini()
6956 * si_get_gpu_clock_counter - return GPU clock counter snapshot
6967 mutex_lock(&rdev->gpu_clock_mutex); in si_get_gpu_clock_counter()
6971 mutex_unlock(&rdev->gpu_clock_mutex); in si_get_gpu_clock_counter()
6977 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks()
6990 return 0; in si_set_uvd_clocks()
6994 16384, 0x03FFFFFF, 0, 128, 5, in si_set_uvd_clocks()
6999 /* set RESET_ANTI_MUX to 0 */ in si_set_uvd_clocks()
7000 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_uvd_clocks()
7006 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
7009 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7021 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in si_set_uvd_clocks()
7026 /* set ref divider to 0 */ in si_set_uvd_clocks()
7027 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK); in si_set_uvd_clocks()
7030 WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9); in si_set_uvd_clocks()
7043 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7048 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
7061 return 0; in si_set_uvd_clocks()
7066 struct pci_dev *root = rdev->pdev->bus->self; in si_pcie_gen3_enable()
7072 if (pci_is_root_bus(rdev->pdev->bus)) in si_pcie_gen3_enable()
7075 if (radeon_pcie_gen2 == 0) in si_pcie_gen3_enable()
7078 if (rdev->flags & RADEON_IS_IGP) in si_pcie_gen3_enable()
7081 if (!(rdev->flags & RADEON_IS_PCIE)) in si_pcie_gen3_enable()
7100 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n"); in si_pcie_gen3_enable()
7106 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); in si_pcie_gen3_enable()
7109 if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev)) in si_pcie_gen3_enable()
7113 /* re-try equalization if gen3 is not already enabled */ in si_pcie_gen3_enable()
7120 pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); in si_pcie_gen3_enable()
7136 for (i = 0; i < 10; i++) { in si_pcie_gen3_enable()
7138 pcie_capability_read_word(rdev->pdev, in si_pcie_gen3_enable()
7146 pcie_capability_read_word(rdev->pdev, in si_pcie_gen3_enable()
7152 pcie_capability_read_word(rdev->pdev, in si_pcie_gen3_enable()
7171 pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL, in si_pcie_gen3_enable()
7183 pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2, in si_pcie_gen3_enable()
7202 tmp16 = 0; in si_pcie_gen3_enable()
7209 pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL2, in si_pcie_gen3_enable()
7216 for (i = 0; i < rdev->usec_timeout; i++) { in si_pcie_gen3_enable()
7218 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0) in si_pcie_gen3_enable()
7230 if (radeon_aspm == 0) in si_program_aspm()
7233 if (!(rdev->flags & RADEON_IS_PCIE)) in si_program_aspm()
7238 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN; in si_program_aspm()
7291 if ((rdev->family != CHIP_OLAND) && (rdev->family != CHIP_HAINAN)) { in si_program_aspm()
7340 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN)) in si_program_aspm()
7347 if ((rdev->family == CHIP_OLAND) || (rdev->family == CHIP_HAINAN)) in si_program_aspm()
7353 !pci_is_root_bus(rdev->pdev->bus)) { in si_program_aspm()
7354 struct pci_dev *root = rdev->pdev->bus->self; in si_program_aspm()
7434 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7442 for (i = 0; i < 100; ++i) { in si_vce_send_vcepll_ctlreq()
7450 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~UPLL_CTLREQ_MASK); in si_vce_send_vcepll_ctlreq()
7454 return -ETIMEDOUT; in si_vce_send_vcepll_ctlreq()
7457 return 0; in si_vce_send_vcepll_ctlreq()
7462 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; in si_set_vce_clocks()
7478 return 0; in si_set_vce_clocks()
7482 16384, 0x03FFFFFF, 0, 128, 5, in si_set_vce_clocks()
7487 /* set RESET_ANTI_MUX to 0 */ in si_set_vce_clocks()
7488 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_vce_clocks()
7494 /* toggle VCEPLL_SLEEP to 1 then back to 0 */ in si_set_vce_clocks()
7497 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_SLEEP_MASK); in si_set_vce_clocks()
7500 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
7512 WREG32_SMC_P(CG_VCEPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in si_set_vce_clocks()
7517 /* set ref divider to 0 */ in si_set_vce_clocks()
7518 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_REF_DIV_MASK); in si_set_vce_clocks()
7529 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_RESET_MASK); in si_set_vce_clocks()
7534 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL, 0, ~VCEPLL_BYPASS_EN_MASK); in si_set_vce_clocks()
7547 return 0; in si_set_vce_clocks()