Lines Matching +full:128 +full:m

49 	case 128:  in rs400_gart_adjust_size()
58 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); in rs400_gart_adjust_size()
59 DRM_ERROR("Forcing to 32M GART size\n"); in rs400_gart_adjust_size()
93 case 128: in rs400_gart_init()
127 case 128: in rs400_gart_enable()
275 rdev->mc.vram_width = 128; in rs400_mc_init()
309 static int rs400_debugfs_gart_info_show(struct seq_file *m, void *unused) in rs400_debugfs_gart_info_show() argument
311 struct radeon_device *rdev = m->private; in rs400_debugfs_gart_info_show()
315 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
317 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
319 seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
322 seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
324 seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
326 seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
328 seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
330 seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
333 seq_printf(m, "AGP_BASE 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
335 seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
337 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
340 seq_printf(m, "GART_BASE 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
342 seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
344 seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
346 seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
348 seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
350 seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
352 seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
354 seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
356 seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
358 seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
360 seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
362 seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
364 seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
366 seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
368 seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
370 seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
372 seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); in rs400_debugfs_gart_info_show()
444 /* 1M ring buffer */ in rs400_startup()