Lines Matching +full:lvds +full:- +full:encoder
3 * Copyright 2007-8 Advanced Micro Devices, Inc.
133 struct radeon_device *rdev = dev->dev_private;
137 if (!rdev->bios)
362 size = RBIOS8(rdev->bios_header_start + 0x6);
365 offset = RBIOS16(rdev->bios_header_start + check_offset);
379 raw = rdev->bios + edid_info;
388 rdev->mode_info.bios_hardcoded_edid = edid;
396 return drm_edid_duplicate(drm_edid_raw(rdev->mode_info.bios_hardcoded_edid));
447 if (rdev->family == CHIP_RS300 ||
448 rdev->family == CHIP_RS400 ||
449 rdev->family == CHIP_RS480)
451 else if (rdev->family == CHIP_R300 ||
452 rdev->family == CHIP_R350) {
459 if (rdev->family == CHIP_R200 ||
460 rdev->family == CHIP_R300 ||
461 rdev->family == CHIP_R350) {
464 } else if (rdev->family == CHIP_RS300 ||
465 rdev->family == CHIP_RS400 ||
466 rdev->family == CHIP_RS480)
468 else if (rdev->family >= CHIP_RV350) {
538 switch (rdev->family) {
601 * reliably on some pre-r4xx hardware; not sure why.
673 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
676 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
683 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
685 if (rdev->family == CHIP_R300 ||
686 rdev->family == CHIP_R350) {
688 } else if (rdev->family == CHIP_RS300 ||
689 rdev->family == CHIP_RS400 ||
690 rdev->family == CHIP_RS480) {
693 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
698 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
699 } else if ((rdev->family == CHIP_R200) ||
700 (rdev->family >= CHIP_R300)) {
703 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
707 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
710 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
716 struct radeon_device *rdev = dev->dev_private;
718 struct radeon_pll *p1pll = &rdev->clock.p1pll;
719 struct radeon_pll *p2pll = &rdev->clock.p2pll;
720 struct radeon_pll *spll = &rdev->clock.spll;
721 struct radeon_pll *mpll = &rdev->clock.mpll;
730 p1pll->reference_freq = RBIOS16(pll_info + 0xe);
731 p1pll->reference_div = RBIOS16(pll_info + 0x10);
732 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);
733 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);
734 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
735 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
738 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);
739 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);
741 p1pll->pll_in_min = 40;
742 p1pll->pll_in_max = 500;
747 spll->reference_freq = RBIOS16(pll_info + 0x1a);
748 spll->reference_div = RBIOS16(pll_info + 0x1c);
749 spll->pll_out_min = RBIOS32(pll_info + 0x1e);
750 spll->pll_out_max = RBIOS32(pll_info + 0x22);
753 spll->pll_in_min = RBIOS32(pll_info + 0x48);
754 spll->pll_in_max = RBIOS32(pll_info + 0x4c);
757 spll->pll_in_min = 40;
758 spll->pll_in_max = 500;
762 mpll->reference_freq = RBIOS16(pll_info + 0x26);
763 mpll->reference_div = RBIOS16(pll_info + 0x28);
764 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);
765 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);
768 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);
769 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);
772 mpll->pll_in_min = 40;
773 mpll->pll_in_max = 500;
784 rdev->clock.default_sclk = sclk;
785 rdev->clock.default_mclk = mclk;
788 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);
790 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */
803 if (rdev->family == CHIP_RS400)
839 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];
845 *encoder)
847 struct drm_device *dev = encoder->base.dev;
848 struct radeon_device *rdev = dev->dev_private;
867 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
871 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
882 if (((rdev->pdev->device == 0x5159) &&
883 (rdev->pdev->subsystem_vendor == 0x174B) &&
884 (rdev->pdev->subsystem_device == 0x7c28)) ||
886 ((rdev->pdev->device == 0x514D) &&
887 (rdev->pdev->subsystem_vendor == 0x174B) &&
888 (rdev->pdev->subsystem_device == 0x7149))) {
920 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
924 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
928 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
932 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");
986 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];
987 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))
988 tv_dac->ps2_tvdac_adj = 0x00880000;
989 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
990 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
996 *encoder)
998 struct drm_device *dev = encoder->base.dev;
999 struct radeon_device *rdev = dev->dev_private;
1016 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1020 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1024 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1026 if (tv_dac->ps2_tvdac_adj)
1031 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1035 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1039 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1041 if (tv_dac->ps2_tvdac_adj)
1044 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);
1055 tv_dac->ps2_tvdac_adj =
1057 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1058 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1060 if (tv_dac->ps2_tvdac_adj)
1065 tv_dac->ps2_tvdac_adj =
1067 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;
1068 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;
1070 if (tv_dac->ps2_tvdac_adj)
1088 struct radeon_encoder_lvds *lvds;
1093 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1095 if (!lvds)
1101 /* These should be fail-safe defaults, fingers crossed */
1102 lvds->panel_pwr_delay = 200;
1103 lvds->panel_vcc_delay = 2000;
1105 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
1106 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;
1107 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
1110 lvds->native_mode.vdisplay =
1114 lvds->native_mode.vdisplay =
1118 lvds->native_mode.hdisplay =
1122 lvds->native_mode.hdisplay =
1125 if ((lvds->native_mode.hdisplay < 640) ||
1126 (lvds->native_mode.vdisplay < 480)) {
1127 lvds->native_mode.hdisplay = 640;
1128 lvds->native_mode.vdisplay = 480;
1134 lvds->use_bios_dividers = false;
1136 lvds->panel_ref_divider =
1138 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;
1139 lvds->panel_fb_divider = ppll_val & 0x7ff;
1141 if ((lvds->panel_ref_divider != 0) &&
1142 (lvds->panel_fb_divider > 3))
1143 lvds->use_bios_dividers = true;
1145 lvds->panel_vcc_delay = 200;
1148 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1149 lvds->native_mode.vdisplay);
1151 return lvds;
1155 *encoder)
1157 struct drm_device *dev = encoder->base.dev;
1158 struct radeon_device *rdev = dev->dev_private;
1163 struct radeon_encoder_lvds *lvds = NULL;
1168 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
1170 if (!lvds)
1179 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
1180 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
1182 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
1183 lvds->native_mode.vdisplay);
1185 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
1186 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
1188 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
1189 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
1190 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;
1192 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);
1193 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);
1194 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);
1195 if ((lvds->panel_ref_divider != 0) &&
1196 (lvds->panel_fb_divider > 3))
1197 lvds->use_bios_dividers = true;
1200 lvds->lvds_gen_cntl = 0xff00;
1202 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;
1205 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;
1209 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;
1212 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;
1215 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;
1222 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;
1225 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;
1228 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;
1231 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;
1233 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);
1240 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
1241 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {
1242 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;
1244 if (hss > lvds->native_mode.hdisplay)
1245 hss = (10 - 1) * 8;
1247 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1248 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;
1249 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1251 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1254 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1255 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));
1256 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1257 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));
1258 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1261 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
1262 lvds->native_mode.flags = 0;
1264 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1270 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);
1273 if (lvds)
1274 encoder->native_mode = lvds->native_mode;
1275 return lvds;
1299 bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
1302 struct drm_device *dev = encoder->base.dev;
1303 struct radeon_device *rdev = dev->dev_private;
1307 tmds->tmds_pll[i].value =
1308 default_tmds_pll[rdev->family][i].value;
1309 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;
1315 bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
1318 struct drm_device *dev = encoder->base.dev;
1319 struct radeon_device *rdev = dev->dev_private;
1334 tmds->tmds_pll[i].value =
1336 tmds->tmds_pll[i].freq =
1339 tmds->tmds_pll[i].freq,
1340 tmds->tmds_pll[i].value);
1348 tmds->tmds_pll[i].value =
1350 tmds->tmds_pll[i].freq =
1357 tmds->tmds_pll[i].freq,
1358 tmds->tmds_pll[i].value);
1368 bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
1371 struct drm_device *dev = encoder->base.dev;
1372 struct radeon_device *rdev = dev->dev_private;
1377 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1380 switch (rdev->mode_info.connector_table) {
1384 tmds->dvo_chip = DVO_SIL164;
1385 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1392 bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
1395 struct drm_device *dev = encoder->base.dev;
1396 struct radeon_device *rdev = dev->dev_private;
1402 tmds->i2c_bus = NULL;
1403 if (rdev->flags & RADEON_IS_IGP) {
1405 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1406 tmds->dvo_chip = DVO_SIL164;
1407 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */
1413 tmds->slave_addr = RBIOS8(offset + 4 + 2);
1414 tmds->slave_addr >>= 1; /* 7 bit addressing */
1424 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
1428 if (!tmds->i2c_bus) {
1438 struct radeon_device *rdev = dev->dev_private;
1442 rdev->mode_info.connector_table = radeon_connector_table;
1443 if (rdev->mode_info.connector_table == CT_NONE) {
1447 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;
1451 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;
1458 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1461 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1467 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;
1475 rdev->mode_info.connector_table = CT_IBOOK;
1478 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;
1481 rdev->mode_info.connector_table = CT_EMAC;
1484 rdev->mode_info.connector_table = CT_MINI_INTERNAL;
1487 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;
1491 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;
1492 } else if ((rdev->pdev->device == 0x4a48) &&
1493 (rdev->pdev->subsystem_vendor == 0x1002) &&
1494 (rdev->pdev->subsystem_device == 0x4a48)) {
1496 rdev->mode_info.connector_table = CT_MAC_X800;
1499 (rdev->pdev->device == 0x4150) &&
1500 (rdev->pdev->subsystem_vendor == 0x1002) &&
1501 (rdev->pdev->subsystem_device == 0x4150)) {
1503 rdev->mode_info.connector_table = CT_MAC_G5_9600;
1504 } else if ((rdev->pdev->device == 0x4c66) &&
1505 (rdev->pdev->subsystem_vendor == 0x1002) &&
1506 (rdev->pdev->subsystem_device == 0x4c66)) {
1508 rdev->mode_info.connector_table = CT_SAM440EP;
1513 rdev->mode_info.connector_table = CT_RN50_POWER;
1516 rdev->mode_info.connector_table = CT_GENERIC;
1519 switch (rdev->mode_info.connector_table) {
1522 rdev->mode_info.connector_table);
1524 if (rdev->flags & RADEON_SINGLE_CRTC) {
1525 /* VGA - primary dac */
1539 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1540 /* LVDS */
1555 /* VGA - primary dac */
1570 /* DVI-I - tv dac, int tmds */
1591 /* VGA - primary dac */
1607 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
1608 /* TV - tv dac */
1626 rdev->mode_info.connector_table);
1627 /* LVDS */
1639 /* VGA - TV DAC */
1651 /* TV - TV DAC */
1667 rdev->mode_info.connector_table);
1668 /* LVDS */
1680 /* DVI-I - primary dac, ext tmds */
1700 /* TV - TV DAC */
1716 rdev->mode_info.connector_table);
1717 /* LVDS */
1729 /* DVI-I - primary dac, int tmds */
1748 /* TV - TV DAC */
1764 rdev->mode_info.connector_table);
1765 /* LVDS */
1777 /* VGA - primary dac */
1789 /* TV - TV DAC */
1805 rdev->mode_info.connector_table);
1806 /* DVI-I - tv dac, ext tmds */
1826 /* TV - TV DAC */
1842 rdev->mode_info.connector_table);
1843 /* DVI-I - tv dac, int tmds */
1862 /* TV - TV DAC */
1878 rdev->mode_info.connector_table);
1879 /* DVI-D - int tmds */
1891 /* VGA - tv dac */
1903 /* TV - TV DAC */
1919 rdev->mode_info.connector_table);
1920 /* VGA - primary dac */
1932 /* VGA - tv dac */
1944 /* TV - TV DAC */
1959 DRM_INFO("Connector Table: %d (rn50-power)\n",
1960 rdev->mode_info.connector_table);
1961 /* VGA - primary dac */
1987 rdev->mode_info.connector_table);
1988 /* DVI - primary dac, internal tmds */
2007 /* DVI - tv dac, dvo */
2029 rdev->mode_info.connector_table);
2030 /* DVI - tv dac, dvo */
2049 /* ADC - primary dac, internal tmds */
2068 /* TV - TV DAC */
2084 rdev->mode_info.connector_table);
2085 /* LVDS */
2097 /* DVI-I - secondary dac, int tmds */
2116 /* VGA - primary dac */
2129 /* TV - TV DAC */
2145 rdev->mode_info.connector_table);
2146 /* DVI-I - tv dac, int tmds */
2165 /* VGA - primary dac */
2177 /* TV - TV DAC */
2193 rdev->mode_info.connector_table);
2209 struct radeon_device *rdev = dev->dev_private;
2212 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */
2213 if (rdev->pdev->device == 0x515e &&
2214 rdev->pdev->subsystem_vendor == 0x1014) {
2216 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
2220 /* X300 card with extra non-existent DVI port */
2221 if (rdev->pdev->device == 0x5B60 &&
2222 rdev->pdev->subsystem_vendor == 0x17af &&
2223 rdev->pdev->subsystem_device == 0x201e && bios_index == 2) {
2233 struct radeon_device *rdev = dev->dev_private;
2235 /* Acer 5102 has non-existent TV port */
2236 if (rdev->pdev->device == 0x5975 &&
2237 rdev->pdev->subsystem_vendor == 0x1025 &&
2238 rdev->pdev->subsystem_device == 0x009f)
2241 /* HP dc5750 has non-existent TV port */
2242 if (rdev->pdev->device == 0x5974 &&
2243 rdev->pdev->subsystem_vendor == 0x103c &&
2244 rdev->pdev->subsystem_device == 0x280a)
2247 /* MSI S270 has non-existent TV port */
2248 if (rdev->pdev->device == 0x5955 &&
2249 rdev->pdev->subsystem_vendor == 0x1462 &&
2250 rdev->pdev->subsystem_device == 0x0131)
2258 struct radeon_device *rdev = dev->dev_private;
2261 if (rdev->flags & RADEON_IS_IGP) {
2293 struct radeon_device *rdev = dev->dev_private;
2401 /* RV100 board with external TDMS bit mis-set.
2404 if (rdev->pdev->device == 0x5159 &&
2405 rdev->pdev->subsystem_vendor == 0x1014 &&
2406 rdev->pdev->subsystem_device == 0x029A) {
2532 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {
2586 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
2630 rdev->pm.default_power_state_index = -1;
2633 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state),
2635 if (rdev->pm.power_state) {
2637 rdev->pm.power_state[0].clock_info =
2640 rdev->pm.power_state[1].clock_info =
2643 if (!rdev->pm.power_state[0].clock_info ||
2644 !rdev->pm.power_state[1].clock_info)
2685 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2686 if (rdev->pm.i2c_bus) {
2691 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2698 if ((rdev->pdev->device == 0x4152) &&
2699 (rdev->pdev->subsystem_vendor == 0x1043) &&
2700 (rdev->pdev->subsystem_device == 0xc002)) {
2702 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2703 if (rdev->pm.i2c_bus) {
2708 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2715 if (rdev->flags & RADEON_IS_MOBILITY) {
2720 rdev->pm.power_state[state_index].num_clock_modes = 1;
2721 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);
2722 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);
2723 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2724 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2726 rdev->pm.power_state[state_index].type =
2731 rdev->pm.power_state[state_index].misc = misc;
2732 rdev->pm.power_state[state_index].misc2 = misc2;
2734 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
2736 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2739 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2741 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;
2743 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2746 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2751 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =
2754 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);
2756 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;
2761 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;
2764 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;
2767 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;
2770 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;
2773 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;
2777 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2779 rdev->pm.power_state[state_index].pcie_lanes =
2781 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2792 rdev->pm.power_state[state_index].type =
2794 rdev->pm.power_state[state_index].num_clock_modes = 1;
2795 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2796 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2797 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
2799 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))
2800 rdev->pm.power_state[state_index].clock_info[0].voltage =
2801 rdev->pm.power_state[0].clock_info[0].voltage;
2803 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2804 rdev->pm.power_state[state_index].pcie_lanes = 16;
2805 rdev->pm.power_state[state_index].flags = 0;
2806 rdev->pm.default_power_state_index = state_index;
2807 rdev->pm.num_power_states = state_index + 1;
2809 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2810 rdev->pm.current_clock_mode_index = 0;
2814 rdev->pm.default_power_state_index = state_index;
2815 rdev->pm.num_power_states = 0;
2817 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2818 rdev->pm.current_clock_mode_index = 0;
2821 void radeon_external_tmds_setup(struct drm_encoder *encoder)
2823 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2824 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2829 switch (tmds->dvo_chip) {
2832 radeon_i2c_put_byte(tmds->i2c_bus,
2833 tmds->slave_addr,
2835 radeon_i2c_put_byte(tmds->i2c_bus,
2836 tmds->slave_addr,
2838 radeon_i2c_put_byte(tmds->i2c_bus,
2839 tmds->slave_addr,
2841 radeon_i2c_put_byte(tmds->i2c_bus,
2842 tmds->slave_addr,
2844 radeon_i2c_put_byte(tmds->i2c_bus,
2845 tmds->slave_addr,
2849 /* sil 1178 - untested */
2868 bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
2870 struct drm_device *dev = encoder->dev;
2871 struct radeon_device *rdev = dev->dev_private;
2872 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2877 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
2882 if (rdev->flags & RADEON_IS_IGP) {
2928 radeon_i2c_put_byte(tmds->i2c_bus,
2936 blocks--;
2983 radeon_i2c_put_byte(tmds->i2c_bus,
2984 tmds->slave_addr,
3001 struct radeon_device *rdev = dev->dev_private;
3052 while (val--) {
3061 while (val--) {
3080 struct radeon_device *rdev = dev->dev_private;
3120 while (tmp--) {
3129 while (tmp--) {
3171 struct radeon_device *rdev = dev->dev_private;
3189 while (tmp--) {
3218 struct radeon_device *rdev = dev->dev_private;
3235 while (ram--) {
3249 struct radeon_device *rdev = dev->dev_private;
3256 if (rdev->flags & RADEON_IS_IGP)
3266 if ((rdev->family < CHIP_R200) &&
3276 rev = RBIOS8(offset - 1);
3278 if ((rdev->family < CHIP_R200)
3311 struct radeon_device *rdev = dev->dev_private;
3315 if (rdev->bios == NULL)
3333 if (!(rdev->flags & RADEON_IS_IGP)) {
3356 * - it hangs on resume inside the dynclk 1 table.
3358 if (rdev->family == CHIP_RS480 &&
3359 rdev->pdev->subsystem_vendor == 0x103c &&
3360 rdev->pdev->subsystem_device == 0x308b)
3364 * - it hangs on resume inside the dynclk 1 table.
3366 if (rdev->family == CHIP_RS480 &&
3367 rdev->pdev->subsystem_vendor == 0x103c &&
3368 rdev->pdev->subsystem_device == 0x30a4)
3372 * - it hangs on resume inside the dynclk 1 table.
3374 if (rdev->family == CHIP_RS480 &&
3375 rdev->pdev->subsystem_vendor == 0x103c &&
3376 rdev->pdev->subsystem_device == 0x30ae)
3380 * - it hangs on resume inside the dynclk 1 table.
3382 if (rdev->family == CHIP_RS480 &&
3383 rdev->pdev->subsystem_vendor == 0x103c &&
3384 rdev->pdev->subsystem_device == 0x280a)
3386 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume
3387 * - it hangs on resume inside the dynclk 1 table.
3389 if (rdev->family == CHIP_RS400 &&
3390 rdev->pdev->subsystem_vendor == 0x1179 &&
3391 rdev->pdev->subsystem_device == 0xff31)
3403 struct radeon_device *rdev = dev->dev_private;
3425 void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)
3427 struct drm_device *dev = encoder->dev;
3428 struct radeon_device *rdev = dev->dev_private;
3443 struct drm_encoder *encoder,
3446 struct drm_device *dev = connector->dev;
3447 struct radeon_device *rdev = dev->dev_private;
3450 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3454 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
3455 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
3460 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */
3470 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
3471 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
3484 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
3485 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
3498 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
3499 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
3512 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
3513 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
3526 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
3527 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
3545 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
3547 struct drm_device *dev = encoder->dev;
3548 struct radeon_device *rdev = dev->dev_private;
3549 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3552 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
3556 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
3560 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
3564 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
3568 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
3572 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
3580 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
3582 struct drm_device *dev = encoder->dev;
3583 struct radeon_device *rdev = dev->dev_private;
3584 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
3587 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
3593 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3599 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3605 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {