Lines Matching refs:post_div
43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
59 if (post_div == 2) in radeon_legacy_get_engine_clock()
61 else if (post_div == 3) in radeon_legacy_get_engine_clock()
63 else if (post_div == 4) in radeon_legacy_get_engine_clock()
73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
89 if (post_div == 2) in radeon_legacy_get_memory_clock()
91 else if (post_div == 3) in radeon_legacy_get_memory_clock()
93 else if (post_div == 4) in radeon_legacy_get_memory_clock()
353 int *fb_div, int *post_div) in calc_eng_mem_clock() argument
364 *post_div = 8; in calc_eng_mem_clock()
367 *post_div = 4; in calc_eng_mem_clock()
370 *post_div = 2; in calc_eng_mem_clock()
373 *post_div = 1; in calc_eng_mem_clock()
384 req_clock /= *post_div; in calc_eng_mem_clock()
394 int fb_div, post_div; in radeon_legacy_set_engine_clock() local
398 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); in radeon_legacy_set_engine_clock()
430 if ((eng_clock * post_div) >= 90000) in radeon_legacy_set_engine_clock()
450 switch (post_div) { in radeon_legacy_set_engine_clock()