Lines Matching +full:al +full:- +full:thermal
96 pr_cont(" thermal"); in r600_dpm_print_class_info()
145 if (rps == rdev->pm.dpm.current_ps) in r600_dpm_print_ps_status()
147 if (rps == rdev->pm.dpm.requested_ps) in r600_dpm_print_ps_status()
149 if (rps == rdev->pm.dpm.boot_ps) in r600_dpm_print_ps_status()
162 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { in r600_dpm_get_vblank_time()
163 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in r600_dpm_get_vblank_time()
165 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { in r600_dpm_get_vblank_time()
167 radeon_crtc->hw_mode.crtc_htotal * in r600_dpm_get_vblank_time()
168 (radeon_crtc->hw_mode.crtc_vblank_end - in r600_dpm_get_vblank_time()
169 radeon_crtc->hw_mode.crtc_vdisplay + in r600_dpm_get_vblank_time()
170 (radeon_crtc->v_border * 2)); in r600_dpm_get_vblank_time()
172 vblank_time_us = vblank_in_pixels * 1000 / radeon_crtc->hw_mode.clock; in r600_dpm_get_vblank_time()
188 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { in r600_dpm_get_vrefresh()
189 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in r600_dpm_get_vrefresh()
191 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { in r600_dpm_get_vrefresh()
192 vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode); in r600_dpm_get_vrefresh()
221 u32 k, a, ah, al; in r600_calculate_at() local
225 return -EINVAL; in r600_calculate_at()
228 t1 = (t * (k - 100)); in r600_calculate_at()
232 al = a - ah; in r600_calculate_at()
234 *th = t - ah; in r600_calculate_at()
235 *tl = t + al; in r600_calculate_at()
251 for (i = 0; i < rdev->usec_timeout; i++) { in r600_gfx_clockgating_enable()
329 for (i = 0; i < rdev->usec_timeout; i++) { in r600_wait_for_spll_change()
531 u32 ix = 3 - (3 & index); in r600_voltage_control_program_voltages()
537 tmp = (tmp & ~mask) | ((pins >> (32 - (3 * ix))) & mask); in r600_voltage_control_program_voltages()
562 u32 ix = 3 - (3 & index); in r600_power_level_enable()
575 u32 ix = 3 - (3 & index); in r600_power_level_set_voltage_index()
584 u32 ix = 3 - (3 & index); in r600_power_level_set_mem_clock_index()
593 u32 ix = 3 - (3 & index); in r600_power_level_set_eng_clock_index()
603 u32 ix = 3 - (3 & index); in r600_power_level_set_watermark_id()
614 u32 ix = 3 - (3 & index); in r600_power_level_set_pcie_gen2()
652 for (i = 0; i < rdev->usec_timeout; i++) { in r600_wait_for_power_level_unequal()
658 for (i = 0; i < rdev->usec_timeout; i++) { in r600_wait_for_power_level_unequal()
670 for (i = 0; i < rdev->usec_timeout; i++) { in r600_wait_for_power_level()
676 for (i = 0; i < rdev->usec_timeout; i++) { in r600_wait_for_power_level()
748 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); in r600_set_thermal_temperature_range()
749 return -EINVAL; in r600_set_thermal_temperature_range()
756 rdev->pm.dpm.thermal.min_temp = low_temp; in r600_set_thermal_temperature_range()
757 rdev->pm.dpm.thermal.max_temp = high_temp; in r600_set_thermal_temperature_range()
789 if (rdev->irq.installed && in r600_dpm_late_enable()
790 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { in r600_dpm_late_enable()
794 rdev->irq.dpm_thermal = true; in r600_dpm_late_enable()
824 radeon_table->entries = kcalloc(atom_table->ucNumEntries, in r600_parse_clk_voltage_dep_table()
827 if (!radeon_table->entries) in r600_parse_clk_voltage_dep_table()
828 return -ENOMEM; in r600_parse_clk_voltage_dep_table()
830 entry = &atom_table->entries[0]; in r600_parse_clk_voltage_dep_table()
831 for (i = 0; i < atom_table->ucNumEntries; i++) { in r600_parse_clk_voltage_dep_table()
832 radeon_table->entries[i].clk = le16_to_cpu(entry->usClockLow) | in r600_parse_clk_voltage_dep_table()
833 (entry->ucClockHigh << 16); in r600_parse_clk_voltage_dep_table()
834 radeon_table->entries[i].v = le16_to_cpu(entry->usVoltage); in r600_parse_clk_voltage_dep_table()
838 radeon_table->count = atom_table->ucNumEntries; in r600_parse_clk_voltage_dep_table()
845 struct radeon_mode_info *mode_info = &rdev->mode_info; in r600_get_platform_caps()
851 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, in r600_get_platform_caps()
853 return -EINVAL; in r600_get_platform_caps()
854 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in r600_get_platform_caps()
856 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); in r600_get_platform_caps()
857 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); in r600_get_platform_caps()
858 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); in r600_get_platform_caps()
873 struct radeon_mode_info *mode_info = &rdev->mode_info; in r600_parse_extended_power_table()
882 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, in r600_parse_extended_power_table()
884 return -EINVAL; in r600_parse_extended_power_table()
885 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); in r600_parse_extended_power_table()
888 if (le16_to_cpu(power_info->pplib.usTableSize) >= in r600_parse_extended_power_table()
890 if (power_info->pplib3.usFanTableOffset) { in r600_parse_extended_power_table()
891 fan_info = (union fan_info *)(mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
892 le16_to_cpu(power_info->pplib3.usFanTableOffset)); in r600_parse_extended_power_table()
893 rdev->pm.dpm.fan.t_hyst = fan_info->fan.ucTHyst; in r600_parse_extended_power_table()
894 rdev->pm.dpm.fan.t_min = le16_to_cpu(fan_info->fan.usTMin); in r600_parse_extended_power_table()
895 rdev->pm.dpm.fan.t_med = le16_to_cpu(fan_info->fan.usTMed); in r600_parse_extended_power_table()
896 rdev->pm.dpm.fan.t_high = le16_to_cpu(fan_info->fan.usTHigh); in r600_parse_extended_power_table()
897 rdev->pm.dpm.fan.pwm_min = le16_to_cpu(fan_info->fan.usPWMMin); in r600_parse_extended_power_table()
898 rdev->pm.dpm.fan.pwm_med = le16_to_cpu(fan_info->fan.usPWMMed); in r600_parse_extended_power_table()
899 rdev->pm.dpm.fan.pwm_high = le16_to_cpu(fan_info->fan.usPWMHigh); in r600_parse_extended_power_table()
900 if (fan_info->fan.ucFanTableFormat >= 2) in r600_parse_extended_power_table()
901 rdev->pm.dpm.fan.t_max = le16_to_cpu(fan_info->fan2.usTMax); in r600_parse_extended_power_table()
903 rdev->pm.dpm.fan.t_max = 10900; in r600_parse_extended_power_table()
904 rdev->pm.dpm.fan.cycle_delay = 100000; in r600_parse_extended_power_table()
905 if (fan_info->fan.ucFanTableFormat >= 3) { in r600_parse_extended_power_table()
906 rdev->pm.dpm.fan.control_mode = fan_info->fan3.ucFanControlMode; in r600_parse_extended_power_table()
907 rdev->pm.dpm.fan.default_max_fan_pwm = in r600_parse_extended_power_table()
908 le16_to_cpu(fan_info->fan3.usFanPWMMax); in r600_parse_extended_power_table()
909 rdev->pm.dpm.fan.default_fan_output_sensitivity = 4836; in r600_parse_extended_power_table()
910 rdev->pm.dpm.fan.fan_output_sensitivity = in r600_parse_extended_power_table()
911 le16_to_cpu(fan_info->fan3.usFanOutputSensitivity); in r600_parse_extended_power_table()
913 rdev->pm.dpm.fan.ucode_fan_control = true; in r600_parse_extended_power_table()
918 if (le16_to_cpu(power_info->pplib.usTableSize) >= in r600_parse_extended_power_table()
920 if (power_info->pplib4.usVddcDependencyOnSCLKOffset) { in r600_parse_extended_power_table()
922 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
923 le16_to_cpu(power_info->pplib4.usVddcDependencyOnSCLKOffset)); in r600_parse_extended_power_table()
924 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in r600_parse_extended_power_table()
929 if (power_info->pplib4.usVddciDependencyOnMCLKOffset) { in r600_parse_extended_power_table()
931 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
932 le16_to_cpu(power_info->pplib4.usVddciDependencyOnMCLKOffset)); in r600_parse_extended_power_table()
933 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in r600_parse_extended_power_table()
936 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
940 if (power_info->pplib4.usVddcDependencyOnMCLKOffset) { in r600_parse_extended_power_table()
942 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
943 le16_to_cpu(power_info->pplib4.usVddcDependencyOnMCLKOffset)); in r600_parse_extended_power_table()
944 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in r600_parse_extended_power_table()
947 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
948 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); in r600_parse_extended_power_table()
952 if (power_info->pplib4.usMvddDependencyOnMCLKOffset) { in r600_parse_extended_power_table()
954 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
955 le16_to_cpu(power_info->pplib4.usMvddDependencyOnMCLKOffset)); in r600_parse_extended_power_table()
956 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in r600_parse_extended_power_table()
959 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
960 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); in r600_parse_extended_power_table()
961 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); in r600_parse_extended_power_table()
965 if (power_info->pplib4.usMaxClockVoltageOnDCOffset) { in r600_parse_extended_power_table()
968 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
969 le16_to_cpu(power_info->pplib4.usMaxClockVoltageOnDCOffset)); in r600_parse_extended_power_table()
970 if (clk_v->ucNumEntries) { in r600_parse_extended_power_table()
971 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in r600_parse_extended_power_table()
972 le16_to_cpu(clk_v->entries[0].usSclkLow) | in r600_parse_extended_power_table()
973 (clk_v->entries[0].ucSclkHigh << 16); in r600_parse_extended_power_table()
974 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in r600_parse_extended_power_table()
975 le16_to_cpu(clk_v->entries[0].usMclkLow) | in r600_parse_extended_power_table()
976 (clk_v->entries[0].ucMclkHigh << 16); in r600_parse_extended_power_table()
977 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in r600_parse_extended_power_table()
978 le16_to_cpu(clk_v->entries[0].usVddc); in r600_parse_extended_power_table()
979 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in r600_parse_extended_power_table()
980 le16_to_cpu(clk_v->entries[0].usVddci); in r600_parse_extended_power_table()
983 if (power_info->pplib4.usVddcPhaseShedLimitsTableOffset) { in r600_parse_extended_power_table()
986 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
987 le16_to_cpu(power_info->pplib4.usVddcPhaseShedLimitsTableOffset)); in r600_parse_extended_power_table()
990 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = in r600_parse_extended_power_table()
991 kcalloc(psl->ucNumEntries, in r600_parse_extended_power_table()
994 if (!rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { in r600_parse_extended_power_table()
996 return -ENOMEM; in r600_parse_extended_power_table()
999 entry = &psl->entries[0]; in r600_parse_extended_power_table()
1000 for (i = 0; i < psl->ucNumEntries; i++) { in r600_parse_extended_power_table()
1001 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].sclk = in r600_parse_extended_power_table()
1002 le16_to_cpu(entry->usSclkLow) | (entry->ucSclkHigh << 16); in r600_parse_extended_power_table()
1003 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].mclk = in r600_parse_extended_power_table()
1004 le16_to_cpu(entry->usMclkLow) | (entry->ucMclkHigh << 16); in r600_parse_extended_power_table()
1005 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.entries[i].voltage = in r600_parse_extended_power_table()
1006 le16_to_cpu(entry->usVoltage); in r600_parse_extended_power_table()
1010 rdev->pm.dpm.dyn_state.phase_shedding_limits_table.count = in r600_parse_extended_power_table()
1011 psl->ucNumEntries; in r600_parse_extended_power_table()
1016 if (le16_to_cpu(power_info->pplib.usTableSize) >= in r600_parse_extended_power_table()
1018 rdev->pm.dpm.tdp_limit = le32_to_cpu(power_info->pplib5.ulTDPLimit); in r600_parse_extended_power_table()
1019 rdev->pm.dpm.near_tdp_limit = le32_to_cpu(power_info->pplib5.ulNearTDPLimit); in r600_parse_extended_power_table()
1020 rdev->pm.dpm.near_tdp_limit_adjusted = rdev->pm.dpm.near_tdp_limit; in r600_parse_extended_power_table()
1021 rdev->pm.dpm.tdp_od_limit = le16_to_cpu(power_info->pplib5.usTDPODLimit); in r600_parse_extended_power_table()
1022 if (rdev->pm.dpm.tdp_od_limit) in r600_parse_extended_power_table()
1023 rdev->pm.dpm.power_control = true; in r600_parse_extended_power_table()
1025 rdev->pm.dpm.power_control = false; in r600_parse_extended_power_table()
1026 rdev->pm.dpm.tdp_adjustment = 0; in r600_parse_extended_power_table()
1027 rdev->pm.dpm.sq_ramping_threshold = le32_to_cpu(power_info->pplib5.ulSQRampingThreshold); in r600_parse_extended_power_table()
1028 rdev->pm.dpm.cac_leakage = le32_to_cpu(power_info->pplib5.ulCACLeakage); in r600_parse_extended_power_table()
1029 rdev->pm.dpm.load_line_slope = le16_to_cpu(power_info->pplib5.usLoadLineSlope); in r600_parse_extended_power_table()
1030 if (power_info->pplib5.usCACLeakageTableOffset) { in r600_parse_extended_power_table()
1033 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1034 le16_to_cpu(power_info->pplib5.usCACLeakageTableOffset)); in r600_parse_extended_power_table()
1036 u32 size = cac_table->ucNumEntries * sizeof(struct radeon_cac_leakage_table); in r600_parse_extended_power_table()
1037 rdev->pm.dpm.dyn_state.cac_leakage_table.entries = kzalloc(size, GFP_KERNEL); in r600_parse_extended_power_table()
1038 if (!rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in r600_parse_extended_power_table()
1040 return -ENOMEM; in r600_parse_extended_power_table()
1042 entry = &cac_table->entries[0]; in r600_parse_extended_power_table()
1043 for (i = 0; i < cac_table->ucNumEntries; i++) { in r600_parse_extended_power_table()
1044 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in r600_parse_extended_power_table()
1045 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1 = in r600_parse_extended_power_table()
1046 le16_to_cpu(entry->usVddc1); in r600_parse_extended_power_table()
1047 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2 = in r600_parse_extended_power_table()
1048 le16_to_cpu(entry->usVddc2); in r600_parse_extended_power_table()
1049 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3 = in r600_parse_extended_power_table()
1050 le16_to_cpu(entry->usVddc3); in r600_parse_extended_power_table()
1052 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc = in r600_parse_extended_power_table()
1053 le16_to_cpu(entry->usVddc); in r600_parse_extended_power_table()
1054 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage = in r600_parse_extended_power_table()
1055 le32_to_cpu(entry->ulLeakageValue); in r600_parse_extended_power_table()
1060 rdev->pm.dpm.dyn_state.cac_leakage_table.count = cac_table->ucNumEntries; in r600_parse_extended_power_table()
1065 if (le16_to_cpu(power_info->pplib.usTableSize) >= in r600_parse_extended_power_table()
1068 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1069 le16_to_cpu(power_info->pplib3.usExtendendedHeaderOffset)); in r600_parse_extended_power_table()
1070 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2) && in r600_parse_extended_power_table()
1071 ext_hdr->usVCETableOffset) { in r600_parse_extended_power_table()
1073 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1074 le16_to_cpu(ext_hdr->usVCETableOffset) + 1); in r600_parse_extended_power_table()
1077 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1078 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + in r600_parse_extended_power_table()
1079 1 + array->ucNumEntries * sizeof(VCEClockInfo)); in r600_parse_extended_power_table()
1082 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1083 le16_to_cpu(ext_hdr->usVCETableOffset) + 1 + in r600_parse_extended_power_table()
1084 1 + (array->ucNumEntries * sizeof (VCEClockInfo)) + in r600_parse_extended_power_table()
1085 1 + (limits->numEntries * sizeof(ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record))); in r600_parse_extended_power_table()
1089 u32 size = limits->numEntries * in r600_parse_extended_power_table()
1091 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries = in r600_parse_extended_power_table()
1093 if (!rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries) { in r600_parse_extended_power_table()
1095 return -ENOMEM; in r600_parse_extended_power_table()
1097 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count = in r600_parse_extended_power_table()
1098 limits->numEntries; in r600_parse_extended_power_table()
1099 entry = &limits->entries[0]; in r600_parse_extended_power_table()
1100 state_entry = &states->entries[0]; in r600_parse_extended_power_table()
1101 for (i = 0; i < limits->numEntries; i++) { in r600_parse_extended_power_table()
1103 ((u8 *)&array->entries[0] + in r600_parse_extended_power_table()
1104 (entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); in r600_parse_extended_power_table()
1105 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = in r600_parse_extended_power_table()
1106 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); in r600_parse_extended_power_table()
1107 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].ecclk = in r600_parse_extended_power_table()
1108 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); in r600_parse_extended_power_table()
1109 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v = in r600_parse_extended_power_table()
1110 le16_to_cpu(entry->usVoltage); in r600_parse_extended_power_table()
1114 for (i = 0; i < states->numEntries; i++) { in r600_parse_extended_power_table()
1118 ((u8 *)&array->entries[0] + in r600_parse_extended_power_table()
1119 (state_entry->ucVCEClockInfoIndex * sizeof(VCEClockInfo))); in r600_parse_extended_power_table()
1120 rdev->pm.dpm.vce_states[i].evclk = in r600_parse_extended_power_table()
1121 le16_to_cpu(vce_clk->usEVClkLow) | (vce_clk->ucEVClkHigh << 16); in r600_parse_extended_power_table()
1122 rdev->pm.dpm.vce_states[i].ecclk = in r600_parse_extended_power_table()
1123 le16_to_cpu(vce_clk->usECClkLow) | (vce_clk->ucECClkHigh << 16); in r600_parse_extended_power_table()
1124 rdev->pm.dpm.vce_states[i].clk_idx = in r600_parse_extended_power_table()
1125 state_entry->ucClockInfoIndex & 0x3f; in r600_parse_extended_power_table()
1126 rdev->pm.dpm.vce_states[i].pstate = in r600_parse_extended_power_table()
1127 (state_entry->ucClockInfoIndex & 0xc0) >> 6; in r600_parse_extended_power_table()
1132 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3) && in r600_parse_extended_power_table()
1133 ext_hdr->usUVDTableOffset) { in r600_parse_extended_power_table()
1135 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1136 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1); in r600_parse_extended_power_table()
1139 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1140 le16_to_cpu(ext_hdr->usUVDTableOffset) + 1 + in r600_parse_extended_power_table()
1141 1 + (array->ucNumEntries * sizeof (UVDClockInfo))); in r600_parse_extended_power_table()
1143 u32 size = limits->numEntries * in r600_parse_extended_power_table()
1145 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries = in r600_parse_extended_power_table()
1147 if (!rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries) { in r600_parse_extended_power_table()
1149 return -ENOMEM; in r600_parse_extended_power_table()
1151 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count = in r600_parse_extended_power_table()
1152 limits->numEntries; in r600_parse_extended_power_table()
1153 entry = &limits->entries[0]; in r600_parse_extended_power_table()
1154 for (i = 0; i < limits->numEntries; i++) { in r600_parse_extended_power_table()
1156 ((u8 *)&array->entries[0] + in r600_parse_extended_power_table()
1157 (entry->ucUVDClockInfoIndex * sizeof(UVDClockInfo))); in r600_parse_extended_power_table()
1158 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].vclk = in r600_parse_extended_power_table()
1159 le16_to_cpu(uvd_clk->usVClkLow) | (uvd_clk->ucVClkHigh << 16); in r600_parse_extended_power_table()
1160 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].dclk = in r600_parse_extended_power_table()
1161 le16_to_cpu(uvd_clk->usDClkLow) | (uvd_clk->ucDClkHigh << 16); in r600_parse_extended_power_table()
1162 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v = in r600_parse_extended_power_table()
1163 le16_to_cpu(entry->usVoltage); in r600_parse_extended_power_table()
1168 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4) && in r600_parse_extended_power_table()
1169 ext_hdr->usSAMUTableOffset) { in r600_parse_extended_power_table()
1172 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1173 le16_to_cpu(ext_hdr->usSAMUTableOffset) + 1); in r600_parse_extended_power_table()
1175 u32 size = limits->numEntries * in r600_parse_extended_power_table()
1177 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries = in r600_parse_extended_power_table()
1179 if (!rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries) { in r600_parse_extended_power_table()
1181 return -ENOMEM; in r600_parse_extended_power_table()
1183 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count = in r600_parse_extended_power_table()
1184 limits->numEntries; in r600_parse_extended_power_table()
1185 entry = &limits->entries[0]; in r600_parse_extended_power_table()
1186 for (i = 0; i < limits->numEntries; i++) { in r600_parse_extended_power_table()
1187 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].clk = in r600_parse_extended_power_table()
1188 le16_to_cpu(entry->usSAMClockLow) | (entry->ucSAMClockHigh << 16); in r600_parse_extended_power_table()
1189 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v = in r600_parse_extended_power_table()
1190 le16_to_cpu(entry->usVoltage); in r600_parse_extended_power_table()
1195 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5) && in r600_parse_extended_power_table()
1196 ext_hdr->usPPMTableOffset) { in r600_parse_extended_power_table()
1198 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1199 le16_to_cpu(ext_hdr->usPPMTableOffset)); in r600_parse_extended_power_table()
1200 rdev->pm.dpm.dyn_state.ppm_table = in r600_parse_extended_power_table()
1202 if (!rdev->pm.dpm.dyn_state.ppm_table) { in r600_parse_extended_power_table()
1204 return -ENOMEM; in r600_parse_extended_power_table()
1206 rdev->pm.dpm.dyn_state.ppm_table->ppm_design = ppm->ucPpmDesign; in r600_parse_extended_power_table()
1207 rdev->pm.dpm.dyn_state.ppm_table->cpu_core_number = in r600_parse_extended_power_table()
1208 le16_to_cpu(ppm->usCpuCoreNumber); in r600_parse_extended_power_table()
1209 rdev->pm.dpm.dyn_state.ppm_table->platform_tdp = in r600_parse_extended_power_table()
1210 le32_to_cpu(ppm->ulPlatformTDP); in r600_parse_extended_power_table()
1211 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdp = in r600_parse_extended_power_table()
1212 le32_to_cpu(ppm->ulSmallACPlatformTDP); in r600_parse_extended_power_table()
1213 rdev->pm.dpm.dyn_state.ppm_table->platform_tdc = in r600_parse_extended_power_table()
1214 le32_to_cpu(ppm->ulPlatformTDC); in r600_parse_extended_power_table()
1215 rdev->pm.dpm.dyn_state.ppm_table->small_ac_platform_tdc = in r600_parse_extended_power_table()
1216 le32_to_cpu(ppm->ulSmallACPlatformTDC); in r600_parse_extended_power_table()
1217 rdev->pm.dpm.dyn_state.ppm_table->apu_tdp = in r600_parse_extended_power_table()
1218 le32_to_cpu(ppm->ulApuTDP); in r600_parse_extended_power_table()
1219 rdev->pm.dpm.dyn_state.ppm_table->dgpu_tdp = in r600_parse_extended_power_table()
1220 le32_to_cpu(ppm->ulDGpuTDP); in r600_parse_extended_power_table()
1221 rdev->pm.dpm.dyn_state.ppm_table->dgpu_ulv_power = in r600_parse_extended_power_table()
1222 le32_to_cpu(ppm->ulDGpuUlvPower); in r600_parse_extended_power_table()
1223 rdev->pm.dpm.dyn_state.ppm_table->tj_max = in r600_parse_extended_power_table()
1224 le32_to_cpu(ppm->ulTjmax); in r600_parse_extended_power_table()
1226 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6) && in r600_parse_extended_power_table()
1227 ext_hdr->usACPTableOffset) { in r600_parse_extended_power_table()
1230 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1231 le16_to_cpu(ext_hdr->usACPTableOffset) + 1); in r600_parse_extended_power_table()
1233 u32 size = limits->numEntries * in r600_parse_extended_power_table()
1235 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries = in r600_parse_extended_power_table()
1237 if (!rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries) { in r600_parse_extended_power_table()
1239 return -ENOMEM; in r600_parse_extended_power_table()
1241 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count = in r600_parse_extended_power_table()
1242 limits->numEntries; in r600_parse_extended_power_table()
1243 entry = &limits->entries[0]; in r600_parse_extended_power_table()
1244 for (i = 0; i < limits->numEntries; i++) { in r600_parse_extended_power_table()
1245 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].clk = in r600_parse_extended_power_table()
1246 le16_to_cpu(entry->usACPClockLow) | (entry->ucACPClockHigh << 16); in r600_parse_extended_power_table()
1247 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v = in r600_parse_extended_power_table()
1248 le16_to_cpu(entry->usVoltage); in r600_parse_extended_power_table()
1253 if ((le16_to_cpu(ext_hdr->usSize) >= SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7) && in r600_parse_extended_power_table()
1254 ext_hdr->usPowerTuneTableOffset) { in r600_parse_extended_power_table()
1255 u8 rev = *(u8 *)(mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1256 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in r600_parse_extended_power_table()
1258 rdev->pm.dpm.dyn_state.cac_tdp_table = in r600_parse_extended_power_table()
1260 if (!rdev->pm.dpm.dyn_state.cac_tdp_table) { in r600_parse_extended_power_table()
1262 return -ENOMEM; in r600_parse_extended_power_table()
1266 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1267 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in r600_parse_extended_power_table()
1268 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = in r600_parse_extended_power_table()
1269 le16_to_cpu(ppt->usMaximumPowerDeliveryLimit); in r600_parse_extended_power_table()
1270 pt = &ppt->power_tune_table; in r600_parse_extended_power_table()
1273 (mode_info->atom_context->bios + data_offset + in r600_parse_extended_power_table()
1274 le16_to_cpu(ext_hdr->usPowerTuneTableOffset)); in r600_parse_extended_power_table()
1275 rdev->pm.dpm.dyn_state.cac_tdp_table->maximum_power_delivery_limit = 255; in r600_parse_extended_power_table()
1276 pt = &ppt->power_tune_table; in r600_parse_extended_power_table()
1278 rdev->pm.dpm.dyn_state.cac_tdp_table->tdp = le16_to_cpu(pt->usTDP); in r600_parse_extended_power_table()
1279 rdev->pm.dpm.dyn_state.cac_tdp_table->configurable_tdp = in r600_parse_extended_power_table()
1280 le16_to_cpu(pt->usConfigurableTDP); in r600_parse_extended_power_table()
1281 rdev->pm.dpm.dyn_state.cac_tdp_table->tdc = le16_to_cpu(pt->usTDC); in r600_parse_extended_power_table()
1282 rdev->pm.dpm.dyn_state.cac_tdp_table->battery_power_limit = in r600_parse_extended_power_table()
1283 le16_to_cpu(pt->usBatteryPowerLimit); in r600_parse_extended_power_table()
1284 rdev->pm.dpm.dyn_state.cac_tdp_table->small_power_limit = in r600_parse_extended_power_table()
1285 le16_to_cpu(pt->usSmallPowerLimit); in r600_parse_extended_power_table()
1286 rdev->pm.dpm.dyn_state.cac_tdp_table->low_cac_leakage = in r600_parse_extended_power_table()
1287 le16_to_cpu(pt->usLowCACLeakage); in r600_parse_extended_power_table()
1288 rdev->pm.dpm.dyn_state.cac_tdp_table->high_cac_leakage = in r600_parse_extended_power_table()
1289 le16_to_cpu(pt->usHighCACLeakage); in r600_parse_extended_power_table()
1298 struct radeon_dpm_dynamic_state *dyn_state = &rdev->pm.dpm.dyn_state; in r600_free_extended_power_table()
1300 kfree(dyn_state->vddc_dependency_on_sclk.entries); in r600_free_extended_power_table()
1301 kfree(dyn_state->vddci_dependency_on_mclk.entries); in r600_free_extended_power_table()
1302 kfree(dyn_state->vddc_dependency_on_mclk.entries); in r600_free_extended_power_table()
1303 kfree(dyn_state->mvdd_dependency_on_mclk.entries); in r600_free_extended_power_table()
1304 kfree(dyn_state->cac_leakage_table.entries); in r600_free_extended_power_table()
1305 kfree(dyn_state->phase_shedding_limits_table.entries); in r600_free_extended_power_table()
1306 kfree(dyn_state->ppm_table); in r600_free_extended_power_table()
1307 kfree(dyn_state->cac_tdp_table); in r600_free_extended_power_table()
1308 kfree(dyn_state->vce_clock_voltage_dependency_table.entries); in r600_free_extended_power_table()
1309 kfree(dyn_state->uvd_clock_voltage_dependency_table.entries); in r600_free_extended_power_table()
1310 kfree(dyn_state->samu_clock_voltage_dependency_table.entries); in r600_free_extended_power_table()
1311 kfree(dyn_state->acp_clock_voltage_dependency_table.entries); in r600_free_extended_power_table()