Lines Matching refs:idx
837 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx); in r600_cs_common_vline_parse()
848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); in r600_cs_common_vline_parse()
864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) { in r600_cs_common_vline_parse()
869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) { in r600_cs_common_vline_parse()
875 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); in r600_cs_common_vline_parse()
879 h_idx = p->idx - 2; in r600_cs_common_vline_parse()
880 p->idx += wait_reg_mem.count + 2; in r600_cs_common_vline_parse()
881 p->idx += p3reloc.count + 2; in r600_cs_common_vline_parse()
918 unsigned idx, unsigned reg) in r600_packet0_check() argument
927 idx, reg); in r600_packet0_check()
932 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); in r600_packet0_check()
942 unsigned idx; in r600_cs_parse_packet0() local
945 idx = pkt->idx + 1; in r600_cs_parse_packet0()
947 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { in r600_cs_parse_packet0()
948 r = r600_packet0_check(p, pkt, idx, reg); in r600_cs_parse_packet0()
966 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in r600_cs_check_reg() argument
975 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_cs_check_reg()
1020 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1023 track->sq_config = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1026 track->db_depth_control = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1038 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1039 ib[idx] &= C_028010_ARRAY_MODE; in r600_cs_check_reg()
1042 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1045 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1049 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1054 track->db_depth_view = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1058 track->db_depth_size = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1059 track->db_depth_size_idx = idx; in r600_cs_check_reg()
1063 track->vgt_strmout_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1067 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1081 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1082 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1093 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in r600_cs_check_reg()
1103 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1106 track->cb_target_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1110 track->cb_shader_mask = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1113 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); in r600_cs_check_reg()
1119 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx)); in r600_cs_check_reg()
1139 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1141 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1144 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1149 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1162 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1174 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1175 track->cb_color_size_idx[tmp] = idx; in r600_cs_check_reg()
1203 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1211 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1212 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1234 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1242 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1243 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1258 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1278 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1279 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1280 track->cb_color_base_last[tmp] = ib[idx]; in r600_cs_check_reg()
1292 track->db_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1293 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1305 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1306 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1311 track->htile_surface = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1313 ib[idx] |= 3; in r600_cs_check_reg()
1375 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1384 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1387 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in r600_cs_check_reg()
1390 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_cs_check_reg()
1469 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, in r600_check_texture_resource() argument
1494 word0 = radeon_get_ib_value(p, idx + 0); in r600_check_texture_resource()
1501 word1 = radeon_get_ib_value(p, idx + 1); in r600_check_texture_resource()
1502 word2 = radeon_get_ib_value(p, idx + 2) << 8; in r600_check_texture_resource()
1503 word3 = radeon_get_ib_value(p, idx + 3) << 8; in r600_check_texture_resource()
1504 word4 = radeon_get_ib_value(p, idx + 4); in r600_check_texture_resource()
1505 word5 = radeon_get_ib_value(p, idx + 5); in r600_check_texture_resource()
1610 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in r600_is_safe_reg() argument
1616 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_is_safe_reg()
1622 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_is_safe_reg()
1632 unsigned idx; in r600_packet3_check() local
1640 idx = pkt->idx + 1; in r600_packet3_check()
1641 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()
1655 tmp = radeon_get_ib_value(p, idx + 1); in r600_packet3_check()
1677 ib[idx + 0] = offset; in r600_packet3_check()
1678 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1716 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in r600_packet3_check()
1718 ib[idx+0] = offset; in r600_packet3_check()
1719 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1735 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in r600_packet3_check()
1767 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) + in r600_packet3_check()
1768 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1770 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); in r600_packet3_check()
1771 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1785 command = radeon_get_ib_value(p, idx+4); in r600_packet3_check()
1803 tmp = radeon_get_ib_value(p, idx) + in r600_packet3_check()
1804 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in r600_packet3_check()
1814 ib[idx] = offset; in r600_packet3_check()
1815 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1833 tmp = radeon_get_ib_value(p, idx+2) + in r600_packet3_check()
1834 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in r600_packet3_check()
1844 ib[idx+2] = offset; in r600_packet3_check()
1845 ib[idx+3] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1855 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in r600_packet3_check()
1856 radeon_get_ib_value(p, idx + 2) != 0) { in r600_packet3_check()
1862 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1879 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in r600_packet3_check()
1880 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1882 ib[idx+1] = offset & 0xfffffff8; in r600_packet3_check()
1883 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1901 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in r600_packet3_check()
1902 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in r600_packet3_check()
1904 ib[idx+1] = offset & 0xfffffffc; in r600_packet3_check()
1905 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1919 r = r600_cs_check_reg(p, reg, idx+1+i); in r600_packet3_check()
1935 r = r600_cs_check_reg(p, reg, idx+1+i); in r600_packet3_check()
1957 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { in r600_packet3_check()
1968 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); in r600_packet3_check()
1970 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); in r600_packet3_check()
1981 r = r600_check_texture_resource(p, idx+(i*7)+1, in r600_packet3_check()
1983 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2), in r600_packet3_check()
1984 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3), in r600_packet3_check()
1988 ib[idx+1+(i*7)+2] += base_offset; in r600_packet3_check()
1989 ib[idx+1+(i*7)+3] += mip_offset; in r600_packet3_check()
2000 offset = radeon_get_ib_value(p, idx+1+(i*7)+0); in r600_packet3_check()
2001 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1; in r600_packet3_check()
2006 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; in r600_packet3_check()
2010 ib[idx+1+(i*8)+0] = offset64; in r600_packet3_check()
2011 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in r600_packet3_check()
2107 offset = (u64)radeon_get_ib_value(p, idx+1) << 8; in r600_packet3_check()
2119 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2145 offset = radeon_get_ib_value(p, idx+1); in r600_packet3_check()
2146 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_packet3_check()
2153 ib[idx+1] = offset; in r600_packet3_check()
2154 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2164 offset = radeon_get_ib_value(p, idx+3); in r600_packet3_check()
2165 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_packet3_check()
2172 ib[idx+3] = offset; in r600_packet3_check()
2173 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2189 offset = radeon_get_ib_value(p, idx+0); in r600_packet3_check()
2190 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in r600_packet3_check()
2201 ib[idx+0] = offset; in r600_packet3_check()
2202 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2218 offset = radeon_get_ib_value(p, idx+1); in r600_packet3_check()
2219 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_packet3_check()
2226 ib[idx+1] = offset; in r600_packet3_check()
2227 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2230 reg = radeon_get_ib_value(p, idx+1) << 2; in r600_packet3_check()
2231 if (!r600_is_safe_reg(p, reg, idx+1)) in r600_packet3_check()
2242 offset = radeon_get_ib_value(p, idx+3); in r600_packet3_check()
2243 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_packet3_check()
2250 ib[idx+3] = offset; in r600_packet3_check()
2251 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2254 reg = radeon_get_ib_value(p, idx+3) << 2; in r600_packet3_check()
2255 if (!r600_is_safe_reg(p, reg, idx+3)) in r600_packet3_check()
2292 r = radeon_cs_packet_parse(p, &pkt, p->idx); in r600_cs_parse()
2298 p->idx += pkt.count + 2; in r600_cs_parse()
2319 } while (p->idx < p->chunk_ib->length_dw); in r600_cs_parse()
2345 unsigned idx; in r600_dma_cs_next_reloc() local
2352 idx = p->dma_reloc_idx; in r600_dma_cs_next_reloc()
2353 if (idx >= p->nrelocs) { in r600_dma_cs_next_reloc()
2355 idx, p->nrelocs); in r600_dma_cs_next_reloc()
2358 *cs_reloc = &p->relocs[idx]; in r600_dma_cs_next_reloc()
2382 u32 idx, idx_value; in r600_dma_cs_parse() local
2387 if (p->idx >= ib_chunk->length_dw) { in r600_dma_cs_parse()
2389 p->idx, ib_chunk->length_dw); in r600_dma_cs_parse()
2392 idx = p->idx; in r600_dma_cs_parse()
2393 header = radeon_get_ib_value(p, idx); in r600_dma_cs_parse()
2406 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2409 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2410 p->idx += count + 5; in r600_dma_cs_parse()
2412 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2413 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in r600_dma_cs_parse()
2415 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2416 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2417 p->idx += count + 3; in r600_dma_cs_parse()
2437 idx_value = radeon_get_ib_value(p, idx + 2); in r600_dma_cs_parse()
2441 src_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2443 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2445 dst_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2446 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2447 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2448 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2451 src_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2452 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2453 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2454 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2456 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2458 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2460 p->idx += 7; in r600_dma_cs_parse()
2463 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2464 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_dma_cs_parse()
2465 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2466 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2468 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2469 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2470 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2471 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2472 p->idx += 5; in r600_dma_cs_parse()
2474 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2475 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2476 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2477 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16; in r600_dma_cs_parse()
2479 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2480 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2481 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2482 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; in r600_dma_cs_parse()
2483 p->idx += 4; in r600_dma_cs_parse()
2507 dst_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2508 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in r600_dma_cs_parse()
2514 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2515 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in r600_dma_cs_parse()
2516 p->idx += 4; in r600_dma_cs_parse()
2519 p->idx += 1; in r600_dma_cs_parse()
2522 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in r600_dma_cs_parse()
2525 } while (p->idx < p->chunk_ib->length_dw); in r600_dma_cs_parse()