Lines Matching +full:8 +full:dev
47 u32 cb_color_base_last[8];
48 struct radeon_bo *cb_color_bo[8];
49 u64 cb_color_bo_mc[8];
50 u64 cb_color_bo_offset[8];
51 struct radeon_bo *cb_color_frag_bo[8];
52 u64 cb_color_frag_offset[8];
53 struct radeon_bo *cb_color_tile_bo[8];
54 u64 cb_color_tile_offset[8];
55 u32 cb_color_mask[8];
56 u32 cb_color_info[8];
57 u32 cb_color_view[8];
58 u32 cb_color_size_idx[8]; /* unused */
62 u32 cb_color_size[8];
90 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
91 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
104 /* 8 bit */
165 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
168 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
254 u32 tile_width = 8; in r600_get_array_mode_alignment()
255 u32 tile_height = 8; in r600_get_array_mode_alignment()
305 for (i = 0; i < 8; i++) { in r600_cs_track_init()
364 dev_warn_once(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", in r600_cs_track_validate_cb()
370 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8; in r600_cs_track_validate_cb()
387 dev_warn_once(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, in r600_cs_track_validate_cb()
405 dev_warn_once(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, in r600_cs_track_validate_cb()
412 dev_warn_once(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_cb()
417 dev_warn_once(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_cb()
422 dev_warn_once(p->dev, in r600_cs_track_validate_cb()
451 dev_warn_once(p->dev, in r600_cs_track_validate_cb()
466 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | in r600_cs_track_validate_cb()
477 /* the tile size is 8x8, but the size is in units of bits. in r600_cs_track_validate_cb()
478 * for bytes, do just * 8. */ in r600_cs_track_validate_cb()
479 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1); in r600_cs_track_validate_cb()
483 dev_warn_once(p->dev, "%s FMASK_TILE_MAX too large " in r600_cs_track_validate_cb()
495 /* One block = 128x128 pixels, one 8x8 tile has 4 bits.. in r600_cs_track_validate_cb()
496 * (128*128) / (8*8) / 2 = 128 bytes per block. */ in r600_cs_track_validate_cb()
501 dev_warn_once(p->dev, "%s CMASK_BLOCK_MAX too large " in r600_cs_track_validate_cb()
511 dev_warn_once(p->dev, "%s invalid tile mode\n", __func__); in r600_cs_track_validate_cb()
531 dev_warn_once(p->dev, "z/stencil with no depth buffer\n"); in r600_cs_track_validate_db()
546 bpe = 8; in r600_cs_track_validate_db()
549 dev_warn_once(p->dev, in r600_cs_track_validate_db()
556 dev_warn_once(p->dev, "z/stencil buffer size not set\n"); in r600_cs_track_validate_db()
562 dev_warn_once(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", in r600_cs_track_validate_db()
570 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8; in r600_cs_track_validate_db()
586 dev_warn_once(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, in r600_cs_track_validate_db()
599 dev_warn_once(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, in r600_cs_track_validate_db()
606 dev_warn_once(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_db()
611 dev_warn_once(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", in r600_cs_track_validate_db()
616 dev_warn_once(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__, in r600_cs_track_validate_db()
625 dev_warn_once(p->dev, in r600_cs_track_validate_db()
640 dev_warn_once(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", in r600_cs_track_validate_db()
645 dev_warn_once(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n", in r600_cs_track_validate_db()
653 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */ in r600_cs_track_validate_db()
654 nbx = round_up(nbx, 16 * 8); in r600_cs_track_validate_db()
655 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */ in r600_cs_track_validate_db()
656 nby = round_up(nby, track->npipes * 8); in r600_cs_track_validate_db()
658 /* always assume 8x8 htile */ in r600_cs_track_validate_db()
659 /* align is htile align * 8, htile align vary according to in r600_cs_track_validate_db()
663 case 8: in r600_cs_track_validate_db()
664 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ in r600_cs_track_validate_db()
665 nbx = round_up(nbx, 64 * 8); in r600_cs_track_validate_db()
666 nby = round_up(nby, 64 * 8); in r600_cs_track_validate_db()
669 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ in r600_cs_track_validate_db()
670 nbx = round_up(nbx, 64 * 8); in r600_cs_track_validate_db()
671 nby = round_up(nby, 32 * 8); in r600_cs_track_validate_db()
674 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ in r600_cs_track_validate_db()
675 nbx = round_up(nbx, 32 * 8); in r600_cs_track_validate_db()
676 nby = round_up(nby, 32 * 8); in r600_cs_track_validate_db()
679 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ in r600_cs_track_validate_db()
680 nbx = round_up(nbx, 32 * 8); in r600_cs_track_validate_db()
681 nby = round_up(nby, 16 * 8); in r600_cs_track_validate_db()
684 dev_warn_once(p->dev, "%s:%d invalid num pipes %d\n", in r600_cs_track_validate_db()
697 dev_warn_once(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", in r600_cs_track_validate_db()
726 dev_warn_once(p->dev, "streamout %d bo too small: 0x%llx, 0x%lx\n", in r600_cs_track_check()
732 dev_warn_once(p->dev, "No buffer for streamout %d\n", i); in r600_cs_track_check()
754 for (i = 0; i < 8; i++) { in r600_cs_track_check()
761 dev_warn_once(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", in r600_cs_track_check()
849 dev_warn_once(p->dev, "vline wait missing WAIT_REG_MEM segment\n"); in r600_cs_common_vline_parse()
856 dev_warn_once(p->dev, "vline WAIT_REG_MEM waiting on MEM instead of REG\n"); in r600_cs_common_vline_parse()
859 /* bit 8 is me (0) or pfp (1) */ in r600_cs_common_vline_parse()
861 dev_warn_once(p->dev, "vline WAIT_REG_MEM waiting on PFP instead of ME\n"); in r600_cs_common_vline_parse()
866 dev_warn_once(p->dev, "vline WAIT_REG_MEM function not equal\n"); in r600_cs_common_vline_parse()
870 dev_warn_once(p->dev, "vline WAIT_REG_MEM bad reg\n"); in r600_cs_common_vline_parse()
875 dev_warn_once(p->dev, "vline WAIT_REG_MEM bad bit mask\n"); in r600_cs_common_vline_parse()
894 dev_warn_once(p->dev, "cannot find crtc %d\n", crtc_id); in r600_cs_common_vline_parse()
908 ib[h_idx + 8] = PACKET2(0); in r600_cs_common_vline_parse()
915 dev_warn_once(p->dev, "unknown crtc reloc\n"); in r600_cs_common_vline_parse()
931 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", in r600_packet0_check()
980 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_cs_check_reg()
1021 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1025 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1039 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1081 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1086 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1087 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1104 dev_warn_once(p->dev, "missing reloc for CP_COHER_BASE " in r600_cs_check_reg()
1108 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1140 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in r600_cs_check_reg()
1203 …dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n… in r600_cs_check_reg()
1212 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in r600_cs_check_reg()
1216 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1217 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1234 …dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n… in r600_cs_check_reg()
1243 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in r600_cs_check_reg()
1247 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1248 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1278 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1283 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1284 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1293 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1297 track->db_offset = radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1298 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1306 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1310 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8; in r600_cs_check_reg()
1311 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1317 /* force 8x8 htile width and height */ in r600_cs_check_reg()
1376 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in r600_cs_check_reg()
1380 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1385 dev_warn_once(p->dev, "bad SET_CONFIG_REG " in r600_cs_check_reg()
1389 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1395 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_cs_check_reg()
1496 base_offset <<= 8; in r600_check_texture_resource()
1497 mip_offset <<= 8; in r600_check_texture_resource()
1507 word2 = radeon_get_ib_value(p, idx + 2) << 8; in r600_check_texture_resource()
1508 word3 = radeon_get_ib_value(p, idx + 3) << 8; in r600_check_texture_resource()
1513 pitch = (G_038000_PITCH(word0) + 1) * 8; in r600_check_texture_resource()
1535 nfaces = 8; in r600_check_texture_resource()
1551 dev_warn_once(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); in r600_check_texture_resource()
1555 dev_warn_once(p->dev, "%s:%d texture invalid format %d\n", in r600_check_texture_resource()
1562 dev_warn_once(p->dev, "%s:%d tex array mode (%d) invalid\n", in r600_check_texture_resource()
1570 dev_warn_once(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", in r600_check_texture_resource()
1575 dev_warn_once(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", in r600_check_texture_resource()
1580 dev_warn_once(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", in r600_check_texture_resource()
1586 dev_warn_once(p->dev, "texture blevel %d > llevel %d\n", in r600_check_texture_resource()
1600 dev_warn_once(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n", in r600_check_texture_resource()
1604 dev_warn_once(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); in r600_check_texture_resource()
1609 /*dev_warn_once(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", in r600_check_texture_resource()
1621 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_is_safe_reg()
1627 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in r600_is_safe_reg()
1656 dev_warn_once(p->dev, "bad SET PREDICATION\n"); in r600_packet3_check()
1668 dev_warn_once(p->dev, "bad SET PREDICATION operation %d\n", pred_op); in r600_packet3_check()
1674 dev_warn_once(p->dev, "bad SET PREDICATION\n"); in r600_packet3_check()
1689 dev_warn_once(p->dev, "bad START_3D\n"); in r600_packet3_check()
1695 dev_warn_once(p->dev, "bad CONTEXT_CONTROL\n"); in r600_packet3_check()
1702 dev_warn_once(p->dev, "bad INDEX_TYPE/NUM_INSTANCES\n"); in r600_packet3_check()
1710 dev_warn_once(p->dev, "bad DRAW_INDEX\n"); in r600_packet3_check()
1715 dev_warn_once(p->dev, "bad DRAW_INDEX\n"); in r600_packet3_check()
1728 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in r600_packet3_check()
1735 dev_warn_once(p->dev, "bad DRAW_INDEX_AUTO\n"); in r600_packet3_check()
1740 dev_warn_once(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in r600_packet3_check()
1747 dev_warn_once(p->dev, "bad DRAW_INDEX_IMMD\n"); in r600_packet3_check()
1752 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in r600_packet3_check()
1758 dev_warn_once(p->dev, "bad WAIT_REG_MEM\n"); in r600_packet3_check()
1767 dev_warn_once(p->dev, "bad WAIT_REG_MEM\n"); in r600_packet3_check()
1778 dev_warn_once(p->dev, "cannot use PFP on REG wait\n"); in r600_packet3_check()
1787 dev_warn_once(p->dev, "bad CP DMA\n"); in r600_packet3_check()
1794 dev_warn_once(p->dev, "CP DMA SAS not supported\n"); in r600_packet3_check()
1798 dev_warn_once(p->dev, "CP DMA SAIC only supported for registers\n"); in r600_packet3_check()
1804 dev_warn_once(p->dev, "bad CP DMA SRC\n"); in r600_packet3_check()
1814 dev_warn_once(p->dev, "CP DMA src buffer too small (%llu %lu)\n", in r600_packet3_check()
1824 dev_warn_once(p->dev, "CP DMA DAS not supported\n"); in r600_packet3_check()
1829 dev_warn_once(p->dev, "CP DMA DAIC only supported for registers\n"); in r600_packet3_check()
1834 dev_warn_once(p->dev, "bad CP DMA DST\n"); in r600_packet3_check()
1844 dev_warn_once(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", in r600_packet3_check()
1856 dev_warn_once(p->dev, "bad SURFACE_SYNC\n"); in r600_packet3_check()
1864 dev_warn_once(p->dev, "bad SURFACE_SYNC\n"); in r600_packet3_check()
1867 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1872 dev_warn_once(p->dev, "bad EVENT_WRITE\n"); in r600_packet3_check()
1880 dev_warn_once(p->dev, "bad EVENT_WRITE\n"); in r600_packet3_check()
1896 dev_warn_once(p->dev, "bad EVENT_WRITE_EOP\n"); in r600_packet3_check()
1901 dev_warn_once(p->dev, "bad EVENT_WRITE\n"); in r600_packet3_check()
1919 dev_warn_once(p->dev, "bad PACKET3_SET_CONFIG_REG\n"); in r600_packet3_check()
1935 dev_warn_once(p->dev, "bad PACKET3_SET_CONTEXT_REG\n"); in r600_packet3_check()
1947 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in r600_packet3_check()
1955 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in r600_packet3_check()
1967 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in r600_packet3_check()
1970 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1981 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in r600_packet3_check()
1984 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2002 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in r600_packet3_check()
2009 dev_warn_once(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", in r600_packet3_check()
2015 ib[idx+1+(i*8)+0] = offset64; in r600_packet3_check()
2016 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in r600_packet3_check()
2023 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in r600_packet3_check()
2035 dev_warn_once(p->dev, "bad SET_ALU_CONST\n"); in r600_packet3_check()
2046 dev_warn_once(p->dev, "bad SET_BOOL_CONST\n"); in r600_packet3_check()
2056 dev_warn_once(p->dev, "bad SET_LOOP_CONST\n"); in r600_packet3_check()
2066 dev_warn_once(p->dev, "bad SET_CTL_CONST\n"); in r600_packet3_check()
2072 dev_warn_once(p->dev, "bad SET_SAMPLER\n"); in r600_packet3_check()
2080 dev_warn_once(p->dev, "bad SET_SAMPLER\n"); in r600_packet3_check()
2087 dev_warn_once(p->dev, "STRMOUT_BASE_UPDATE only supported on 7xx\n"); in r600_packet3_check()
2091 dev_warn_once(p->dev, "bad STRMOUT_BASE_UPDATE packet count\n"); in r600_packet3_check()
2095 dev_warn_once(p->dev, "bad STRMOUT_BASE_UPDATE index\n"); in r600_packet3_check()
2103 dev_warn_once(p->dev, "bad STRMOUT_BASE_UPDATE reloc\n"); in r600_packet3_check()
2108 dev_warn_once(p->dev, "bad STRMOUT_BASE_UPDATE, bo does not match\n"); in r600_packet3_check()
2112 offset = (u64)radeon_get_ib_value(p, idx+1) << 8; in r600_packet3_check()
2114 dev_warn_once(p->dev, in r600_packet3_check()
2121 dev_warn_once(p->dev, in r600_packet3_check()
2126 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2131 dev_warn_once(p->dev, "bad SURFACE_BASE_UPDATE\n"); in r600_packet3_check()
2135 dev_warn_once(p->dev, "bad SURFACE_BASE_UPDATE\n"); in r600_packet3_check()
2141 dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); in r600_packet3_check()
2149 dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); in r600_packet3_check()
2155 dev_warn_once(p->dev, in r600_packet3_check()
2169 dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); in r600_packet3_check()
2175 dev_warn_once(p->dev, in r600_packet3_check()
2190 dev_warn_once(p->dev, "bad MEM_WRITE (invalid count)\n"); in r600_packet3_check()
2195 dev_warn_once(p->dev, "bad MEM_WRITE (missing reloc)\n"); in r600_packet3_check()
2201 dev_warn_once(p->dev, "bad MEM_WRITE (address not qwords aligned)\n"); in r600_packet3_check()
2204 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in r600_packet3_check()
2205 dev_warn_once(p->dev, "bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n", in r600_packet3_check()
2206 offset + 8, radeon_bo_size(reloc->robj)); in r600_packet3_check()
2216 dev_warn_once(p->dev, "bad COPY_DW (invalid count)\n"); in r600_packet3_check()
2224 dev_warn_once(p->dev, "bad COPY_DW (missing src reloc)\n"); in r600_packet3_check()
2230 dev_warn_once(p->dev, "bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", in r600_packet3_check()
2248 dev_warn_once(p->dev, "bad COPY_DW (missing dst reloc)\n"); in r600_packet3_check()
2254 dev_warn_once(p->dev, "bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", in r600_packet3_check()
2271 dev_warn_once(p->dev, "Packet3 opcode %x not supported\n", pkt->opcode); in r600_packet3_check()
2318 dev_warn_once(p->dev, "Unknown packet type %d !\n", pkt.type); in r600_cs_parse()
2358 dev_warn_once(p->dev, "No relocation chunk !\n"); in r600_dma_cs_next_reloc()
2363 dev_warn_once(p->dev, "Relocs at %d after relocations chunk end %d !\n", in r600_dma_cs_next_reloc()
2397 dev_warn_once(p->dev, "Can not parse packet at %d after CS end %d !\n", in r600_dma_cs_parse()
2411 dev_warn_once(p->dev, "bad DMA_PACKET_WRITE\n"); in r600_dma_cs_parse()
2416 dst_offset <<= 8; in r600_dma_cs_parse()
2418 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2429 dev_warn_once(p->dev, "DMA write buffer too small (%llu %lu)\n", in r600_dma_cs_parse()
2437 dev_warn_once(p->dev, "bad DMA_PACKET_COPY\n"); in r600_dma_cs_parse()
2442 dev_warn_once(p->dev, "bad DMA_PACKET_COPY\n"); in r600_dma_cs_parse()
2451 src_offset <<= 8; in r600_dma_cs_parse()
2452 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2466 dst_offset <<= 8; in r600_dma_cs_parse()
2467 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2496 dev_warn_once(p->dev, "DMA copy src buffer too small (%llu %lu)\n", in r600_dma_cs_parse()
2501 dev_warn_once(p->dev, "DMA write dst buffer too small (%llu %lu)\n", in r600_dma_cs_parse()
2508 dev_warn_once(p->dev, "Constant Fill is 7xx only !\n"); in r600_dma_cs_parse()
2513 dev_warn_once(p->dev, "bad DMA_PACKET_WRITE\n"); in r600_dma_cs_parse()
2519 dev_warn_once(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", in r600_dma_cs_parse()
2531 dev_warn_once(p->dev, "Unknown packet type %d at %d !\n", cmd, idx); in r600_dma_cs_parse()