Lines Matching +full:dac +full:- +full:current +full:- +full:limit +full:- +full:low
105 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
125 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); in r600_rcu_rreg()
128 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); in r600_rcu_rreg()
136 spin_lock_irqsave(&rdev->rcu_idx_lock, flags); in r600_rcu_wreg()
139 spin_unlock_irqrestore(&rdev->rcu_idx_lock, flags); in r600_rcu_wreg()
147 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_rreg()
150 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_rreg()
158 spin_lock_irqsave(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_wreg()
161 spin_unlock_irqrestore(&rdev->uvd_idx_lock, flags); in r600_uvd_ctx_wreg()
165 * r600_get_allowed_info_register - fetch the register for the info ioctl
171 * Returns 0 for success or -EINVAL for an invalid register
186 return -EINVAL; in r600_get_allowed_info_register()
191 * r600_get_xclk - get the xclk
200 return rdev->clock.spll.reference_freq; in r600_get_xclk()
217 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
227 if (rdev->clock.spll.reference_freq == 10000) in r600_set_uvd_clocks()
238 if (rdev->family >= CHIP_RV670 && rdev->family < CHIP_RS780) in r600_set_uvd_clocks()
251 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
279 if (rdev->family >= CHIP_RS780) in r600_set_uvd_clocks()
298 struct drm_device *dev = encoder->dev; in dce3_program_fmt()
299 struct radeon_device *rdev = dev->dev_private; in dce3_program_fmt()
301 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); in dce3_program_fmt()
310 dither = radeon_connector->dither; in dce3_program_fmt()
314 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) in dce3_program_fmt()
318 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || in dce3_program_fmt()
319 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) in dce3_program_fmt()
346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
357 actual_temp -= 256; in rv6xx_get_temp()
366 rdev->pm.dynpm_can_upclock = true; in r600_pm_get_dynpm_state()
367 rdev->pm.dynpm_can_downclock = true; in r600_pm_get_dynpm_state()
369 /* power state array is low to high, default is first */ in r600_pm_get_dynpm_state()
370 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) { in r600_pm_get_dynpm_state()
373 if (rdev->pm.num_power_states > 2) in r600_pm_get_dynpm_state()
376 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
378 rdev->pm.requested_power_state_index = min_power_state_index; in r600_pm_get_dynpm_state()
379 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
380 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
383 if (rdev->pm.current_power_state_index == min_power_state_index) { in r600_pm_get_dynpm_state()
384 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
385 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
387 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
388 for (i = 0; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
389 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
391 else if (i >= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
392 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
393 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
396 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
401 if (rdev->pm.current_power_state_index == 0) in r600_pm_get_dynpm_state()
402 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
403 rdev->pm.num_power_states - 1; in r600_pm_get_dynpm_state()
405 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
406 rdev->pm.current_power_state_index - 1; in r600_pm_get_dynpm_state()
409 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
411 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
412 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
413 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
415 rdev->pm.requested_power_state_index++; in r600_pm_get_dynpm_state()
419 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) { in r600_pm_get_dynpm_state()
420 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
421 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
423 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
424 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) { in r600_pm_get_dynpm_state()
425 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
427 else if (i <= rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
428 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
429 rdev->pm.current_power_state_index; in r600_pm_get_dynpm_state()
432 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
437 rdev->pm.requested_power_state_index = in r600_pm_get_dynpm_state()
438 rdev->pm.current_power_state_index + 1; in r600_pm_get_dynpm_state()
440 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
443 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
444 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
445 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
455 /* power state array is low to high, default is first (0) */ in r600_pm_get_dynpm_state()
456 if (rdev->pm.active_crtc_count > 1) { in r600_pm_get_dynpm_state()
457 rdev->pm.requested_power_state_index = -1; in r600_pm_get_dynpm_state()
459 for (i = 1; i < rdev->pm.num_power_states; i++) { in r600_pm_get_dynpm_state()
460 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) in r600_pm_get_dynpm_state()
462 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) || in r600_pm_get_dynpm_state()
463 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) { in r600_pm_get_dynpm_state()
464 rdev->pm.requested_power_state_index = i; in r600_pm_get_dynpm_state()
469 if (rdev->pm.requested_power_state_index == -1) in r600_pm_get_dynpm_state()
470 rdev->pm.requested_power_state_index = 0; in r600_pm_get_dynpm_state()
472 rdev->pm.requested_power_state_index = 1; in r600_pm_get_dynpm_state()
474 switch (rdev->pm.dynpm_planned_action) { in r600_pm_get_dynpm_state()
476 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
477 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
480 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
481 if (rdev->pm.current_clock_mode_index == 0) { in r600_pm_get_dynpm_state()
482 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
483 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
485 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
486 rdev->pm.current_clock_mode_index - 1; in r600_pm_get_dynpm_state()
488 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
489 rdev->pm.dynpm_can_downclock = false; in r600_pm_get_dynpm_state()
492 if ((rdev->pm.active_crtc_count > 0) && in r600_pm_get_dynpm_state()
493 (rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
494 clock_info[rdev->pm.requested_clock_mode_index].flags & in r600_pm_get_dynpm_state()
496 rdev->pm.requested_clock_mode_index++; in r600_pm_get_dynpm_state()
500 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) { in r600_pm_get_dynpm_state()
501 if (rdev->pm.current_clock_mode_index == in r600_pm_get_dynpm_state()
502 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) { in r600_pm_get_dynpm_state()
503 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index; in r600_pm_get_dynpm_state()
504 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
506 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
507 rdev->pm.current_clock_mode_index + 1; in r600_pm_get_dynpm_state()
509 rdev->pm.requested_clock_mode_index = in r600_pm_get_dynpm_state()
510 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1; in r600_pm_get_dynpm_state()
511 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
515 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index; in r600_pm_get_dynpm_state()
516 rdev->pm.requested_clock_mode_index = 0; in r600_pm_get_dynpm_state()
517 rdev->pm.dynpm_can_upclock = false; in r600_pm_get_dynpm_state()
527 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
528 clock_info[rdev->pm.requested_clock_mode_index].sclk, in r600_pm_get_dynpm_state()
529 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
530 clock_info[rdev->pm.requested_clock_mode_index].mclk, in r600_pm_get_dynpm_state()
531 rdev->pm.power_state[rdev->pm.requested_power_state_index]. in r600_pm_get_dynpm_state()
537 if (rdev->pm.num_power_states == 2) { in rs780_pm_init_profile()
539 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
540 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
541 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
542 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
543 /* low sh */ in rs780_pm_init_profile()
544 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
545 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
546 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
547 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
549 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
550 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
551 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
552 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
554 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
555 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
556 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
557 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
558 /* low mh */ in rs780_pm_init_profile()
559 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
560 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
561 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
562 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
566 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
569 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in rs780_pm_init_profile()
570 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
571 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
572 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
573 } else if (rdev->pm.num_power_states == 3) { in rs780_pm_init_profile()
575 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
576 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
577 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
578 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
579 /* low sh */ in rs780_pm_init_profile()
580 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
585 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
590 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
594 /* low mh */ in rs780_pm_init_profile()
595 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
600 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1; in rs780_pm_init_profile()
602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
605 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1; in rs780_pm_init_profile()
606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
611 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
612 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in rs780_pm_init_profile()
613 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
614 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
615 /* low sh */ in rs780_pm_init_profile()
616 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
617 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
618 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
619 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
621 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
622 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2; in rs780_pm_init_profile()
623 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
624 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
626 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
627 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
628 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
629 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
630 /* low mh */ in rs780_pm_init_profile()
631 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
632 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
633 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
634 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
636 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
637 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0; in rs780_pm_init_profile()
638 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
639 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
641 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in rs780_pm_init_profile()
642 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3; in rs780_pm_init_profile()
643 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in rs780_pm_init_profile()
644 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in rs780_pm_init_profile()
652 if (rdev->family == CHIP_R600) { in r600_pm_init_profile()
655 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
656 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
657 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
658 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
659 /* low sh */ in r600_pm_init_profile()
660 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
661 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
662 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
663 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
665 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
666 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
667 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
668 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
670 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
671 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
672 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
673 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
674 /* low mh */ in r600_pm_init_profile()
675 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
676 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
677 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
678 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
680 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
681 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
682 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
683 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
685 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
686 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
687 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
688 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
690 if (rdev->pm.num_power_states < 4) { in r600_pm_init_profile()
692 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
693 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
694 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
695 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
696 /* low sh */ in r600_pm_init_profile()
697 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
698 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
699 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
700 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
702 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
703 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
704 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
705 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
707 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1; in r600_pm_init_profile()
708 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1; in r600_pm_init_profile()
709 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
710 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
711 /* low mh */ in r600_pm_init_profile()
712 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
713 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
714 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
715 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
716 /* low mh */ in r600_pm_init_profile()
717 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
718 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
719 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
720 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
722 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2; in r600_pm_init_profile()
723 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2; in r600_pm_init_profile()
724 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
725 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
728 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
729 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r600_pm_init_profile()
730 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
731 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
732 /* low sh */ in r600_pm_init_profile()
733 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
737 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
738 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
739 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
740 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
742 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
743 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
744 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
745 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
748 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
749 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
750 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
751 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
752 /* low mh */ in r600_pm_init_profile()
753 if (rdev->flags & RADEON_IS_MOBILITY) in r600_pm_init_profile()
757 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
758 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
759 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
760 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r600_pm_init_profile()
762 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
763 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
764 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
765 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in r600_pm_init_profile()
768 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in r600_pm_init_profile()
769 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in r600_pm_init_profile()
770 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r600_pm_init_profile()
771 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in r600_pm_init_profile()
778 int req_ps_idx = rdev->pm.requested_power_state_index; in r600_pm_misc()
779 int req_cm_idx = rdev->pm.requested_clock_mode_index; in r600_pm_misc()
780 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in r600_pm_misc()
781 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage; in r600_pm_misc()
783 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) { in r600_pm_misc()
785 if (voltage->voltage == 0xff01) in r600_pm_misc()
787 if (voltage->voltage != rdev->pm.current_vddc) { in r600_pm_misc()
788 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in r600_pm_misc()
789 rdev->pm.current_vddc = voltage->voltage; in r600_pm_misc()
790 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage); in r600_pm_misc()
957 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r600_hpd_init()
960 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || in r600_hpd_init()
961 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { in r600_hpd_init()
973 switch (radeon_connector->hpd.hpd) { in r600_hpd_init()
997 switch (radeon_connector->hpd.hpd) { in r600_hpd_init()
1011 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in r600_hpd_init()
1012 enable |= 1 << radeon_connector->hpd.hpd; in r600_hpd_init()
1013 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in r600_hpd_init()
1024 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { in r600_hpd_fini()
1027 switch (radeon_connector->hpd.hpd) { in r600_hpd_fini()
1051 switch (radeon_connector->hpd.hpd) { in r600_hpd_fini()
1065 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) in r600_hpd_fini()
1066 disable |= 1 << radeon_connector->hpd.hpd; in r600_hpd_fini()
1080 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_pcie_gart_tlb_flush()
1081 !(rdev->flags & RADEON_IS_AGP)) { in r600_pcie_gart_tlb_flush()
1082 void __iomem *ptr = (void *)rdev->gart.ptr; in r600_pcie_gart_tlb_flush()
1094 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
1095 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
1097 for (i = 0; i < rdev->usec_timeout; i++) { in r600_pcie_gart_tlb_flush()
1116 if (rdev->gart.robj) { in r600_pcie_gart_init()
1124 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in r600_pcie_gart_init()
1133 if (rdev->gart.robj == NULL) { in r600_pcie_gart_enable()
1134 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in r600_pcie_gart_enable()
1135 return -EINVAL; in r600_pcie_gart_enable()
1168 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
1169 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
1170 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
1174 (u32)(rdev->dummy_page.addr >> 12)); in r600_pcie_gart_enable()
1180 (unsigned)(rdev->mc.gtt_size >> 20), in r600_pcie_gart_enable()
1181 (unsigned long long)rdev->gart.table_addr); in r600_pcie_gart_enable()
1182 rdev->gart.ready = true; in r600_pcie_gart_enable()
1267 for (i = 0; i < rdev->usec_timeout; i++) { in r600_mc_wait_for_idle()
1274 return -1; in r600_mc_wait_for_idle()
1282 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs780_mc_rreg()
1286 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs780_mc_rreg()
1294 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs780_mc_wreg()
1299 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs780_mc_wreg()
1320 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1325 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1326 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1329 rdev->mc.vram_start >> 12); in r600_mc_program()
1331 rdev->mc.gtt_end >> 12); in r600_mc_program()
1335 rdev->mc.gtt_start >> 12); in r600_mc_program()
1337 rdev->mc.vram_end >> 12); in r600_mc_program()
1340 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1341 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1343 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1344 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1345 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1347 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1350 if (rdev->flags & RADEON_IS_AGP) { in r600_mc_program()
1351 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1352 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1353 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1360 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_mc_program()
1369 * r600_vram_gtt_location - try to find VRAM & GTT location
1378 * aperture then we limit the VRAM size to the aperture.
1393 if (mc->mc_vram_size > 0xE0000000) { in r600_vram_gtt_location()
1395 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1396 mc->real_vram_size = 0xE0000000; in r600_vram_gtt_location()
1397 mc->mc_vram_size = 0xE0000000; in r600_vram_gtt_location()
1399 if (rdev->flags & RADEON_IS_AGP) { in r600_vram_gtt_location()
1400 size_bf = mc->gtt_start; in r600_vram_gtt_location()
1401 size_af = mc->mc_mask - mc->gtt_end; in r600_vram_gtt_location()
1403 if (mc->mc_vram_size > size_bf) { in r600_vram_gtt_location()
1404 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1405 mc->real_vram_size = size_bf; in r600_vram_gtt_location()
1406 mc->mc_vram_size = size_bf; in r600_vram_gtt_location()
1408 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r600_vram_gtt_location()
1410 if (mc->mc_vram_size > size_af) { in r600_vram_gtt_location()
1411 dev_warn(rdev->dev, "limiting VRAM\n"); in r600_vram_gtt_location()
1412 mc->real_vram_size = size_af; in r600_vram_gtt_location()
1413 mc->mc_vram_size = size_af; in r600_vram_gtt_location()
1415 mc->vram_start = mc->gtt_end + 1; in r600_vram_gtt_location()
1417 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r600_vram_gtt_location()
1418 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", in r600_vram_gtt_location()
1419 mc->mc_vram_size >> 20, mc->vram_start, in r600_vram_gtt_location()
1420 mc->vram_end, mc->real_vram_size >> 20); in r600_vram_gtt_location()
1423 if (rdev->flags & RADEON_IS_IGP) { in r600_vram_gtt_location()
1427 radeon_vram_location(rdev, &rdev->mc, base); in r600_vram_gtt_location()
1428 rdev->mc.gtt_base_align = 0; in r600_vram_gtt_location()
1441 rdev->mc.vram_is_ddr = true; in r600_mc_init()
1466 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
1468 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r600_mc_init()
1469 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r600_mc_init()
1471 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1472 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1473 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1474 r600_vram_gtt_location(rdev, &rdev->mc); in r600_mc_init()
1476 if (rdev->flags & RADEON_IS_IGP) { in r600_mc_init()
1478 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in r600_mc_init()
1480 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { in r600_mc_init()
1482 rdev->fastfb_working = false; in r600_mc_init()
1487 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) in r600_mc_init()
1493 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { in r600_mc_init()
1495 (unsigned long long)rdev->mc.aper_base, k8_addr); in r600_mc_init()
1496 rdev->mc.aper_base = (resource_size_t)k8_addr; in r600_mc_init()
1497 rdev->fastfb_working = true; in r600_mc_init()
1511 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_init()
1514 0, NULL, NULL, &rdev->vram_scratch.robj); in r600_vram_scratch_init()
1520 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_init()
1523 r = radeon_bo_pin(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1524 RADEON_GEM_DOMAIN_VRAM, &rdev->vram_scratch.gpu_addr); in r600_vram_scratch_init()
1526 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1529 r = radeon_bo_kmap(rdev->vram_scratch.robj, in r600_vram_scratch_init()
1530 (void **)&rdev->vram_scratch.ptr); in r600_vram_scratch_init()
1532 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1533 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_init()
1542 if (rdev->vram_scratch.robj == NULL) { in r600_vram_scratch_fini()
1545 r = radeon_bo_reserve(rdev->vram_scratch.robj, false); in r600_vram_scratch_fini()
1547 radeon_bo_kunmap(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1548 radeon_bo_unpin(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1549 radeon_bo_unreserve(rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1551 radeon_bo_unref(&rdev->vram_scratch.robj); in r600_vram_scratch_fini()
1568 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", in r600_print_gpu_status_regs()
1570 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", in r600_print_gpu_status_regs()
1572 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", in r600_print_gpu_status_regs()
1574 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", in r600_print_gpu_status_regs()
1576 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", in r600_print_gpu_status_regs()
1578 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", in r600_print_gpu_status_regs()
1580 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", in r600_print_gpu_status_regs()
1582 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", in r600_print_gpu_status_regs()
1592 for (i = 0; i < rdev->num_crtc; i++) { in r600_is_display_hung()
1600 for (i = 0; i < rdev->num_crtc; i++) { in r600_is_display_hung()
1622 if (rdev->family >= CHIP_RV770) { in r600_gpu_check_soft_reset()
1693 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in r600_gpu_soft_reset()
1698 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1717 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_soft_reset()
1721 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1757 if (rdev->family >= CHIP_RV770) in r600_gpu_soft_reset()
1775 if (!(rdev->flags & RADEON_IS_IGP)) { in r600_gpu_soft_reset()
1786 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1800 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1825 dev_info(rdev->dev, "GPU pci config reset\n"); in r600_gpu_pci_config_reset()
1830 if (rdev->family >= CHIP_RV770) in r600_gpu_pci_config_reset()
1846 if (rdev->family >= CHIP_RV770) in r600_gpu_pci_config_reset()
1849 pci_clear_master(rdev->pdev); in r600_gpu_pci_config_reset()
1853 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in r600_gpu_pci_config_reset()
1874 for (i = 0; i < rdev->usec_timeout; i++) { in r600_gpu_pci_config_reset()
1913 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1942 u32 data = 0, mask = 1 << (max_rb_num - 1); in r6xx_remap_render_backend()
1952 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); in r6xx_remap_render_backend()
1956 pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num; in r6xx_remap_render_backend()
1958 if (rdev->family <= CHIP_RV740) { in r6xx_remap_render_backend()
1970 data |= max_rb_num - i - 1; in r6xx_remap_render_backend()
1974 data |= max_rb_num - i - 1; in r6xx_remap_render_backend()
1975 pipe_rb_remain--; in r6xx_remap_render_backend()
2004 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
2005 switch (rdev->family) { in r600_gpu_init()
2007 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
2008 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
2009 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2010 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2011 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
2012 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2013 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2014 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2015 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2016 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2017 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2018 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2019 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2023 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
2024 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
2025 rdev->config.r600.max_simds = 3; in r600_gpu_init()
2026 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2027 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2028 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2029 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2030 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2031 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2032 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2033 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2034 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2035 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2041 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
2042 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
2043 rdev->config.r600.max_simds = 2; in r600_gpu_init()
2044 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2045 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2046 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2047 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2048 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
2049 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2050 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2051 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2052 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2053 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
2056 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
2057 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
2058 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2059 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2060 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
2061 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2062 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2063 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2064 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2065 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2066 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2067 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2068 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2088 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
2104 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
2105 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
2120 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2122 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2126 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2130 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2134 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2137 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2139 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
2145 …tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >>… in r600_gpu_init()
2147 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); in r600_gpu_init()
2156 if (rdev->family == CHIP_RV670) in r600_gpu_init()
2161 if ((rdev->family > CHIP_R600)) in r600_gpu_init()
2165 if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
2166 ((rdev->family) == CHIP_RV630) || in r600_gpu_init()
2167 ((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2168 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2169 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2170 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2185 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2186 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2187 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2188 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2193 } else if (((rdev->family) == CHIP_R600) || in r600_gpu_init()
2194 ((rdev->family) == CHIP_RV630)) { in r600_gpu_init()
2215 if ((rdev->family) == CHIP_R600) { in r600_gpu_init()
2229 } else if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2230 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2231 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2232 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2249 } else if (((rdev->family) == CHIP_RV630) || in r600_gpu_init()
2250 ((rdev->family) == CHIP_RV635)) { in r600_gpu_init()
2264 } else if ((rdev->family) == CHIP_RV670) { in r600_gpu_init()
2287 if (((rdev->family) == CHIP_RV610) || in r600_gpu_init()
2288 ((rdev->family) == CHIP_RV620) || in r600_gpu_init()
2289 ((rdev->family) == CHIP_RS780) || in r600_gpu_init()
2290 ((rdev->family) == CHIP_RS880)) { in r600_gpu_init()
2313 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2314 switch (rdev->family) { in r600_gpu_init()
2357 switch (rdev->family) { in r600_gpu_init()
2400 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in r600_pciep_rreg()
2404 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in r600_pciep_rreg()
2412 spin_lock_irqsave(&rdev->pciep_idx_lock, flags); in r600_pciep_wreg()
2417 spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags); in r600_pciep_wreg()
2425 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_stop()
2426 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_cp_stop()
2429 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in r600_cp_stop()
2443 switch (rdev->family) { in r600_init_microcode()
2537 if (rdev->family >= CHIP_CEDAR) { in r600_init_microcode()
2541 } else if (rdev->family >= CHIP_RV770) { in r600_init_microcode()
2554 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in r600_init_microcode()
2557 if (rdev->pfp_fw->size != pfp_req_size) { in r600_init_microcode()
2559 rdev->pfp_fw->size, fw_name); in r600_init_microcode()
2560 err = -EINVAL; in r600_init_microcode()
2565 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in r600_init_microcode()
2568 if (rdev->me_fw->size != me_req_size) { in r600_init_microcode()
2570 rdev->me_fw->size, fw_name); in r600_init_microcode()
2571 err = -EINVAL; in r600_init_microcode()
2576 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in r600_init_microcode()
2579 if (rdev->rlc_fw->size != rlc_req_size) { in r600_init_microcode()
2581 rdev->rlc_fw->size, fw_name); in r600_init_microcode()
2582 err = -EINVAL; in r600_init_microcode()
2586 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_HEMLOCK)) { in r600_init_microcode()
2588 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in r600_init_microcode()
2591 release_firmware(rdev->smc_fw); in r600_init_microcode()
2592 rdev->smc_fw = NULL; in r600_init_microcode()
2594 } else if (rdev->smc_fw->size != smc_req_size) { in r600_init_microcode()
2596 rdev->smc_fw->size, fw_name); in r600_init_microcode()
2597 err = -EINVAL; in r600_init_microcode()
2603 if (err != -EINVAL) in r600_init_microcode()
2606 release_firmware(rdev->pfp_fw); in r600_init_microcode()
2607 rdev->pfp_fw = NULL; in r600_init_microcode()
2608 release_firmware(rdev->me_fw); in r600_init_microcode()
2609 rdev->me_fw = NULL; in r600_init_microcode()
2610 release_firmware(rdev->rlc_fw); in r600_init_microcode()
2611 rdev->rlc_fw = NULL; in r600_init_microcode()
2612 release_firmware(rdev->smc_fw); in r600_init_microcode()
2613 rdev->smc_fw = NULL; in r600_init_microcode()
2623 if (rdev->wb.enabled) in r600_gfx_get_rptr()
2624 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_gfx_get_rptr()
2640 WREG32(R600_CP_RB_WPTR, ring->wptr); in r600_gfx_set_wptr()
2649 if (!rdev->me_fw || !rdev->pfp_fw) in r600_cp_load_microcode()
2650 return -EINVAL; in r600_cp_load_microcode()
2668 fw_data = (const __be32 *)rdev->me_fw->data; in r600_cp_load_microcode()
2674 fw_data = (const __be32 *)rdev->pfp_fw->data; in r600_cp_load_microcode()
2688 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_start()
2699 if (rdev->family >= CHIP_RV770) { in r600_cp_start()
2701 radeon_ring_write(ring, rdev->config.rv770.max_hw_contexts - 1); in r600_cp_start()
2704 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
2718 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_resume()
2730 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2744 ring->wptr = 0; in r600_cp_resume()
2745 WREG32(CP_RB_WPTR, ring->wptr); in r600_cp_resume()
2749 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2750 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2751 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2753 if (rdev->wb.enabled) in r600_cp_resume()
2763 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in r600_cp_resume()
2767 ring->ready = true; in r600_cp_resume()
2770 ring->ready = false; in r600_cp_resume()
2774 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in r600_cp_resume()
2775 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r600_cp_resume()
2788 ring->ring_size = ring_size; in r600_ring_init()
2789 ring->align_mask = 16 - 1; in r600_ring_init()
2792 r = radeon_scratch_get(rdev, &ring->rptr_save_reg); in r600_ring_init()
2795 ring->rptr_save_reg = 0; in r600_ring_init()
2802 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_cp_fini()
2805 radeon_scratch_free(rdev, ring->rptr_save_reg); in r600_cp_fini()
2815 rdev->scratch.num_reg = 7; in r600_scratch_init()
2816 rdev->scratch.reg_base = SCRATCH_REG0; in r600_scratch_init()
2817 for (i = 0; i < rdev->scratch.num_reg; i++) { in r600_scratch_init()
2818 rdev->scratch.free[i] = true; in r600_scratch_init()
2819 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in r600_scratch_init()
2838 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); in r600_ring_test()
2843 radeon_ring_write(ring, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); in r600_ring_test()
2846 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ring_test()
2852 if (i < rdev->usec_timeout) { in r600_ring_test()
2853 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); in r600_ring_test()
2856 ring->idx, scratch, tmp); in r600_ring_test()
2857 r = -EINVAL; in r600_ring_test()
2870 struct radeon_ring *ring = &rdev->ring[fence->ring]; in r600_fence_ring_emit()
2874 if (rdev->family >= CHIP_RV770) in r600_fence_ring_emit()
2877 if (rdev->wb.use_event) { in r600_fence_ring_emit()
2878 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in r600_fence_ring_emit()
2885 /* EVENT_WRITE_EOP - flush caches, send int */ in r600_fence_ring_emit()
2890 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2903 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_fence_ring_emit()
2907 …radeon_ring_write(ring, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET… in r600_fence_ring_emit()
2908 radeon_ring_write(ring, fence->seq); in r600_fence_ring_emit()
2916 * r600_semaphore_ring_emit - emit a semaphore on the CP ring
2931 uint64_t addr = semaphore->gpu_addr; in r600_semaphore_ring_emit()
2934 if (rdev->family < CHIP_CAYMAN) in r600_semaphore_ring_emit()
2942 if (emit_wait && (rdev->family >= CHIP_CEDAR)) { in r600_semaphore_ring_emit()
2952 * r600_copy_cpdma - copy pages using the CP DMA engine
2971 int ring_index = rdev->asic->copy.blit_ring_index; in r600_copy_cpdma()
2972 struct radeon_ring *ring = &rdev->ring[ring_index]; in r600_copy_cpdma()
2989 radeon_sync_rings(rdev, &sync, ring->idx); in r600_copy_cpdma()
2992 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
2998 size_in_bytes -= cur_size_in_bytes; in r600_copy_cpdma()
3012 radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_copy_cpdma()
3015 r = radeon_fence_emit(rdev, &fence, ring->idx); in r600_copy_cpdma()
3045 if (!rdev->has_uvd) in r600_uvd_init()
3050 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in r600_uvd_init()
3052 * At this point rdev->uvd.vcpu_bo is NULL which trickles down in r600_uvd_init()
3057 rdev->has_uvd = false; in r600_uvd_init()
3060 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in r600_uvd_init()
3061 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in r600_uvd_init()
3068 if (!rdev->has_uvd) in r600_uvd_start()
3073 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in r600_uvd_start()
3078 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in r600_uvd_start()
3084 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in r600_uvd_start()
3092 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in r600_uvd_resume()
3095 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in r600_uvd_resume()
3096 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in r600_uvd_resume()
3098 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in r600_uvd_resume()
3103 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in r600_uvd_resume()
3123 if (rdev->flags & RADEON_IS_AGP) { in r600_startup()
3139 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r600_startup()
3146 if (!rdev->irq.installed) { in r600_startup()
3160 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r600_startup()
3161 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in r600_startup()
3177 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r600_startup()
3213 atom_asic_init(rdev->mode_info.atom_context); in r600_resume()
3215 if (rdev->pm.pm_method == PM_METHOD_DPM) in r600_resume()
3218 rdev->accel_working = true; in r600_resume()
3222 rdev->accel_working = false; in r600_resume()
3234 if (rdev->has_uvd) { in r600_suspend()
3259 return -EINVAL; in r600_init()
3262 if (!rdev->is_atom_bios) { in r600_init()
3263 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); in r600_init()
3264 return -EINVAL; in r600_init()
3271 if (!rdev->bios) { in r600_init()
3272 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in r600_init()
3273 return -EINVAL; in r600_init()
3276 atom_asic_init(rdev->mode_info.atom_context); in r600_init()
3286 if (rdev->flags & RADEON_IS_AGP) { in r600_init()
3299 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in r600_init()
3310 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in r600_init()
3311 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in r600_init()
3315 rdev->ih.ring_obj = NULL; in r600_init()
3322 rdev->accel_working = true; in r600_init()
3325 dev_err(rdev->dev, "disabling GPU acceleration\n"); in r600_init()
3332 rdev->accel_working = false; in r600_init()
3344 if (rdev->has_uvd) { in r600_fini()
3358 kfree(rdev->bios); in r600_fini()
3359 rdev->bios = NULL; in r600_fini()
3368 struct radeon_ring *ring = &rdev->ring[ib->ring]; in r600_ring_ib_execute()
3371 if (ring->rptr_save_reg) { in r600_ring_ib_execute()
3372 next_rptr = ring->wptr + 3 + 4; in r600_ring_ib_execute()
3374 radeon_ring_write(ring, ((ring->rptr_save_reg - in r600_ring_ib_execute()
3377 } else if (rdev->wb.enabled) { in r600_ring_ib_execute()
3378 next_rptr = ring->wptr + 5 + 4; in r600_ring_ib_execute()
3380 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in r600_ring_ib_execute()
3381 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18)); in r600_ring_ib_execute()
3391 (ib->gpu_addr & 0xFFFFFFFC)); in r600_ring_ib_execute()
3392 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in r600_ring_ib_execute()
3393 radeon_ring_write(ring, ib->length_dw); in r600_ring_ib_execute()
3410 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in r600_ib_test()
3416 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); in r600_ib_test()
3431 r = -ETIMEDOUT; in r600_ib_test()
3435 for (i = 0; i < rdev->usec_timeout; i++) { in r600_ib_test()
3441 if (i < rdev->usec_timeout) { in r600_ib_test()
3442 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); in r600_ib_test()
3446 r = -EINVAL; in r600_ib_test()
3463 * current interrupts have been processed.
3473 rdev->ih.ring_size = ring_size; in r600_ih_ring_init()
3474 rdev->ih.ptr_mask = rdev->ih.ring_size - 1; in r600_ih_ring_init()
3475 rdev->ih.rptr = 0; in r600_ih_ring_init()
3483 if (rdev->ih.ring_obj == NULL) { in r600_ih_ring_alloc()
3484 r = radeon_bo_create(rdev, rdev->ih.ring_size, in r600_ih_ring_alloc()
3487 NULL, NULL, &rdev->ih.ring_obj); in r600_ih_ring_alloc()
3492 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_alloc()
3495 r = radeon_bo_pin(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3497 &rdev->ih.gpu_addr); in r600_ih_ring_alloc()
3499 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3503 r = radeon_bo_kmap(rdev->ih.ring_obj, in r600_ih_ring_alloc()
3504 (void **)&rdev->ih.ring); in r600_ih_ring_alloc()
3505 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_alloc()
3517 if (rdev->ih.ring_obj) { in r600_ih_ring_fini()
3518 r = radeon_bo_reserve(rdev->ih.ring_obj, false); in r600_ih_ring_fini()
3520 radeon_bo_kunmap(rdev->ih.ring_obj); in r600_ih_ring_fini()
3521 radeon_bo_unpin(rdev->ih.ring_obj); in r600_ih_ring_fini()
3522 radeon_bo_unreserve(rdev->ih.ring_obj); in r600_ih_ring_fini()
3524 radeon_bo_unref(&rdev->ih.ring_obj); in r600_ih_ring_fini()
3525 rdev->ih.ring = NULL; in r600_ih_ring_fini()
3526 rdev->ih.ring_obj = NULL; in r600_ih_ring_fini()
3533 if ((rdev->family >= CHIP_RV770) && in r600_rlc_stop()
3534 (rdev->family <= CHIP_RV740)) { in r600_rlc_stop()
3556 if (!rdev->rlc_fw) in r600_rlc_resume()
3557 return -EINVAL; in r600_rlc_resume()
3571 fw_data = (const __be32 *)rdev->rlc_fw->data; in r600_rlc_resume()
3572 if (rdev->family >= CHIP_RV770) { in r600_rlc_resume()
3599 rdev->ih.enabled = true; in r600_enable_interrupts()
3614 rdev->ih.enabled = false; in r600_disable_interrupts()
3615 rdev->ih.rptr = 0; in r600_disable_interrupts()
3686 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3697 WREG32(INTERRUPT_CNTL2, rdev->dummy_page.addr >> 8); in r600_irq_init()
3699 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi in r600_irq_init()
3700 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN in r600_irq_init()
3703 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */ in r600_irq_init()
3707 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3708 rb_bufsz = order_base_2(rdev->ih.ring_size / 4); in r600_irq_init()
3714 if (rdev->wb.enabled) in r600_irq_init()
3718 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3719 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3730 if (rdev->msi_enabled) in r600_irq_init()
3735 if (rdev->family >= CHIP_CEDAR) in r600_irq_init()
3741 pci_set_master(rdev->pdev); in r600_irq_init()
3771 if (!rdev->irq.installed) { in r600_irq_set()
3773 return -EINVAL; in r600_irq_set()
3776 if (!rdev->ih.enabled) { in r600_irq_set()
3807 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { in r600_irq_set()
3810 } else if (rdev->family >= CHIP_RV770) { in r600_irq_set()
3814 if (rdev->irq.dpm_thermal) { in r600_irq_set()
3819 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in r600_irq_set()
3825 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in r600_irq_set()
3830 if (rdev->irq.crtc_vblank_int[0] || in r600_irq_set()
3831 atomic_read(&rdev->irq.pflip[0])) { in r600_irq_set()
3835 if (rdev->irq.crtc_vblank_int[1] || in r600_irq_set()
3836 atomic_read(&rdev->irq.pflip[1])) { in r600_irq_set()
3840 if (rdev->irq.hpd[0]) { in r600_irq_set()
3844 if (rdev->irq.hpd[1]) { in r600_irq_set()
3848 if (rdev->irq.hpd[2]) { in r600_irq_set()
3852 if (rdev->irq.hpd[3]) { in r600_irq_set()
3856 if (rdev->irq.hpd[4]) { in r600_irq_set()
3860 if (rdev->irq.hpd[5]) { in r600_irq_set()
3864 if (rdev->irq.afmt[0]) { in r600_irq_set()
3868 if (rdev->irq.afmt[1]) { in r600_irq_set()
3900 if ((rdev->family > CHIP_R600) && (rdev->family < CHIP_RV770)) { in r600_irq_set()
3902 } else if (rdev->family >= CHIP_RV770) { in r600_irq_set()
3917 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3918 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3919 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3921 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3922 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3924 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3925 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3928 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3929 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3930 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3931 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3932 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3934 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3935 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3937 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3939 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3941 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3943 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3945 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3947 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3949 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3960 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3971 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3982 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3988 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3993 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
3998 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4003 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4009 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4014 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4041 if (rdev->wb.enabled) in r600_get_ih_wptr()
4042 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in r600_get_ih_wptr()
4052 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in r600_get_ih_wptr()
4053 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in r600_get_ih_wptr()
4054 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in r600_get_ih_wptr()
4059 return (wptr & rdev->ih.ptr_mask); in r600_get_ih_wptr()
4064 * [7:0] - interrupt source id
4065 * [31:8] - reserved
4066 * [59:32] - interrupt source data
4067 * [127:60] - reserved
4078 * 19 2 DAC A auto-detection
4079 * 19 3 DAC B auto-detection
4082 * 176 - CP_INT RB
4083 * 177 - CP_INT IB1
4084 * 178 - CP_INT IB2
4085 * 181 - EOP Interrupt
4086 * 233 - GUI Idle
4102 if (!rdev->ih.enabled || rdev->shutdown) in r600_irq_process()
4106 if (!rdev->msi_enabled) in r600_irq_process()
4113 if (atomic_xchg(&rdev->ih.lock, 1)) in r600_irq_process()
4116 rptr = rdev->ih.rptr; in r600_irq_process()
4128 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in r600_irq_process()
4129 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in r600_irq_process()
4135 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4136 DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4138 if (rdev->irq.crtc_vblank_int[0]) { in r600_irq_process()
4140 rdev->pm.vblank_sync = true; in r600_irq_process()
4141 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
4143 if (atomic_read(&rdev->irq.pflip[0])) in r600_irq_process()
4145 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
4150 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) in r600_irq_process()
4151 DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4153 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
4165 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) in r600_irq_process()
4166 DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4168 if (rdev->irq.crtc_vblank_int[1]) { in r600_irq_process()
4170 rdev->pm.vblank_sync = true; in r600_irq_process()
4171 wake_up(&rdev->irq.vblank_queue); in r600_irq_process()
4173 if (atomic_read(&rdev->irq.pflip[1])) in r600_irq_process()
4175 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
4180 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) in r600_irq_process()
4181 DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4183 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
4202 case 19: /* HPD/DAC hotplug */ in r600_irq_process()
4205 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) in r600_irq_process()
4206 DRM_DEBUG("IH: HPD1 - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4208 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
4213 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) in r600_irq_process()
4214 DRM_DEBUG("IH: HPD2 - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4216 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
4221 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) in r600_irq_process()
4222 DRM_DEBUG("IH: HPD3 - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4224 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
4229 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) in r600_irq_process()
4230 DRM_DEBUG("IH: HPD4 - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4232 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
4237 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) in r600_irq_process()
4238 DRM_DEBUG("IH: HPD5 - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4240 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
4245 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) in r600_irq_process()
4246 DRM_DEBUG("IH: HPD6 - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4248 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
4261 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4262 DRM_DEBUG("IH: HDMI0 - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4264 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4270 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4271 DRM_DEBUG("IH: HDMI1 - IH event w/o asserted irq bit?\n"); in r600_irq_process()
4273 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4301 case 230: /* thermal low to high */ in r600_irq_process()
4302 DRM_DEBUG("IH: thermal low to high\n"); in r600_irq_process()
4303 rdev->pm.dpm.thermal.high_to_low = false; in r600_irq_process()
4306 case 231: /* thermal high to low */ in r600_irq_process()
4307 DRM_DEBUG("IH: thermal high to low\n"); in r600_irq_process()
4308 rdev->pm.dpm.thermal.high_to_low = true; in r600_irq_process()
4321 rptr &= rdev->ih.ptr_mask; in r600_irq_process()
4325 schedule_delayed_work(&rdev->hotplug_work, 0); in r600_irq_process()
4327 schedule_work(&rdev->audio_work); in r600_irq_process()
4328 if (queue_thermal && rdev->pm.dpm_enabled) in r600_irq_process()
4329 schedule_work(&rdev->pm.dpm.thermal.work); in r600_irq_process()
4330 rdev->ih.rptr = rptr; in r600_irq_process()
4331 atomic_set(&rdev->ih.lock, 0); in r600_irq_process()
4348 struct radeon_device *rdev = m->private; in r600_debugfs_mc_info_show()
4361 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; in r600_debugfs_mc_info_init()
4370 * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
4385 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && in r600_mmio_hdp_flush()
4386 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { in r600_mmio_hdp_flush()
4387 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; in r600_mmio_hdp_flush()
4399 if (rdev->flags & RADEON_IS_IGP) in r600_set_pcie_lanes()
4402 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_set_pcie_lanes()
4452 if (rdev->flags & RADEON_IS_IGP) in r600_get_pcie_lanes()
4455 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_get_pcie_lanes()
4493 if (rdev->flags & RADEON_IS_IGP) in r600_pcie_gen2_enable()
4496 if (!(rdev->flags & RADEON_IS_PCIE)) in r600_pcie_gen2_enable()
4504 if (rdev->family <= CHIP_R600) in r600_pcie_gen2_enable()
4507 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in r600_pcie_gen2_enable()
4508 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in r600_pcie_gen2_enable()
4520 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4521 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4522 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4545 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4546 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4547 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4572 if ((rdev->family == CHIP_RV670) || in r600_pcie_gen2_enable()
4573 (rdev->family == CHIP_RV620) || in r600_pcie_gen2_enable()
4574 (rdev->family == CHIP_RV635)) { in r600_pcie_gen2_enable()
4600 * r600_get_gpu_clock_counter - return GPU clock counter snapshot
4604 * Fetches a GPU clock counter snapshot (R6xx-cayman).
4611 mutex_lock(&rdev->gpu_clock_mutex); in r600_get_gpu_clock_counter()
4615 mutex_unlock(&rdev->gpu_clock_mutex); in r600_get_gpu_clock_counter()