Lines Matching +full:frc +full:- +full:shared
95 /* State based - direct writes to registers trigger vertex
107 /* index size - when not set the indices are assumed to be 16 bit */
147 /* BEGIN: Vertex data assembly - lots of uncertainties */
207 * - always set up to produce at least two attributes:
209 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.
307 /* These seem to be per-pixel and per-vertex X and Y clipping planes. The first
308 * plane is per-pixel and the second plane is per-vertex.
330 # define R300_2288_R300 0x00750000 /* -- nh */
331 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */
381 /* These are values from r300_reg/r300_reg.h - they are known to be correct
383 * - Vladimir
430 /* MSPOS - positions for multisample antialiasing (?) */
432 /* shifts - each of the fields is 4 bits */
605 * perform depth test (see --vb-triangles in r300_demo)
606 * Don't know about other chips. - Vladimir
623 /* BEGIN: Rasterization / Interpolators - many guesses */
699 * correct or not. - Oliver.
709 /* END: Rasterization / Interpolators - many guesses */
735 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
736 * on whether the pixel is inside cliprects 0-3, respectively. For example,
745 * For some reason, the top-left corner of the framebuffer is at (1440, 1440)
890 /* 0x16 - some 16 bit green format.. ?? */
896 /* Note - hardware supports both 16 and 32 bit floating point */
1008 * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The
1061 * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands
1062 * - DP4: Use OUTC_DP4, OUTA_DP4
1063 * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands
1064 * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands
1065 * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG1
1066 * - CMP: If ARG2 < 0, return ARG1, else return ARG0
1067 * - FLR: use FRC+MAD
1068 * - XPD: use MAD+MAD
1069 * - SGE, SLT: use MAD+CMP
1070 * - RSQ: use ABS modifier for argument
1071 * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation
1073 * - apparently, there's no quick DST operation
1074 * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"
1075 * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"
1076 * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"
1111 * - Argument order is the same as in ARB_fragment_program.
1112 * - Operation is MAD
1113 * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP
1114 * - Set FPI0/FPI2_SPECIAL_LRP
1298 * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in
1300 * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND
1303 * - Most blend flags are simply copied from R200 and not tested yet
1311 /* the following are shared between CBLEND and ABLEND */
1387 /* There seems to be no "write only" setting, so use Z-test = ALWAYS
1389 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd
1588 * - ABS r, a is implemented as MAX r, a, -a
1589 * - MOV is implemented as ADD to zero
1590 * - XPD is implemented as MUL + MAD
1591 * - FLR is implemented as FRC + ADD
1592 * - apparently, fglrx tries to schedule instructions so that there is at
1596 * - register indices seem to be unrelated with OpenGL aliasing to
1598 * - only one attribute and one parameter can be loaded at a time; however,
1600 * - the second software argument for POW is the third hardware argument
1602 * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2
1764 * CP type-3 packets