220 	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));  in r300_fence_ring_emit()
221 	radeon_ring_write(ring, 0);  in r300_fence_ring_emit()
222 	radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));  in r300_fence_ring_emit()
223 	radeon_ring_write(ring, 0);  in r300_fence_ring_emit()
225 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_fence_ring_emit()
226 	radeon_ring_write(ring, R300_RB3D_DC_FLUSH);  in r300_fence_ring_emit()
227 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_fence_ring_emit()
228 	radeon_ring_write(ring, R300_ZC_FLUSH);  in r300_fence_ring_emit()
230 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_fence_ring_emit()
231 	radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |  in r300_fence_ring_emit()
234 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r300_fence_ring_emit()
235 	radeon_ring_write(ring, rdev->config.r300.hdp_cntl |  in r300_fence_ring_emit()
237 	radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));  in r300_fence_ring_emit()
238 	radeon_ring_write(ring, rdev->config.r300.hdp_cntl);  in r300_fence_ring_emit()
240 	radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));  in r300_fence_ring_emit()
241 	radeon_ring_write(ring, fence->seq);  in r300_fence_ring_emit()
242 	radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));  in r300_fence_ring_emit()
243 	radeon_ring_write(ring, RADEON_SW_INT_FIRE);  in r300_fence_ring_emit()
273 	radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));  in r300_ring_start()
274 	radeon_ring_write(ring,  in r300_ring_start()
279 	radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));  in r300_ring_start()
280 	radeon_ring_write(ring, gb_tile_config);  in r300_ring_start()
281 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_ring_start()
282 	radeon_ring_write(ring,  in r300_ring_start()
285 	radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));  in r300_ring_start()
286 	radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);  in r300_ring_start()
287 	radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));  in r300_ring_start()
288 	radeon_ring_write(ring, 0);  in r300_ring_start()
289 	radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));  in r300_ring_start()
290 	radeon_ring_write(ring, 0);  in r300_ring_start()
291 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_ring_start()
292 	radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);  in r300_ring_start()
293 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_ring_start()
294 	radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);  in r300_ring_start()
295 	radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));  in r300_ring_start()
296 	radeon_ring_write(ring,  in r300_ring_start()
299 	radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));  in r300_ring_start()
300 	radeon_ring_write(ring, 0);  in r300_ring_start()
301 	radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));  in r300_ring_start()
302 	radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);  in r300_ring_start()
303 	radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));  in r300_ring_start()
304 	radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);  in r300_ring_start()
305 	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));  in r300_ring_start()
306 	radeon_ring_write(ring,  in r300_ring_start()
315 	radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));  in r300_ring_start()
316 	radeon_ring_write(ring,  in r300_ring_start()
324 	radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));  in r300_ring_start()
325 	radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);  in r300_ring_start()
326 	radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));  in r300_ring_start()
327 	radeon_ring_write(ring,  in r300_ring_start()
329 	radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));  in r300_ring_start()
330 	radeon_ring_write(ring,  in r300_ring_start()