Lines Matching +full:1 +full:x
52 # define ECLK_DIR_CNTL_EN (1 << 8)
54 # define ECLK_STATUS (1 << 0)
60 #define RINGID(x) (((x) & 0x3) << 0) argument
61 #define VMID(x) (((x) & 0x7) << 0) argument
63 #define RLC_RQ_PENDING (1 << 3)
64 #define GRBM_RQ_PENDING (1 << 5)
65 #define VMC_BUSY (1 << 8)
66 #define MCB_BUSY (1 << 9)
67 #define MCB_NON_DISPLAY_BUSY (1 << 10)
68 #define MCC_BUSY (1 << 11)
69 #define MCD_BUSY (1 << 12)
70 #define SEM_BUSY (1 << 14)
71 #define RLC_BUSY (1 << 15)
72 #define IH_BUSY (1 << 17)
75 #define SOFT_RESET_BIF (1 << 1)
76 #define SOFT_RESET_CG (1 << 2)
77 #define SOFT_RESET_DC (1 << 5)
78 #define SOFT_RESET_DMA1 (1 << 6)
79 #define SOFT_RESET_GRBM (1 << 8)
80 #define SOFT_RESET_HDP (1 << 9)
81 #define SOFT_RESET_IH (1 << 10)
82 #define SOFT_RESET_MC (1 << 11)
83 #define SOFT_RESET_RLC (1 << 13)
84 #define SOFT_RESET_ROM (1 << 14)
85 #define SOFT_RESET_SEM (1 << 15)
86 #define SOFT_RESET_VMC (1 << 17)
87 #define SOFT_RESET_DMA (1 << 20)
88 #define SOFT_RESET_TST (1 << 21)
89 #define SOFT_RESET_REGBB (1 << 22)
90 #define SOFT_RESET_ORB (1 << 23)
97 #define DMA_BUSY (1 << 5)
98 #define DMA1_BUSY (1 << 6)
101 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) argument
105 #define ENABLE_L2_CACHE (1 << 0)
106 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
107 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
108 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
109 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14) argument
110 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 18) argument
113 * 1 logical via context1 page table
118 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
119 #define INVALIDATE_L2_CACHE (1 << 1)
121 #define BANK_SELECT(x) ((x) << 0) argument
122 #define CACHE_UPDATE_MODE(x) ((x) << 6) argument
123 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
124 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) argument
126 #define L2_BUSY (1 << 0)
128 #define ENABLE_CONTEXT (1 << 0)
129 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) argument
130 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
131 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
132 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
133 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
134 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
135 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
136 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
137 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
138 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
139 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
140 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
141 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
142 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) argument
160 #define MEMORY_CLIENT_RW_MASK (1 << 24)
179 #define ENABLE_L1_TLB (1 << 0)
180 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
182 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
186 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
203 #define CHANSIZE_OVERRIDE (1 << 11)
205 #define RUN_MASK (1 << 0)
208 #define MEM_FALL_OUT_CMD (1 << 8)
222 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
237 #define GRBM_READ_TIMEOUT(x) ((x) << 0) argument
240 #define RING2_RQ_PENDING (1 << 4)
241 #define SRBM_RQ_PENDING (1 << 5)
242 #define RING1_RQ_PENDING (1 << 6)
243 #define CF_RQ_PENDING (1 << 7)
244 #define PF_RQ_PENDING (1 << 8)
245 #define GDS_DMA_RQ_PENDING (1 << 9)
246 #define GRBM_EE_BUSY (1 << 10)
247 #define SX_CLEAN (1 << 11)
248 #define DB_CLEAN (1 << 12)
249 #define CB_CLEAN (1 << 13)
250 #define TA_BUSY (1 << 14)
251 #define GDS_BUSY (1 << 15)
252 #define VGT_BUSY_NO_DMA (1 << 16)
253 #define VGT_BUSY (1 << 17)
254 #define IA_BUSY_NO_DMA (1 << 18)
255 #define IA_BUSY (1 << 19)
256 #define SX_BUSY (1 << 20)
257 #define SH_BUSY (1 << 21)
258 #define SPI_BUSY (1 << 22)
259 #define SC_BUSY (1 << 24)
260 #define PA_BUSY (1 << 25)
261 #define DB_BUSY (1 << 26)
262 #define CP_COHERENCY_BUSY (1 << 28)
263 #define CP_BUSY (1 << 29)
264 #define CB_BUSY (1 << 30)
265 #define GUI_ACTIVE (1 << 31)
268 #define SE_SX_CLEAN (1 << 0)
269 #define SE_DB_CLEAN (1 << 1)
270 #define SE_CB_CLEAN (1 << 2)
271 #define SE_VGT_BUSY (1 << 23)
272 #define SE_PA_BUSY (1 << 24)
273 #define SE_TA_BUSY (1 << 25)
274 #define SE_SX_BUSY (1 << 26)
275 #define SE_SPI_BUSY (1 << 27)
276 #define SE_SH_BUSY (1 << 28)
277 #define SE_SC_BUSY (1 << 29)
278 #define SE_DB_BUSY (1 << 30)
279 #define SE_CB_BUSY (1 << 31)
281 #define SOFT_RESET_CP (1 << 0)
282 #define SOFT_RESET_CB (1 << 1)
283 #define SOFT_RESET_DB (1 << 3)
284 #define SOFT_RESET_GDS (1 << 4)
285 #define SOFT_RESET_PA (1 << 5)
286 #define SOFT_RESET_SC (1 << 6)
287 #define SOFT_RESET_SPI (1 << 8)
288 #define SOFT_RESET_SH (1 << 9)
289 #define SOFT_RESET_SX (1 << 10)
290 #define SOFT_RESET_TC (1 << 11)
291 #define SOFT_RESET_TA (1 << 12)
292 #define SOFT_RESET_VGT (1 << 14)
293 #define SOFT_RESET_IA (1 << 15)
296 #define INSTANCE_INDEX(x) ((x) << 0) argument
297 #define SE_INDEX(x) ((x) << 16) argument
298 #define INSTANCE_BROADCAST_WRITES (1 << 30)
299 #define SE_BROADCAST_WRITES (1 << 31)
319 #define CP_ME_HALT (1 << 28)
320 #define CP_PFP_HALT (1 << 26)
326 #define MEQ1_START(x) ((x) << 0) argument
327 #define MEQ2_START(x) ((x) << 8) argument
331 #define CACHE_INVALIDATION(x) ((x) << 0) argument
333 #define TC_ONLY 1
335 #define AUTO_INVLD_EN(x) ((x) << 6) argument
337 #define ES_AUTO 1
344 #define INACTIVE_QD_PIPES(x) ((x) << 8) argument
347 #define INACTIVE_SIMDS(x) ((x) << 16) argument
358 #define CLIP_VTX_REORDER_ENA (1 << 0)
359 #define NUM_CLIP_SEQ(x) ((x) << 1) argument
361 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0) argument
362 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) argument
363 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) argument
365 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) argument
366 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) argument
369 #define VC_ENABLE (1 << 0)
370 #define EXPORT_SRC_C (1 << 1)
371 #define GFX_PRIO(x) ((x) << 2) argument
372 #define CS1_PRIO(x) ((x) << 4) argument
373 #define CS2_PRIO(x) ((x) << 6) argument
375 #define NUM_PS_GPRS(x) ((x) << 0) argument
376 #define NUM_VS_GPRS(x) ((x) << 16) argument
377 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) argument
389 #define CACHE_FIFO_SIZE(x) ((x) << 0) argument
390 #define FETCH_FIFO_HIWATER(x) ((x) << 8) argument
391 #define DONE_FIFO_HIWATER(x) ((x) << 16) argument
392 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) argument
398 #define DYN_GPR_ENABLE (1 << 8)
402 #define COLOR_BUFFER_SIZE(x) ((x) << 0) argument
403 #define POSITION_BUFFER_SIZE(x) ((x) << 8) argument
404 #define SMX_BUFFER_SIZE(x) ((x) << 16) argument
406 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
409 #define GPR_WRITE_PRIORITY(x) ((x) << 0) argument
411 #define VTX_DONE_DELAY(x) ((x) << 0) argument
412 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
413 #define CRC_SIMD_ID_WADDR_DISABLE (1 << 8)
420 #define OVERRIDE (1 << 21)
423 #define DISABLE_CUBE_WRAP (1 << 0)
424 #define DISABLE_CUBE_ANISO (1 << 1)
430 #define BACKEND_DISABLE(x) ((x) << 16) argument
432 #define NUM_PIPES(x) ((x) << 0) argument
435 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) argument
438 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) argument
439 #define NUM_SHADER_ENGINES(x) ((x) << 12) argument
442 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) argument
445 #define NUM_GPUS(x) ((x) << 20) argument
448 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) argument
451 #define ROW_SIZE(x) ((x) << 28) argument
454 #define NUM_LOWER_PIPES(x) ((x) << 30) argument
473 #define USE_HASH_FUNCTION (1 << 0)
474 #define NUMBER_OF_SETS(x) ((x) << 1) argument
475 #define FLUSH_ALL_ON_EVENT (1 << 10)
476 #define STALL_ON_EVENT (1 << 11)
478 #define ES_FLUSH_CTL(x) ((x) << 0) argument
479 #define GS_FLUSH_CTL(x) ((x) << 3) argument
480 #define ACK_FLUSH_CTL(x) ((x) << 6) argument
481 #define SYNC_FLUSH_CTL (1 << 8)
485 #define RB_BUFSZ(x) ((x) << 0) argument
486 #define RB_BLKSZ(x) ((x) << 8) argument
487 #define RB_NO_UPDATE (1 << 27)
488 #define RB_RPTR_WR_ENA (1 << 31)
495 # define CNTX_BUSY_INT_ENABLE (1 << 19)
496 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
497 # define TIME_STAMP_INT_ENABLE (1 << 26)
525 #define HOST_SMC_MSG(x) ((x) << 0) argument
528 #define HOST_SMC_RESP(x) ((x) << 8) argument
531 #define SMC_HOST_MSG(x) ((x) << 16) argument
534 #define SMC_HOST_RESP(x) ((x) << 24) argument
539 #define SPLL_RESET (1 << 0)
540 #define SPLL_SLEEP (1 << 1)
541 #define SPLL_BYPASS_EN (1 << 3)
542 #define SPLL_REF_DIV(x) ((x) << 4) argument
544 #define SPLL_PDIV_A(x) ((x) << 20) argument
548 #define SCLK_MUX_SEL(x) ((x) << 0) argument
551 #define SPLL_FB_DIV(x) ((x) << 0) argument
554 #define SPLL_DITHEN (1 << 28)
557 # define SS_SSEN (1 << 24)
558 # define SS_DSMODE_EN (1 << 25)
561 #define CLKF(x) ((x) << 0) argument
563 #define CLKR(x) ((x) << 7) argument
565 #define CLKFRAC(x) ((x) << 12) argument
567 #define YCLK_POST_DIV(x) ((x) << 17) argument
569 #define IBIAS(x) ((x) << 20) argument
571 #define RESET (1 << 30)
572 #define PDNB (1 << 31)
574 #define BYPASS (1 << 19)
575 #define BIAS_GEN_PDNB (1 << 24)
576 #define RESET_EN (1 << 25)
577 #define VCO_MODE (1 << 29)
582 # define GLOBAL_PWRMGT_EN (1 << 0)
583 # define STATIC_PM_EN (1 << 1)
584 # define THERMAL_PROTECTION_DIS (1 << 2)
585 # define THERMAL_PROTECTION_TYPE (1 << 3)
586 # define ENABLE_GEN2PCIE (1 << 4)
587 # define ENABLE_GEN2XSP (1 << 5)
588 # define SW_SMIO_INDEX(x) ((x) << 6) argument
591 # define LOW_VOLT_D2_ACPI (1 << 8)
592 # define LOW_VOLT_D3_ACPI (1 << 9)
593 # define VOLT_PWRMGT_EN (1 << 10)
594 # define BACKBIAS_PAD_EN (1 << 18)
595 # define BACKBIAS_VALUE (1 << 19)
596 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
597 # define AC_DC_SW (1 << 24)
600 # define SCLK_PWRMGT_OFF (1 << 0)
601 # define SCLK_LOW_D1 (1 << 1)
602 # define FIR_RESET (1 << 4)
603 # define FIR_FORCE_TREND_SEL (1 << 5)
604 # define FIR_TREND_MODE (1 << 6)
605 # define DYN_GFX_CLK_OFF_EN (1 << 7)
606 # define GFX_CLK_FORCE_ON (1 << 8)
607 # define GFX_CLK_REQUEST_OFF (1 << 9)
608 # define GFX_CLK_FORCE_OFF (1 << 10)
609 # define GFX_CLK_OFF_ACPI_D1 (1 << 11)
610 # define GFX_CLK_OFF_ACPI_D2 (1 << 12)
611 # define GFX_CLK_OFF_ACPI_D3 (1 << 13)
612 # define DYN_LIGHT_SLEEP_EN (1 << 14)
614 # define DLL_SPEED(x) ((x) << 0) argument
616 # define MPLL_PWRMGT_OFF (1 << 5)
617 # define DLL_READY (1 << 6)
618 # define MC_INT_CNTL (1 << 7)
619 # define MRDCKA0_PDNB (1 << 8)
620 # define MRDCKA1_PDNB (1 << 9)
621 # define MRDCKB0_PDNB (1 << 10)
622 # define MRDCKB1_PDNB (1 << 11)
623 # define MRDCKC0_PDNB (1 << 12)
624 # define MRDCKC1_PDNB (1 << 13)
625 # define MRDCKD0_PDNB (1 << 14)
626 # define MRDCKD1_PDNB (1 << 15)
627 # define MRDCKA0_RESET (1 << 16)
628 # define MRDCKA1_RESET (1 << 17)
629 # define MRDCKB0_RESET (1 << 18)
630 # define MRDCKB1_RESET (1 << 19)
631 # define MRDCKC0_RESET (1 << 20)
632 # define MRDCKC1_RESET (1 << 21)
633 # define MRDCKD0_RESET (1 << 22)
634 # define MRDCKD1_RESET (1 << 23)
635 # define DLL_READY_READ (1 << 24)
636 # define USE_DISPLAY_GAP (1 << 25)
637 # define USE_DISPLAY_URGENT_NORMAL (1 << 26)
638 # define MPLL_TURNOFF_D2 (1 << 28)
640 # define MRDCKA0_BYPASS (1 << 24)
641 # define MRDCKA1_BYPASS (1 << 25)
642 # define MRDCKB0_BYPASS (1 << 26)
643 # define MRDCKB1_BYPASS (1 << 27)
644 # define MRDCKC0_BYPASS (1 << 28)
645 # define MRDCKC1_BYPASS (1 << 29)
646 # define MRDCKD0_BYPASS (1 << 30)
647 # define MRDCKD1_BYPASS (1 << 31)
654 # define CG_R(x) ((x) << 0) argument
656 # define CG_L(x) ((x) << 16) argument
660 #define CG_CLIENT_REQ(x) ((x) << 0) argument
663 #define CG_CLIENT_RESP(x) ((x) << 8) argument
666 #define CLIENT_CG_REQ(x) ((x) << 16) argument
669 #define CLIENT_CG_RESP(x) ((x) << 24) argument
674 #define SSEN (1 << 0)
675 #define CLK_S(x) ((x) << 4) argument
679 #define CLK_V(x) ((x) << 0) argument
688 #define CLKV(x) ((x) << 0) argument
691 #define CLKS(x) ((x) << 0) argument
695 #define TID_CNT(x) ((x) << 0) argument
697 #define TID_UNIT(x) ((x) << 14) argument
707 #define MCDW_WR_ENABLE (1 << 0)
708 #define MCDX_WR_ENABLE (1 << 1)
709 #define MCDY_WR_ENABLE (1 << 2)
710 #define MCDZ_WR_ENABLE (1 << 3)
711 #define MC_RD_ENABLE(x) ((x) << 4) argument
713 #define INDEX(x) ((x) << 6) argument
718 #define ENABLE (1 << 0)
719 #define READ_WEIGHT(x) ((x) << 1) argument
720 #define READ_WEIGHT_MASK (0x3f << 1)
721 #define READ_WEIGHT_SHIFT 1
722 #define WRITE_WEIGHT(x) ((x) << 7) argument
725 #define ALLOW_OVERFLOW (1 << 13)
731 #define POWERMODE0(x) ((x) << 0) argument
734 #define POWERMODE1(x) ((x) << 8) argument
737 #define POWERMODE2(x) ((x) << 16) argument
740 #define POWERMODE3(x) ((x) << 24) argument
745 #define CG_ARB_REQ(x) ((x) << 0) argument
748 #define CG_ARB_RESP(x) ((x) << 8) argument
751 #define ARB_CG_REQ(x) ((x) << 16) argument
754 #define ARB_CG_RESP(x) ((x) << 24) argument
765 #define STATE0(x) ((x) << 0) argument
768 #define STATE1(x) ((x) << 5) argument
771 #define STATE2(x) ((x) << 10) argument
774 #define STATE3(x) ((x) << 15) argument
827 #define AUX_EN (1 << 0)
828 #define AUX_LS_READ_EN (1 << 8)
829 #define AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12) argument
830 #define AUX_HPD_DISCON(x) (((x) & 0x1) << 16) argument
831 #define AUX_DET_EN (1 << 18)
832 #define AUX_HPD_SEL(x) (((x) & 0x7) << 20) argument
833 #define AUX_IMPCAL_REQ_EN (1 << 24)
834 #define AUX_TEST_MODE (1 << 28)
835 #define AUX_DEGLITCH_EN (1 << 29)
837 #define AUX_SW_GO (1 << 0)
838 #define AUX_LS_READ_TRIG (1 << 2)
839 #define AUX_SW_START_DELAY(x) (((x) & 0xf) << 4) argument
840 #define AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16) argument
843 #define AUX_SW_DONE_INT (1 << 0)
844 #define AUX_SW_DONE_ACK (1 << 1)
845 #define AUX_SW_DONE_MASK (1 << 2)
846 #define AUX_SW_LS_DONE_INT (1 << 4)
847 #define AUX_SW_LS_DONE_MASK (1 << 6)
849 #define AUX_SW_DONE (1 << 0)
850 #define AUX_SW_REQ (1 << 1)
851 #define AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4) argument
852 #define AUX_SW_RX_TIMEOUT (1 << 7)
853 #define AUX_SW_RX_OVERFLOW (1 << 8)
854 #define AUX_SW_RX_HPD_DISCON (1 << 9)
855 #define AUX_SW_RX_PARTIAL_BYTE (1 << 10)
856 #define AUX_SW_NON_AUX_MODE (1 << 11)
857 #define AUX_SW_RX_MIN_COUNT_VIOL (1 << 12)
858 #define AUX_SW_RX_INVALID_STOP (1 << 14)
859 #define AUX_SW_RX_SYNC_INVALID_L (1 << 17)
860 #define AUX_SW_RX_SYNC_INVALID_H (1 << 18)
861 #define AUX_SW_RX_INVALID_START (1 << 19)
862 #define AUX_SW_RX_RECV_NO_DET (1 << 20)
863 #define AUX_SW_RX_RECV_INVALID_H (1 << 22)
864 #define AUX_SW_RX_RECV_INVALID_V (1 << 23)
867 #define AUX_SW_DATA_RW (1 << 0)
868 #define AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8) argument
869 #define AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16) argument
870 #define AUX_SW_AUTOINCREMENT_DISABLE (1 << 31)
877 #define DC_STUTTER_ENABLE_A (1 << 0)
878 #define DC_STUTTER_ENABLE_B (1 << 1)
881 #define VSP(x) ((x) << 0) argument
884 #define VSP0(x) ((x) << 8) argument
887 #define GPR(x) ((x) << 16) argument
892 #define MIN_POWER(x) ((x) << 0) argument
895 #define MAX_POWER(x) ((x) << 16) argument
899 #define MAX_POWER_DELTA(x) ((x) << 0) argument
902 #define STI_SIZE(x) ((x) << 16) argument
905 #define LTI_RATIO(x) ((x) << 27) argument
911 #define WEIGHT_TCP_SIG0(x) ((x) << 0) argument
914 #define WEIGHT_TCP_SIG1(x) ((x) << 6) argument
917 #define WEIGHT_TA_SIG(x) ((x) << 12) argument
921 #define WEIGHT_TCC_EN0(x) ((x) << 0) argument
924 #define WEIGHT_TCC_EN1(x) ((x) << 6) argument
927 #define WEIGHT_TCC_EN2(x) ((x) << 12) argument
930 #define WEIGHT_TCC_EN3(x) ((x) << 18) argument
934 #define WEIGHT_CB_EN0(x) ((x) << 0) argument
937 #define WEIGHT_CB_EN1(x) ((x) << 6) argument
940 #define WEIGHT_CB_EN2(x) ((x) << 12) argument
943 #define WEIGHT_CB_EN3(x) ((x) << 18) argument
947 #define WEIGHT_DB_SIG0(x) ((x) << 0) argument
950 #define WEIGHT_DB_SIG1(x) ((x) << 6) argument
953 #define WEIGHT_DB_SIG2(x) ((x) << 12) argument
956 #define WEIGHT_DB_SIG3(x) ((x) << 18) argument
960 #define WEIGHT_SXM_SIG0(x) ((x) << 0) argument
963 #define WEIGHT_SXM_SIG1(x) ((x) << 6) argument
966 #define WEIGHT_SXM_SIG2(x) ((x) << 12) argument
969 #define WEIGHT_SXS_SIG0(x) ((x) << 18) argument
972 #define WEIGHT_SXS_SIG1(x) ((x) << 24) argument
976 #define WEIGHT_XBR_0(x) ((x) << 0) argument
979 #define WEIGHT_XBR_1(x) ((x) << 6) argument
982 #define WEIGHT_XBR_2(x) ((x) << 12) argument
985 #define WEIGHT_SPI_SIG0(x) ((x) << 18) argument
989 #define WEIGHT_SPI_SIG1(x) ((x) << 0) argument
992 #define WEIGHT_SPI_SIG2(x) ((x) << 6) argument
995 #define WEIGHT_SPI_SIG3(x) ((x) << 12) argument
998 #define WEIGHT_SPI_SIG4(x) ((x) << 18) argument
1001 #define WEIGHT_SPI_SIG5(x) ((x) << 24) argument
1005 #define WEIGHT_LDS_SIG0(x) ((x) << 0) argument
1008 #define WEIGHT_LDS_SIG1(x) ((x) << 6) argument
1011 #define WEIGHT_SC(x) ((x) << 24) argument
1015 #define WEIGHT_BIF(x) ((x) << 0) argument
1018 #define WEIGHT_CP(x) ((x) << 6) argument
1021 #define WEIGHT_PA_SIG0(x) ((x) << 12) argument
1024 #define WEIGHT_PA_SIG1(x) ((x) << 18) argument
1027 #define WEIGHT_VGT_SIG0(x) ((x) << 24) argument
1031 #define WEIGHT_VGT_SIG1(x) ((x) << 0) argument
1034 #define WEIGHT_VGT_SIG2(x) ((x) << 6) argument
1037 #define WEIGHT_DC_SIG0(x) ((x) << 12) argument
1040 #define WEIGHT_DC_SIG1(x) ((x) << 18) argument
1043 #define WEIGHT_DC_SIG2(x) ((x) << 24) argument
1047 #define WEIGHT_DC_SIG3(x) ((x) << 0) argument
1050 #define WEIGHT_UVD_SIG0(x) ((x) << 6) argument
1053 #define WEIGHT_UVD_SIG1(x) ((x) << 12) argument
1056 #define WEIGHT_SPARE0(x) ((x) << 18) argument
1059 #define WEIGHT_SPARE1(x) ((x) << 24) argument
1063 #define WEIGHT_SQ_VSP(x) ((x) << 0) argument
1066 #define WEIGHT_SQ_VSP0(x) ((x) << 14) argument
1070 #define OVR_MODE_SPARE_0(x) ((x) << 16) argument
1073 #define OVR_VAL_SPARE_0(x) ((x) << 17) argument
1076 #define OVR_MODE_SPARE_1(x) ((x) << 18) argument
1079 #define OVR_VAL_SPARE_1(x) ((x) << 19) argument
1083 #define WEIGHT_SQ_GPR(x) ((x) << 0) argument
1086 #define WEIGHT_SQ_LDS(x) ((x) << 14) argument
1096 # define LC_LINK_WIDTH_X1 1
1103 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
1104 # define LC_RECONFIG_NOW (1 << 8)
1105 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
1106 # define LC_RENEGOTIATE_EN (1 << 10)
1107 # define LC_SHORT_RECONFIG_EN (1 << 11)
1108 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
1109 # define LC_UPCONFIGURE_DIS (1 << 13)
1111 # define LC_GEN2_EN_STRAP (1 << 0)
1112 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
1113 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
1114 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
1117 # define LC_CURRENT_DATA_RATE (1 << 11)
1118 # define LC_HW_VOLTAGE_IF_CONTROL(x) ((x) << 12) argument
1122 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
1123 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
1124 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
1126 # define MM_WR_TO_CFG_EN (1 << 3)
1129 # define SELECTABLE_DEEMPHASIS (1 << 6)
1195 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
1197 * 1 - <
1204 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
1206 * 1 - mem
1208 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
1210 * 1 - pfp
1215 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1216 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1217 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1218 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1219 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1220 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1221 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1222 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1223 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1224 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
1225 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
1226 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
1227 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
1228 # define PACKET3_FULL_CACHE_ENA (1 << 20)
1229 # define PACKET3_TC_ACTION_ENA (1 << 23)
1230 # define PACKET3_CB_ACTION_ENA (1 << 25)
1231 # define PACKET3_DB_ACTION_ENA (1 << 26)
1232 # define PACKET3_SH_ACTION_ENA (1 << 27)
1233 # define PACKET3_SX_ACTION_ENA (1 << 28)
1234 # define PACKET3_ENGINE_ME (1 << 31)
1236 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) argument
1239 #define EVENT_TYPE(x) ((x) << 0) argument
1240 #define EVENT_INDEX(x) ((x) << 8) argument
1242 * 1 - ZPASS_DONE
1249 #define DATA_SEL(x) ((x) << 29) argument
1251 * 1 - send low 32bit data
1255 #define INT_SEL(x) ((x) << 24) argument
1257 * 1 - interrupt only (DATA_SEL = 0)
1305 # define DMA_RB_ENABLE (1 << 0)
1306 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ argument
1307 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1308 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1309 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1310 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ argument
1319 # define DMA_IB_ENABLE (1 << 0)
1320 # define DMA_IB_SWAP_ENABLE (1 << 4)
1321 # define CMD_VMID_FORCE (1 << 31)
1324 # define TRAP_ENABLE (1 << 0)
1325 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1326 # define SEM_WAIT_INT_ENABLE (1 << 2)
1327 # define DATA_SWAP_ENABLE (1 << 3)
1328 # define FENCE_SWAP_ENABLE (1 << 4)
1329 # define CTXEMPTY_INT_ENABLE (1 << 28)
1331 # define DMA_IDLE (1 << 0)
1347 (1 << 26) | \
1348 (1 << 21) | \
1352 (1 << 27) | \
1353 (1 << 26))
1356 (1 << 27))