Lines Matching full:pi
152 struct kv_power_info *pi = rdev->pm.dpm.priv; in kv_get_pi() local
154 return pi; in kv_get_pi()
208 struct kv_power_info *pi = kv_get_pi(rdev); in kv_do_enable_didt() local
211 if (pi->caps_sq_ramping) { in kv_do_enable_didt()
220 if (pi->caps_db_ramping) { in kv_do_enable_didt()
229 if (pi->caps_td_ramping) { in kv_do_enable_didt()
238 if (pi->caps_tcp_ramping) { in kv_do_enable_didt()
250 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_didt() local
253 if (pi->caps_sq_ramping || in kv_enable_didt()
254 pi->caps_db_ramping || in kv_enable_didt()
255 pi->caps_td_ramping || in kv_enable_didt()
256 pi->caps_tcp_ramping) { in kv_enable_didt()
277 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_smc_cac() local
280 if (pi->caps_cac) { in kv_enable_smc_cac()
284 pi->cac_enabled = false; in kv_enable_smc_cac()
286 pi->cac_enabled = true; in kv_enable_smc_cac()
287 } else if (pi->cac_enabled) { in kv_enable_smc_cac()
289 pi->cac_enabled = false; in kv_enable_smc_cac()
298 struct kv_power_info *pi = kv_get_pi(rdev); in kv_process_firmware_header() local
304 &tmp, pi->sram_end); in kv_process_firmware_header()
307 pi->dpm_table_start = tmp; in kv_process_firmware_header()
311 &tmp, pi->sram_end); in kv_process_firmware_header()
314 pi->soft_regs_start = tmp; in kv_process_firmware_header()
321 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_dpm_voltage_scaling() local
324 pi->graphics_voltage_change_enable = 1; in kv_enable_dpm_voltage_scaling()
327 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
329 &pi->graphics_voltage_change_enable, in kv_enable_dpm_voltage_scaling()
330 sizeof(u8), pi->sram_end); in kv_enable_dpm_voltage_scaling()
337 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_interval() local
340 pi->graphics_interval = 1; in kv_set_dpm_interval()
343 pi->dpm_table_start + in kv_set_dpm_interval()
345 &pi->graphics_interval, in kv_set_dpm_interval()
346 sizeof(u8), pi->sram_end); in kv_set_dpm_interval()
353 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_dpm_boot_state() local
357 pi->dpm_table_start + in kv_set_dpm_boot_state()
359 &pi->graphics_boot_level, in kv_set_dpm_boot_state()
360 sizeof(u8), pi->sram_end); in kv_set_dpm_boot_state()
378 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_divider_value() local
387 pi->graphics_level[index].SclkDid = (u8)dividers.post_div; in kv_set_divider_value()
388 pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk); in kv_set_divider_value()
448 struct kv_power_info *pi = kv_get_pi(rdev); in kv_convert_2bit_index_to_voltage() local
450 &pi->sys_info.vid_mapping_table, in kv_convert_2bit_index_to_voltage()
459 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_vid() local
461 pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t; in kv_set_vid()
462 pi->graphics_level[index].MinVddNb = in kv_set_vid()
470 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_at() local
472 pi->graphics_level[index].AT = cpu_to_be16((u16)at); in kv_set_at()
480 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enable() local
482 pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0; in kv_dpm_power_level_enable()
540 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_sclk_t() local
544 if (pi->caps_sclk_throttle_low_notification) { in kv_update_sclk_t()
545 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in kv_update_sclk_t()
548 pi->dpm_table_start + in kv_update_sclk_t()
551 sizeof(u32), pi->sram_end); in kv_update_sclk_t()
558 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_bootup_state() local
564 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
565 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
569 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
573 &pi->sys_info.sclk_voltage_mapping_table; in kv_program_bootup_state()
578 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_program_bootup_state()
579 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
583 pi->graphics_boot_level = (u8)i; in kv_program_bootup_state()
591 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_auto_thermal_throttling() local
594 pi->graphics_therm_throttle_enable = 1; in kv_enable_auto_thermal_throttling()
597 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
599 &pi->graphics_therm_throttle_enable, in kv_enable_auto_thermal_throttling()
600 sizeof(u8), pi->sram_end); in kv_enable_auto_thermal_throttling()
607 struct kv_power_info *pi = kv_get_pi(rdev); in kv_upload_dpm_settings() local
611 pi->dpm_table_start + in kv_upload_dpm_settings()
613 (u8 *)&pi->graphics_level, in kv_upload_dpm_settings()
615 pi->sram_end); in kv_upload_dpm_settings()
621 pi->dpm_table_start + in kv_upload_dpm_settings()
623 &pi->graphics_dpm_level_count, in kv_upload_dpm_settings()
624 sizeof(u8), pi->sram_end); in kv_upload_dpm_settings()
636 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_clk_bypass() local
639 if (pi->caps_enable_dfs_bypass) { in kv_get_clk_bypass()
661 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_uvd_table() local
671 pi->uvd_level_count = 0; in kv_populate_uvd_table()
673 if (pi->high_voltage_t && in kv_populate_uvd_table()
674 (pi->high_voltage_t < table->entries[i].v)) in kv_populate_uvd_table()
677 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk); in kv_populate_uvd_table()
678 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk); in kv_populate_uvd_table()
679 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v); in kv_populate_uvd_table()
681 pi->uvd_level[i].VClkBypassCntl = in kv_populate_uvd_table()
683 pi->uvd_level[i].DClkBypassCntl = in kv_populate_uvd_table()
690 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
696 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div; in kv_populate_uvd_table()
698 pi->uvd_level_count++; in kv_populate_uvd_table()
702 pi->dpm_table_start + in kv_populate_uvd_table()
704 (u8 *)&pi->uvd_level_count, in kv_populate_uvd_table()
705 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
709 pi->uvd_interval = 1; in kv_populate_uvd_table()
712 pi->dpm_table_start + in kv_populate_uvd_table()
714 &pi->uvd_interval, in kv_populate_uvd_table()
715 sizeof(u8), pi->sram_end); in kv_populate_uvd_table()
720 pi->dpm_table_start + in kv_populate_uvd_table()
722 (u8 *)&pi->uvd_level, in kv_populate_uvd_table()
724 pi->sram_end); in kv_populate_uvd_table()
732 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_vce_table() local
742 pi->vce_level_count = 0; in kv_populate_vce_table()
744 if (pi->high_voltage_t && in kv_populate_vce_table()
745 pi->high_voltage_t < table->entries[i].v) in kv_populate_vce_table()
748 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); in kv_populate_vce_table()
749 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_vce_table()
751 pi->vce_level[i].ClkBypassCntl = in kv_populate_vce_table()
758 pi->vce_level[i].Divider = (u8)dividers.post_div; in kv_populate_vce_table()
760 pi->vce_level_count++; in kv_populate_vce_table()
764 pi->dpm_table_start + in kv_populate_vce_table()
766 (u8 *)&pi->vce_level_count, in kv_populate_vce_table()
768 pi->sram_end); in kv_populate_vce_table()
772 pi->vce_interval = 1; in kv_populate_vce_table()
775 pi->dpm_table_start + in kv_populate_vce_table()
777 (u8 *)&pi->vce_interval, in kv_populate_vce_table()
779 pi->sram_end); in kv_populate_vce_table()
784 pi->dpm_table_start + in kv_populate_vce_table()
786 (u8 *)&pi->vce_level, in kv_populate_vce_table()
788 pi->sram_end); in kv_populate_vce_table()
795 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_samu_table() local
805 pi->samu_level_count = 0; in kv_populate_samu_table()
807 if (pi->high_voltage_t && in kv_populate_samu_table()
808 pi->high_voltage_t < table->entries[i].v) in kv_populate_samu_table()
811 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_samu_table()
812 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_samu_table()
814 pi->samu_level[i].ClkBypassCntl = in kv_populate_samu_table()
821 pi->samu_level[i].Divider = (u8)dividers.post_div; in kv_populate_samu_table()
823 pi->samu_level_count++; in kv_populate_samu_table()
827 pi->dpm_table_start + in kv_populate_samu_table()
829 (u8 *)&pi->samu_level_count, in kv_populate_samu_table()
831 pi->sram_end); in kv_populate_samu_table()
835 pi->samu_interval = 1; in kv_populate_samu_table()
838 pi->dpm_table_start + in kv_populate_samu_table()
840 (u8 *)&pi->samu_interval, in kv_populate_samu_table()
842 pi->sram_end); in kv_populate_samu_table()
847 pi->dpm_table_start + in kv_populate_samu_table()
849 (u8 *)&pi->samu_level, in kv_populate_samu_table()
851 pi->sram_end); in kv_populate_samu_table()
861 struct kv_power_info *pi = kv_get_pi(rdev); in kv_populate_acp_table() local
871 pi->acp_level_count = 0; in kv_populate_acp_table()
873 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk); in kv_populate_acp_table()
874 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v); in kv_populate_acp_table()
880 pi->acp_level[i].Divider = (u8)dividers.post_div; in kv_populate_acp_table()
882 pi->acp_level_count++; in kv_populate_acp_table()
886 pi->dpm_table_start + in kv_populate_acp_table()
888 (u8 *)&pi->acp_level_count, in kv_populate_acp_table()
890 pi->sram_end); in kv_populate_acp_table()
894 pi->acp_interval = 1; in kv_populate_acp_table()
897 pi->dpm_table_start + in kv_populate_acp_table()
899 (u8 *)&pi->acp_interval, in kv_populate_acp_table()
901 pi->sram_end); in kv_populate_acp_table()
906 pi->dpm_table_start + in kv_populate_acp_table()
908 (u8 *)&pi->acp_level, in kv_populate_acp_table()
910 pi->sram_end); in kv_populate_acp_table()
919 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dfs_bypass_settings() local
925 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
926 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
928 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
930 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
932 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
934 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
936 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
938 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
940 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
945 &pi->sys_info.sclk_voltage_mapping_table; in kv_calculate_dfs_bypass_settings()
946 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_calculate_dfs_bypass_settings()
947 if (pi->caps_enable_dfs_bypass) { in kv_calculate_dfs_bypass_settings()
949 pi->graphics_level[i].ClkBypassCntl = 3; in kv_calculate_dfs_bypass_settings()
951 pi->graphics_level[i].ClkBypassCntl = 2; in kv_calculate_dfs_bypass_settings()
953 pi->graphics_level[i].ClkBypassCntl = 7; in kv_calculate_dfs_bypass_settings()
955 pi->graphics_level[i].ClkBypassCntl = 6; in kv_calculate_dfs_bypass_settings()
957 pi->graphics_level[i].ClkBypassCntl = 8; in kv_calculate_dfs_bypass_settings()
959 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
961 pi->graphics_level[i].ClkBypassCntl = 0; in kv_calculate_dfs_bypass_settings()
975 struct kv_power_info *pi = kv_get_pi(rdev); in kv_reset_acp_boot_level() local
977 pi->acp_boot_level = 0xff; in kv_reset_acp_boot_level()
984 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_current_ps() local
986 pi->current_rps = *rps; in kv_update_current_ps()
987 pi->current_ps = *new_ps; in kv_update_current_ps()
988 pi->current_rps.ps_priv = &pi->current_ps; in kv_update_current_ps()
995 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_requested_ps() local
997 pi->requested_rps = *rps; in kv_update_requested_ps()
998 pi->requested_ps = *new_ps; in kv_update_requested_ps()
999 pi->requested_rps.ps_priv = &pi->requested_ps; in kv_update_requested_ps()
1004 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable_bapm() local
1007 if (pi->bapm_enable) { in kv_dpm_enable_bapm()
1029 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_enable() local
1073 if (pi->enable_auto_thermal_throttling) { in kv_dpm_enable()
1174 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_sclk_t() local
1176 pi->low_sclk_interrupt_t = 0; in kv_init_sclk_t()
1181 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_fps_limits() local
1184 if (pi->caps_fps) { in kv_init_fps_limits()
1188 pi->fps_high_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1190 pi->dpm_table_start + in kv_init_fps_limits()
1192 (u8 *)&pi->fps_high_t, in kv_init_fps_limits()
1193 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1196 pi->fps_low_t = cpu_to_be16(tmp); in kv_init_fps_limits()
1199 pi->dpm_table_start + in kv_init_fps_limits()
1201 (u8 *)&pi->fps_low_t, in kv_init_fps_limits()
1202 sizeof(u16), pi->sram_end); in kv_init_fps_limits()
1210 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_powergate_state() local
1212 pi->uvd_power_gated = false; in kv_init_powergate_state()
1213 pi->vce_power_gated = false; in kv_init_powergate_state()
1214 pi->samu_power_gated = false; in kv_init_powergate_state()
1215 pi->acp_power_gated = false; in kv_init_powergate_state()
1245 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_uvd_dpm() local
1253 pi->uvd_boot_level = table->count - 1; in kv_update_uvd_dpm()
1255 pi->uvd_boot_level = 0; in kv_update_uvd_dpm()
1257 if (!pi->caps_uvd_dpm || pi->caps_stable_p_state) { in kv_update_uvd_dpm()
1258 mask = 1 << pi->uvd_boot_level; in kv_update_uvd_dpm()
1264 pi->dpm_table_start + in kv_update_uvd_dpm()
1266 (uint8_t *)&pi->uvd_boot_level, in kv_update_uvd_dpm()
1267 sizeof(u8), pi->sram_end); in kv_update_uvd_dpm()
1297 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_vce_dpm() local
1306 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1307 pi->vce_boot_level = table->count - 1; in kv_update_vce_dpm()
1309 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); in kv_update_vce_dpm()
1312 pi->dpm_table_start + in kv_update_vce_dpm()
1314 (u8 *)&pi->vce_boot_level, in kv_update_vce_dpm()
1316 pi->sram_end); in kv_update_vce_dpm()
1320 if (pi->caps_stable_p_state) in kv_update_vce_dpm()
1323 (1 << pi->vce_boot_level)); in kv_update_vce_dpm()
1338 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_samu_dpm() local
1344 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1345 pi->samu_boot_level = table->count - 1; in kv_update_samu_dpm()
1347 pi->samu_boot_level = 0; in kv_update_samu_dpm()
1350 pi->dpm_table_start + in kv_update_samu_dpm()
1352 (u8 *)&pi->samu_boot_level, in kv_update_samu_dpm()
1354 pi->sram_end); in kv_update_samu_dpm()
1358 if (pi->caps_stable_p_state) in kv_update_samu_dpm()
1361 (1 << pi->samu_boot_level)); in kv_update_samu_dpm()
1386 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_boot_level() local
1389 if (!pi->caps_stable_p_state) { in kv_update_acp_boot_level()
1391 if (acp_boot_level != pi->acp_boot_level) { in kv_update_acp_boot_level()
1392 pi->acp_boot_level = acp_boot_level; in kv_update_acp_boot_level()
1395 (1 << pi->acp_boot_level)); in kv_update_acp_boot_level()
1402 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_acp_dpm() local
1408 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1409 pi->acp_boot_level = table->count - 1; in kv_update_acp_dpm()
1411 pi->acp_boot_level = kv_get_acp_boot_level(rdev); in kv_update_acp_dpm()
1414 pi->dpm_table_start + in kv_update_acp_dpm()
1416 (u8 *)&pi->acp_boot_level, in kv_update_acp_dpm()
1418 pi->sram_end); in kv_update_acp_dpm()
1422 if (pi->caps_stable_p_state) in kv_update_acp_dpm()
1425 (1 << pi->acp_boot_level)); in kv_update_acp_dpm()
1433 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_uvd() local
1435 if (pi->uvd_power_gated == gate) in kv_dpm_powergate_uvd()
1438 pi->uvd_power_gated = gate; in kv_dpm_powergate_uvd()
1441 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1446 if (pi->caps_uvd_pg) in kv_dpm_powergate_uvd()
1449 if (pi->caps_uvd_pg) { in kv_dpm_powergate_uvd()
1461 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_vce() local
1463 if (pi->vce_power_gated == gate) in kv_dpm_powergate_vce()
1466 pi->vce_power_gated = gate; in kv_dpm_powergate_vce()
1469 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1474 if (pi->caps_vce_pg) { in kv_dpm_powergate_vce()
1484 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_samu() local
1486 if (pi->samu_power_gated == gate) in kv_dpm_powergate_samu()
1489 pi->samu_power_gated = gate; in kv_dpm_powergate_samu()
1493 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1496 if (pi->caps_samu_pg) in kv_dpm_powergate_samu()
1504 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_powergate_acp() local
1506 if (pi->acp_power_gated == gate) in kv_dpm_powergate_acp()
1512 pi->acp_power_gated = gate; in kv_dpm_powergate_acp()
1516 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1519 if (pi->caps_acp_pg) in kv_dpm_powergate_acp()
1529 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_valid_clock_range() local
1535 for (i = 0; i < pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1537 (i == (pi->graphics_dpm_level_count - 1))) { in kv_set_valid_clock_range()
1538 pi->lowest_valid = i; in kv_set_valid_clock_range()
1543 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1547 pi->highest_valid = i; in kv_set_valid_clock_range()
1549 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1550 if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) > in kv_set_valid_clock_range()
1551 (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk)) in kv_set_valid_clock_range()
1552 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1554 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1558 &pi->sys_info.sclk_voltage_mapping_table; in kv_set_valid_clock_range()
1560 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) { in kv_set_valid_clock_range()
1562 i == (int)(pi->graphics_dpm_level_count - 1)) { in kv_set_valid_clock_range()
1563 pi->lowest_valid = i; in kv_set_valid_clock_range()
1568 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) { in kv_set_valid_clock_range()
1573 pi->highest_valid = i; in kv_set_valid_clock_range()
1575 if (pi->lowest_valid > pi->highest_valid) { in kv_set_valid_clock_range()
1577 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1578 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
1580 pi->highest_valid = pi->lowest_valid; in kv_set_valid_clock_range()
1582 pi->lowest_valid = pi->highest_valid; in kv_set_valid_clock_range()
1591 struct kv_power_info *pi = kv_get_pi(rdev); in kv_update_dfs_bypass_settings() local
1595 if (pi->caps_enable_dfs_bypass) { in kv_update_dfs_bypass_settings()
1597 pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0; in kv_update_dfs_bypass_settings()
1599 (pi->dpm_table_start + in kv_update_dfs_bypass_settings()
1601 (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) + in kv_update_dfs_bypass_settings()
1604 sizeof(u8), pi->sram_end); in kv_update_dfs_bypass_settings()
1613 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_nb_dpm() local
1617 if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1620 pi->nb_dpm_enabled = true; in kv_enable_nb_dpm()
1623 if (pi->enable_nb_dpm && pi->nb_dpm_enabled) { in kv_enable_nb_dpm()
1626 pi->nb_dpm_enabled = false; in kv_enable_nb_dpm()
1659 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_pre_set_power_state() local
1666 &pi->requested_rps, in kv_dpm_pre_set_power_state()
1667 &pi->current_rps); in kv_dpm_pre_set_power_state()
1674 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_set_power_state() local
1675 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_set_power_state()
1676 struct radeon_ps *old_ps = &pi->current_rps; in kv_dpm_set_power_state()
1679 if (pi->bapm_enable) { in kv_dpm_set_power_state()
1688 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1717 if (pi->enable_dpm) { in kv_dpm_set_power_state()
1748 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_post_set_power_state() local
1749 struct radeon_ps *new_ps = &pi->requested_rps; in kv_dpm_post_set_power_state()
1766 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_max_power_limits_table() local
1768 if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) { in kv_construct_max_power_limits_table()
1769 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1; in kv_construct_max_power_limits_table()
1771 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
1774 pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit); in kv_construct_max_power_limits_table()
1777 table->mclk = pi->sys_info.nbp_memory_clock[0]; in kv_construct_max_power_limits_table()
1824 struct kv_power_info *pi = kv_get_pi(rdev); in kv_construct_boot_state() local
1826 pi->boot_pl.sclk = pi->sys_info.bootup_sclk; in kv_construct_boot_state()
1827 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; in kv_construct_boot_state()
1828 pi->boot_pl.ds_divider_index = 0; in kv_construct_boot_state()
1829 pi->boot_pl.ss_divider_index = 0; in kv_construct_boot_state()
1830 pi->boot_pl.allow_gnb_slow = 1; in kv_construct_boot_state()
1831 pi->boot_pl.force_nbp_state = 0; in kv_construct_boot_state()
1832 pi->boot_pl.display_wm = 0; in kv_construct_boot_state()
1833 pi->boot_pl.vce_wm = 0; in kv_construct_boot_state()
1879 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_sleep_divider_id_from_clock() local
1888 if (!pi->caps_sclk_ds) in kv_get_sleep_divider_id_from_clock()
1902 struct kv_power_info *pi = kv_get_pi(rdev); in kv_get_high_voltage_limit() local
1909 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
1911 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
1918 &pi->sys_info.sclk_voltage_mapping_table; in kv_get_high_voltage_limit()
1921 if (pi->high_voltage_t && in kv_get_high_voltage_limit()
1923 pi->high_voltage_t)) { in kv_get_high_voltage_limit()
1939 struct kv_power_info *pi = kv_get_pi(rdev); in kv_apply_state_adjust_rules() local
1961 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
1991 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
1992 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2000 &pi->sys_info.sclk_voltage_mapping_table; in kv_apply_state_adjust_rules()
2003 if (pi->high_voltage_t && in kv_apply_state_adjust_rules()
2004 (pi->high_voltage_t < in kv_apply_state_adjust_rules()
2012 if (pi->caps_stable_p_state) { in kv_apply_state_adjust_rules()
2018 pi->video_start = new_rps->dclk || new_rps->vclk || in kv_apply_state_adjust_rules()
2023 pi->battery_state = true; in kv_apply_state_adjust_rules()
2025 pi->battery_state = false; in kv_apply_state_adjust_rules()
2038 if (pi->sys_info.nb_dpm_enable) { in kv_apply_state_adjust_rules()
2039 force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_apply_state_adjust_rules()
2040 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) || in kv_apply_state_adjust_rules()
2041 pi->disable_nb_ps3_in_battery; in kv_apply_state_adjust_rules()
2053 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_power_level_enabled_for_throttle() local
2055 pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0; in kv_dpm_power_level_enabled_for_throttle()
2060 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_ds_divider() local
2064 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_ds_divider()
2067 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_ds_divider()
2068 pi->graphics_level[i].DeepSleepDivId = in kv_calculate_ds_divider()
2070 be32_to_cpu(pi->graphics_level[i].SclkFrequency), in kv_calculate_ds_divider()
2078 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_nbps_level_settings() local
2085 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_nbps_level_settings()
2089 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2090 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2091 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2092 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2095 if (!pi->sys_info.nb_dpm_enable) in kv_calculate_nbps_level_settings()
2098 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) || in kv_calculate_nbps_level_settings()
2099 (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start); in kv_calculate_nbps_level_settings()
2102 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_nbps_level_settings()
2103 pi->graphics_level[i].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2105 if (pi->battery_state) in kv_calculate_nbps_level_settings()
2106 pi->graphics_level[0].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2108 pi->graphics_level[1].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2109 pi->graphics_level[2].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2110 pi->graphics_level[3].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2111 pi->graphics_level[4].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2114 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) { in kv_calculate_nbps_level_settings()
2115 pi->graphics_level[i].GnbSlow = 1; in kv_calculate_nbps_level_settings()
2116 pi->graphics_level[i].ForceNbPs1 = 0; in kv_calculate_nbps_level_settings()
2117 pi->graphics_level[i].UpH = 0; in kv_calculate_nbps_level_settings()
2120 if (pi->sys_info.nb_dpm_enable && pi->battery_state) { in kv_calculate_nbps_level_settings()
2121 pi->graphics_level[pi->lowest_valid].UpH = 0x28; in kv_calculate_nbps_level_settings()
2122 pi->graphics_level[pi->lowest_valid].GnbSlow = 0; in kv_calculate_nbps_level_settings()
2123 if (pi->lowest_valid != pi->highest_valid) in kv_calculate_nbps_level_settings()
2124 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1; in kv_calculate_nbps_level_settings()
2132 struct kv_power_info *pi = kv_get_pi(rdev); in kv_calculate_dpm_settings() local
2135 if (pi->lowest_valid > pi->highest_valid) in kv_calculate_dpm_settings()
2138 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_calculate_dpm_settings()
2139 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0; in kv_calculate_dpm_settings()
2146 struct kv_power_info *pi = kv_get_pi(rdev); in kv_init_graphics_levels() local
2154 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2156 if (pi->high_voltage_t && in kv_init_graphics_levels()
2157 (pi->high_voltage_t < in kv_init_graphics_levels()
2163 &pi->sys_info.vid_mapping_table, in kv_init_graphics_levels()
2166 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2168 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2172 &pi->sys_info.sclk_voltage_mapping_table; in kv_init_graphics_levels()
2174 pi->graphics_dpm_level_count = 0; in kv_init_graphics_levels()
2176 if (pi->high_voltage_t && in kv_init_graphics_levels()
2177 pi->high_voltage_t < in kv_init_graphics_levels()
2183 kv_set_at(rdev, i, pi->at[i]); in kv_init_graphics_levels()
2185 pi->graphics_dpm_level_count++; in kv_init_graphics_levels()
2195 struct kv_power_info *pi = kv_get_pi(rdev); in kv_enable_new_levels() local
2199 if (i >= pi->lowest_valid && i <= pi->highest_valid) in kv_enable_new_levels()
2215 struct kv_power_info *pi = kv_get_pi(rdev); in kv_set_enabled_levels() local
2218 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) in kv_set_enabled_levels()
2230 struct kv_power_info *pi = kv_get_pi(rdev); in kv_program_nbps_index_settings() local
2236 if (pi->sys_info.nb_dpm_enable) { in kv_program_nbps_index_settings()
2287 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_sys_info_table() local
2304 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock); in kv_parse_sys_info_table()
2305 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock); in kv_parse_sys_info_table()
2306 pi->sys_info.bootup_nb_voltage_index = in kv_parse_sys_info_table()
2309 pi->sys_info.htc_tmp_lmt = 203; in kv_parse_sys_info_table()
2311 pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt; in kv_parse_sys_info_table()
2313 pi->sys_info.htc_hyst_lmt = 5; in kv_parse_sys_info_table()
2315 pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt; in kv_parse_sys_info_table()
2316 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { in kv_parse_sys_info_table()
2321 pi->sys_info.nb_dpm_enable = true; in kv_parse_sys_info_table()
2323 pi->sys_info.nb_dpm_enable = false; in kv_parse_sys_info_table()
2326 pi->sys_info.nbp_memory_clock[i] = in kv_parse_sys_info_table()
2328 pi->sys_info.nbp_n_clock[i] = in kv_parse_sys_info_table()
2333 pi->caps_enable_dfs_bypass = true; in kv_parse_sys_info_table()
2336 &pi->sys_info.sclk_voltage_mapping_table, in kv_parse_sys_info_table()
2340 &pi->sys_info.vid_mapping_table, in kv_parse_sys_info_table()
2373 struct kv_power_info *pi = kv_get_pi(rdev); in kv_patch_boot_state() local
2376 ps->levels[0] = pi->boot_pl; in kv_patch_boot_state()
2410 struct kv_power_info *pi = kv_get_pi(rdev); in kv_parse_pplib_clock_info() local
2422 if (pi->caps_sclk_ds) { in kv_parse_pplib_clock_info()
2520 struct kv_power_info *pi; in kv_dpm_init() local
2523 pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL); in kv_dpm_init()
2524 if (pi == NULL) in kv_dpm_init()
2526 rdev->pm.dpm.priv = pi; in kv_dpm_init()
2537 pi->at[i] = TRINITY_AT_DFLT; in kv_dpm_init()
2539 pi->sram_end = SMC_RAM_END; in kv_dpm_init()
2543 pi->enable_nb_dpm = false; in kv_dpm_init()
2545 pi->enable_nb_dpm = true; in kv_dpm_init()
2547 pi->caps_power_containment = true; in kv_dpm_init()
2548 pi->caps_cac = true; in kv_dpm_init()
2549 pi->enable_didt = false; in kv_dpm_init()
2550 if (pi->enable_didt) { in kv_dpm_init()
2551 pi->caps_sq_ramping = true; in kv_dpm_init()
2552 pi->caps_db_ramping = true; in kv_dpm_init()
2553 pi->caps_td_ramping = true; in kv_dpm_init()
2554 pi->caps_tcp_ramping = true; in kv_dpm_init()
2557 pi->caps_sclk_ds = true; in kv_dpm_init()
2558 pi->enable_auto_thermal_throttling = true; in kv_dpm_init()
2559 pi->disable_nb_ps3_in_battery = false; in kv_dpm_init()
2563 pi->bapm_enable = true; in kv_dpm_init()
2565 pi->bapm_enable = false; in kv_dpm_init()
2567 pi->bapm_enable = false; in kv_dpm_init()
2569 pi->bapm_enable = true; in kv_dpm_init()
2571 pi->voltage_drop_t = 0; in kv_dpm_init()
2572 pi->caps_sclk_throttle_low_notification = false; in kv_dpm_init()
2573 pi->caps_fps = false; /* true? */ in kv_dpm_init()
2574 pi->caps_uvd_pg = true; in kv_dpm_init()
2575 pi->caps_uvd_dpm = true; in kv_dpm_init()
2576 pi->caps_vce_pg = false; /* XXX true */ in kv_dpm_init()
2577 pi->caps_samu_pg = false; in kv_dpm_init()
2578 pi->caps_acp_pg = false; in kv_dpm_init()
2579 pi->caps_stable_p_state = false; in kv_dpm_init()
2592 pi->enable_dpm = true; in kv_dpm_init()
2600 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_debugfs_print_current_performance_level() local
2610 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_debugfs_print_current_performance_level()
2614 seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2615 seq_printf(m, "vce %sabled\n", pi->vce_power_gated ? "dis" : "en"); in kv_dpm_debugfs_print_current_performance_level()
2623 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_sclk() local
2632 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency); in kv_dpm_get_current_sclk()
2639 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_current_mclk() local
2641 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_current_mclk()
2681 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_sclk() local
2682 struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps); in kv_dpm_get_sclk()
2692 struct kv_power_info *pi = kv_get_pi(rdev); in kv_dpm_get_mclk() local
2694 return pi->sys_info.bootup_uma_clk; in kv_dpm_get_mclk()