46 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));  in evergreen_dma_fence_ring_emit()
47 	radeon_ring_write(ring, addr & 0xfffffffc);  in evergreen_dma_fence_ring_emit()
48 	radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));  in evergreen_dma_fence_ring_emit()
49 	radeon_ring_write(ring, fence->seq);  in evergreen_dma_fence_ring_emit()
51 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));  in evergreen_dma_fence_ring_emit()
53 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));  in evergreen_dma_fence_ring_emit()
54 	radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));  in evergreen_dma_fence_ring_emit()
55 	radeon_ring_write(ring, 1);  in evergreen_dma_fence_ring_emit()
76 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));  in evergreen_dma_ring_ib_execute()
77 		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);  in evergreen_dma_ring_ib_execute()
78 		radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);  in evergreen_dma_ring_ib_execute()
79 		radeon_ring_write(ring, next_rptr);  in evergreen_dma_ring_ib_execute()
86 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));  in evergreen_dma_ring_ib_execute()
87 	radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));  in evergreen_dma_ring_ib_execute()
88 	radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));  in evergreen_dma_ring_ib_execute()
89 	radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));  in evergreen_dma_ring_ib_execute()
139 		radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));  in evergreen_copy_dma()
140 		radeon_ring_write(ring, dst_offset & 0xfffffffc);  in evergreen_copy_dma()
141 		radeon_ring_write(ring, src_offset & 0xfffffffc);  in evergreen_copy_dma()
142 		radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);  in evergreen_copy_dma()
143 		radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);  in evergreen_copy_dma()