2895 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2960 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
2961 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2964 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
2966 						      src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
2985 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2986 					src_offset <<= 8;  in evergreen_dma_cs_parse()
2995 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
2996 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3004 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3006 						      src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3019 				src_offset = radeon_get_ib_value(p, idx+2);  in evergreen_dma_cs_parse()
3020 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3023 				if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3025 						      src_offset + count, radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3065 				src_offset = radeon_get_ib_value(p, idx+3);  in evergreen_dma_cs_parse()
3066 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3067 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3069 						      src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3105 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3106 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3107 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3109 						      src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3167 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3168 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3169 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3171 						      src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3196 					src_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3197 					src_offset <<= 8;  in evergreen_dma_cs_parse()
3206 					src_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3207 					src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3215 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3217 						      src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()
3254 				src_offset = radeon_get_ib_value(p, idx+8);  in evergreen_dma_cs_parse()
3255 				src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3256 				if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {  in evergreen_dma_cs_parse()
3258 						      src_offset + (count * 4), radeon_bo_size(src_reloc->robj));  in evergreen_dma_cs_parse()