Lines Matching refs:idx
757 unsigned idx) in evergreen_cs_track_validate_texture() argument
765 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
766 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
767 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
768 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
769 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
770 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
771 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
772 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1051 unsigned idx, unsigned reg) in evergreen_packet0_check() argument
1060 idx, reg); in evergreen_packet0_check()
1065 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx); in evergreen_packet0_check()
1075 unsigned idx; in evergreen_cs_parse_packet0() local
1078 idx = pkt->idx + 1; in evergreen_cs_parse_packet0()
1080 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { in evergreen_cs_parse_packet0()
1081 r = evergreen_packet0_check(p, pkt, idx, reg); in evergreen_cs_parse_packet0()
1095 static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_cs_handle_reg() argument
1150 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1153 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1171 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1179 ib[idx] &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_handle_reg()
1181 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1189 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1190 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1199 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1203 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1207 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1211 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1221 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1222 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1233 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1234 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1245 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1246 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1257 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1258 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1263 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1267 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1281 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1282 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1292 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_handle_reg()
1302 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1305 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1309 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1318 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1327 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; in evergreen_cs_handle_reg()
1339 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1347 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1359 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1367 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1377 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1385 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_handle_reg()
1399 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1407 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1419 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1420 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1428 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1429 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_handle_reg()
1453 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1454 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1461 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1481 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_handle_reg()
1482 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_handle_reg()
1489 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_handle_reg()
1506 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1523 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1535 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1546 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1563 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1564 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1579 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1580 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1591 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1592 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1598 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_handle_reg()
1600 ib[idx] |= 3; in evergreen_cs_handle_reg()
1709 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1723 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1737 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1740 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_handle_reg()
1743 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_handle_reg()
1779 unsigned idx; in evergreen_packet3_check() local
1787 idx = pkt->idx + 1; in evergreen_packet3_check()
1788 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1802 tmp = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
1824 ib[idx + 0] = offset; in evergreen_packet3_check()
1825 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1868 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1870 ib[idx+0] = offset; in evergreen_packet3_check()
1871 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1903 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1905 ib[idx+0] = offset; in evergreen_packet3_check()
1906 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1930 radeon_get_ib_value(p, idx+1) + in evergreen_packet3_check()
1931 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
1933 ib[idx+1] = offset; in evergreen_packet3_check()
1934 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1950 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1961 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2026 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2027 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2066 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2080 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2103 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2104 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2106 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); in evergreen_packet3_check()
2107 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2121 command = radeon_get_ib_value(p, idx+4); in evergreen_packet3_check()
2123 info = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2156 tmp = radeon_get_ib_value(p, idx) + in evergreen_packet3_check()
2157 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2167 ib[idx] = offset; in evergreen_packet3_check()
2168 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2194 tmp = radeon_get_ib_value(p, idx+2) + in evergreen_packet3_check()
2195 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in evergreen_packet3_check()
2205 ib[idx+2] = offset; in evergreen_packet3_check()
2206 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2226 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in evergreen_packet3_check()
2227 radeon_get_ib_value(p, idx + 2) != 0) { in evergreen_packet3_check()
2233 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2250 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in evergreen_packet3_check()
2251 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2253 ib[idx+1] = offset & 0xfffffff8; in evergreen_packet3_check()
2254 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2272 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2273 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2275 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2276 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2294 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2295 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2297 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2298 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2310 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { in evergreen_packet3_check()
2313 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2327 for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { in evergreen_packet3_check()
2330 r = evergreen_cs_handle_reg(p, reg, idx); in evergreen_packet3_check()
2353 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2362 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2370 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2371 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2382 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2383 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2402 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()
2405 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2406 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2417 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2418 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2422 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2426 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2427 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2499 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2500 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2507 ib[idx+1] = offset; in evergreen_packet3_check()
2508 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2518 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2519 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2526 ib[idx+3] = offset; in evergreen_packet3_check()
2527 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2543 offset = radeon_get_ib_value(p, idx+0); in evergreen_packet3_check()
2544 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in evergreen_packet3_check()
2555 ib[idx+0] = offset; in evergreen_packet3_check()
2556 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2572 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2573 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2580 ib[idx+1] = offset; in evergreen_packet3_check()
2581 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2584 reg = radeon_get_ib_value(p, idx+1) << 2; in evergreen_packet3_check()
2587 reg, idx + 1); in evergreen_packet3_check()
2599 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2600 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2607 ib[idx+3] = offset; in evergreen_packet3_check()
2608 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2611 reg = radeon_get_ib_value(p, idx+3) << 2; in evergreen_packet3_check()
2614 reg, idx + 3); in evergreen_packet3_check()
2636 areg, idx); in evergreen_packet3_check()
2649 offset = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
2653 offset += ((u64)(radeon_get_ib_value(p, idx + 2) & 0xff)) << 32; in evergreen_packet3_check()
2656 ib[idx+1] = (offset & 0xfffffffc) | swap; in evergreen_packet3_check()
2657 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2750 r = radeon_cs_packet_parse(p, &pkt, p->idx); in evergreen_cs_parse()
2756 p->idx += pkt.count + 2; in evergreen_cs_parse()
2777 } while (p->idx < p->chunk_ib->length_dw); in evergreen_cs_parse()
2804 u32 idx; in evergreen_dma_cs_parse() local
2809 if (p->idx >= ib_chunk->length_dw) { in evergreen_dma_cs_parse()
2811 p->idx, ib_chunk->length_dw); in evergreen_dma_cs_parse()
2814 idx = p->idx; in evergreen_dma_cs_parse()
2815 header = radeon_get_ib_value(p, idx); in evergreen_dma_cs_parse()
2830 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2833 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2834 p->idx += count + 7; in evergreen_dma_cs_parse()
2838 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2839 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2841 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2842 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2843 p->idx += count + 3; in evergreen_dma_cs_parse()
2846 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); in evergreen_dma_cs_parse()
2870 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2871 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2872 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2873 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2884 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2885 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2886 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2887 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2888 p->idx += 5; in evergreen_dma_cs_parse()
2893 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2895 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2897 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2899 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2900 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2901 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2902 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2905 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2906 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2907 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2908 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2910 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2912 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2924 p->idx += 9; in evergreen_dma_cs_parse()
2929 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2930 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2931 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2932 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2943 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2944 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2945 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2946 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2947 p->idx += 5; in evergreen_dma_cs_parse()
2956 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2957 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2958 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2959 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2961 p->idx += 9; in evergreen_dma_cs_parse()
2971 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2972 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2973 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2974 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2975 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2976 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2992 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2993 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2994 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2995 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2996 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2997 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2998 p->idx += 7; in evergreen_dma_cs_parse()
3002 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3011 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3013 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3015 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3016 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3032 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3033 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3034 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3035 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3036 p->idx += 10; in evergreen_dma_cs_parse()
3046 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3048 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3050 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3051 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3054 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3055 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3057 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3059 p->idx += 12; in evergreen_dma_cs_parse()
3064 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3073 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3075 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3077 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3078 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3094 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3095 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3096 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3097 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3098 p->idx += 10; in evergreen_dma_cs_parse()
3104 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3106 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3108 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3110 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3111 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3112 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3113 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3116 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3117 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3118 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3119 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3121 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3123 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3135 p->idx += 9; in evergreen_dma_cs_parse()
3144 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3145 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3146 p->idx += 13; in evergreen_dma_cs_parse()
3151 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3160 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3162 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3164 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3165 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3181 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3182 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3183 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3184 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3185 p->idx += 10; in evergreen_dma_cs_parse()
3188 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); in evergreen_dma_cs_parse()
3198 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3199 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3205 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3206 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()
3207 p->idx += 4; in evergreen_dma_cs_parse()
3210 p->idx += 1; in evergreen_dma_cs_parse()
3213 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_cs_parse()
3216 } while (p->idx < p->chunk_ib->length_dw); in evergreen_dma_cs_parse()
3352 u32 idx = pkt->idx + 1; in evergreen_vm_packet3_check() local
3353 u32 idx_value = ib[idx]; in evergreen_vm_packet3_check()
3410 reg = ib[idx + 5] * 4; in evergreen_vm_packet3_check()
3417 reg = ib[idx + 3] * 4; in evergreen_vm_packet3_check()
3438 command = ib[idx + 4]; in evergreen_vm_packet3_check()
3439 info = ib[idx + 1]; in evergreen_vm_packet3_check()
3476 start_reg = ib[idx + 2]; in evergreen_vm_packet3_check()
3511 areg, idx); in evergreen_vm_packet3_check()
3525 u32 idx = 0; in evergreen_ib_parse() local
3529 pkt.idx = idx; in evergreen_ib_parse()
3530 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in evergreen_ib_parse()
3531 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in evergreen_ib_parse()
3539 idx += 1; in evergreen_ib_parse()
3542 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in evergreen_ib_parse()
3544 idx += pkt.count + 2; in evergreen_ib_parse()
3553 } while (idx < ib->length_dw); in evergreen_ib_parse()
3569 u32 idx = 0; in evergreen_dma_ib_parse() local
3573 header = ib->ptr[idx]; in evergreen_dma_ib_parse()
3583 idx += count + 7; in evergreen_dma_ib_parse()
3587 idx += count + 3; in evergreen_dma_ib_parse()
3590 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3598 idx += 5; in evergreen_dma_ib_parse()
3602 idx += 9; in evergreen_dma_ib_parse()
3606 idx += 5; in evergreen_dma_ib_parse()
3610 idx += 9; in evergreen_dma_ib_parse()
3614 idx += 7; in evergreen_dma_ib_parse()
3618 idx += 10; in evergreen_dma_ib_parse()
3622 idx += 12; in evergreen_dma_ib_parse()
3626 idx += 10; in evergreen_dma_ib_parse()
3630 idx += 9; in evergreen_dma_ib_parse()
3634 idx += 13; in evergreen_dma_ib_parse()
3638 idx += 10; in evergreen_dma_ib_parse()
3641 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3646 idx += 4; in evergreen_dma_ib_parse()
3649 idx += 1; in evergreen_dma_ib_parse()
3652 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_ib_parse()
3655 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()