Lines Matching +full:8 +full:dev
52 struct radeon_bo *cb_color_fmask_bo[8]; /* unused */
53 struct radeon_bo *cb_color_cmask_bo[8]; /* unused */
60 u32 cb_color_cmask_slice[8];/* unused */
61 u32 cb_color_fmask_slice[8];/* unused */
111 case 8: in evergreen_cs_get_num_banks()
123 for (i = 0; i < 8; i++) { in evergreen_cs_track_init()
216 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", in evergreen_surface_check_linear_aligned()
231 palign = track->group_size / (8 * surf->bpe * surf->nsamples); in evergreen_surface_check_1d()
232 palign = MAX(8, palign); in evergreen_surface_check_1d()
236 surf->halign = 8; in evergreen_surface_check_1d()
239 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", in evergreen_surface_check_1d()
245 if ((surf->nby & (8 - 1))) { in evergreen_surface_check_1d()
247 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", in evergreen_surface_check_1d()
270 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
271 halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea; in evergreen_surface_check_2d()
272 mtileb = (palign / 8) * (halign / 8) * tileb; in evergreen_surface_check_2d()
276 surf->base_align = (palign / 8) * (halign / 8) * tileb; in evergreen_surface_check_2d()
282 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", in evergreen_surface_check_2d()
289 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", in evergreen_surface_check_2d()
316 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", in evergreen_surface_check()
336 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", in evergreen_surface_value_conv_check()
344 case 2: surf->nbanks = 8; break; in evergreen_surface_value_conv_check()
347 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", in evergreen_surface_value_conv_check()
355 case 3: surf->bankw = 8; break; in evergreen_surface_value_conv_check()
357 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", in evergreen_surface_value_conv_check()
365 case 3: surf->bankh = 8; break; in evergreen_surface_value_conv_check()
367 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n", in evergreen_surface_value_conv_check()
375 case 3: surf->mtilea = 8; break; in evergreen_surface_value_conv_check()
377 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n", in evergreen_surface_value_conv_check()
390 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n", in evergreen_surface_value_conv_check()
408 surf.nbx = (pitch + 1) * 8; in evergreen_cs_track_validate_cb()
420 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n", in evergreen_cs_track_validate_cb()
433 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_cb()
440 offset = (u64)track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
442 dev_warn(p->dev, "%s:%d cb[%d] bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_cb()
450 * program slice with ALIGN(h, 8), catch this and patch in evergreen_cs_track_validate_cb()
458 if (surf.nby > 8) { in evergreen_cs_track_validate_cb()
459 min = surf.nby - 8; in evergreen_cs_track_validate_cb()
462 tmp = (u64)track->cb_color_bo_offset[id] << 8; in evergreen_cs_track_validate_cb()
482 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " in evergreen_cs_track_validate_cb()
485 (u64)track->cb_color_bo_offset[id] << 8, mslice, in evergreen_cs_track_validate_cb()
487 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", in evergreen_cs_track_validate_cb()
506 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", in evergreen_cs_track_validate_htile()
512 /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */ in evergreen_cs_track_validate_htile()
513 nbx = round_up(nbx, 16 * 8); in evergreen_cs_track_validate_htile()
514 /* height is npipes htiles aligned == npipes * 8 pixel aligned */ in evergreen_cs_track_validate_htile()
515 nby = round_up(nby, track->npipes * 8); in evergreen_cs_track_validate_htile()
517 /* always assume 8x8 htile */ in evergreen_cs_track_validate_htile()
518 /* align is htile align * 8, htile align vary according to in evergreen_cs_track_validate_htile()
522 case 8: in evergreen_cs_track_validate_htile()
523 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ in evergreen_cs_track_validate_htile()
524 nbx = round_up(nbx, 64 * 8); in evergreen_cs_track_validate_htile()
525 nby = round_up(nby, 64 * 8); in evergreen_cs_track_validate_htile()
528 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ in evergreen_cs_track_validate_htile()
529 nbx = round_up(nbx, 64 * 8); in evergreen_cs_track_validate_htile()
530 nby = round_up(nby, 32 * 8); in evergreen_cs_track_validate_htile()
533 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ in evergreen_cs_track_validate_htile()
534 nbx = round_up(nbx, 32 * 8); in evergreen_cs_track_validate_htile()
535 nby = round_up(nby, 32 * 8); in evergreen_cs_track_validate_htile()
538 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ in evergreen_cs_track_validate_htile()
539 nbx = round_up(nbx, 32 * 8); in evergreen_cs_track_validate_htile()
540 nby = round_up(nby, 16 * 8); in evergreen_cs_track_validate_htile()
543 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", in evergreen_cs_track_validate_htile()
556 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", in evergreen_cs_track_validate_htile()
575 surf.nbx = (pitch + 1) * 8; in evergreen_cs_track_validate_stencil()
587 dev_warn(p->dev, "%s:%d stencil invalid format %d\n", in evergreen_cs_track_validate_stencil()
608 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_stencil()
615 offset = (u64)track->db_s_read_offset << 8; in evergreen_cs_track_validate_stencil()
617 dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_stencil()
623 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, " in evergreen_cs_track_validate_stencil()
626 (u64)track->db_s_read_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
628 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_stencil()
634 offset = (u64)track->db_s_write_offset << 8; in evergreen_cs_track_validate_stencil()
636 dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_stencil()
642 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, " in evergreen_cs_track_validate_stencil()
645 (u64)track->db_s_write_offset << 8, mslice, in evergreen_cs_track_validate_stencil()
672 surf.nbx = (pitch + 1) * 8; in evergreen_cs_track_validate_depth()
692 dev_warn(p->dev, "%s:%d depth invalid format %d\n", in evergreen_cs_track_validate_depth()
699 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_depth()
707 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_depth()
713 offset = (u64)track->db_z_read_offset << 8; in evergreen_cs_track_validate_depth()
715 dev_warn(p->dev, "%s:%d stencil read bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_depth()
721 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, " in evergreen_cs_track_validate_depth()
724 (u64)track->db_z_read_offset << 8, mslice, in evergreen_cs_track_validate_depth()
729 offset = (u64)track->db_z_write_offset << 8; in evergreen_cs_track_validate_depth()
731 dev_warn(p->dev, "%s:%d stencil write bo base %llu not aligned with %ld\n", in evergreen_cs_track_validate_depth()
737 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, " in evergreen_cs_track_validate_depth()
740 (u64)track->db_z_write_offset << 8, mslice, in evergreen_cs_track_validate_depth()
764 u32 texdw[8]; in evergreen_cs_track_validate_texture()
782 surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8; in evergreen_cs_track_validate_texture()
792 toffset = texdw[2] << 8; in evergreen_cs_track_validate_texture()
793 moffset = texdw[3] << 8; in evergreen_cs_track_validate_texture()
796 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in evergreen_cs_track_validate_texture()
817 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", in evergreen_cs_track_validate_texture()
833 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in evergreen_cs_track_validate_texture()
841 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
846 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
856 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
859 (unsigned long)texdw[2] << 8, mslice, in evergreen_cs_track_validate_texture()
867 dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n", in evergreen_cs_track_validate_texture()
898 dev_warn(p->dev, "%s:%d invalid array mode %d\n", in evergreen_cs_track_validate_texture()
916 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
920 (unsigned long)texdw[3] << 8, moffset, mslice, in evergreen_cs_track_validate_texture()
923 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", in evergreen_cs_track_validate_texture()
956 dev_warn_once(p->dev, "streamout %d bo too small: 0x%llx, 0x%lx\n", in evergreen_cs_track_check()
962 dev_warn_once(p->dev, "No buffer for streamout %d\n", i); in evergreen_cs_track_check()
977 for (i = 0; i < 8; i++) { in evergreen_cs_track_check()
984 dev_warn_once(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", in evergreen_cs_track_check()
1061 dev_warn_once(p->dev, "No reloc for ib[%d]=0x%04X\n", in evergreen_packet0_check()
1148 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1152 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1160 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1167 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1177 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1219 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1224 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1231 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1236 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1243 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1248 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1255 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1260 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1278 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1283 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_handle_reg()
1284 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1300 dev_warn_once(p->dev, "missing reloc for CP_COHER_BASE " in evergreen_cs_handle_reg()
1304 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1316 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1325 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1348 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8; in evergreen_cs_handle_reg()
1365 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1378 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; in evergreen_cs_handle_reg()
1383 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1408 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8; in evergreen_cs_handle_reg()
1429 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; in evergreen_cs_handle_reg()
1444 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1472 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1490 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8; in evergreen_cs_handle_reg()
1505 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in evergreen_cs_handle_reg()
1508 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1522 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in evergreen_cs_handle_reg()
1525 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1560 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1566 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1576 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1580 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; in evergreen_cs_handle_reg()
1582 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1589 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1594 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1599 /* 8x8 only */ in evergreen_cs_handle_reg()
1601 /* force 8x8 htile width and height */ in evergreen_cs_handle_reg()
1707 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1711 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1715 dev_warn_once(p->dev, "bad SET_CONFIG_REG " in evergreen_cs_handle_reg()
1721 dev_warn_once(p->dev, "bad SET_CONFIG_REG " in evergreen_cs_handle_reg()
1725 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1729 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1735 dev_warn_once(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_handle_reg()
1739 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_handle_reg()
1745 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_handle_reg()
1800 dev_warn_once(p->dev, "bad SET PREDICATION\n"); in evergreen_packet3_check()
1812 dev_warn_once(p->dev, "bad SET PREDICATION operation %d\n", pred_op); in evergreen_packet3_check()
1818 dev_warn_once(p->dev, "bad SET PREDICATION\n"); in evergreen_packet3_check()
1832 dev_warn_once(p->dev, "bad CONTEXT_CONTROL\n"); in evergreen_packet3_check()
1840 dev_warn_once(p->dev, "bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); in evergreen_packet3_check()
1846 dev_warn_once(p->dev, "bad PACKET3_DEALLOC_STATE\n"); in evergreen_packet3_check()
1850 dev_warn_once(p->dev, "bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n"); in evergreen_packet3_check()
1859 dev_warn_once(p->dev, "bad INDEX_BASE\n"); in evergreen_packet3_check()
1864 dev_warn_once(p->dev, "bad INDEX_BASE\n"); in evergreen_packet3_check()
1877 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1885 dev_warn_once(p->dev, "bad INDEX_BUFFER_SIZE\n"); in evergreen_packet3_check()
1894 dev_warn_once(p->dev, "bad DRAW_INDEX\n"); in evergreen_packet3_check()
1899 dev_warn_once(p->dev, "bad DRAW_INDEX\n"); in evergreen_packet3_check()
1912 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1922 dev_warn_once(p->dev, "bad DRAW_INDEX_2\n"); in evergreen_packet3_check()
1927 dev_warn_once(p->dev, "bad DRAW_INDEX_2\n"); in evergreen_packet3_check()
1940 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1947 dev_warn_once(p->dev, "bad DRAW_INDEX_AUTO\n"); in evergreen_packet3_check()
1952 dev_warn_once(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1958 dev_warn_once(p->dev, "bad DRAW_INDEX_MULTI_AUTO\n"); in evergreen_packet3_check()
1963 dev_warn_once(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1969 dev_warn_once(p->dev, "bad DRAW_INDEX_IMMD\n"); in evergreen_packet3_check()
1974 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1980 dev_warn_once(p->dev, "bad DRAW_INDEX_OFFSET\n"); in evergreen_packet3_check()
1985 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1991 dev_warn_once(p->dev, "bad DRAW_INDEX_OFFSET_2\n"); in evergreen_packet3_check()
1996 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2007 4 ADDRESS_HI Bits [31:8] - Reserved. Bits [7:0] - Upper bits of Address [47:32] in evergreen_packet3_check()
2010 dev_warn_once(p->dev, "bad SET_BASE\n"); in evergreen_packet3_check()
2016 dev_warn_once(p->dev, "bad SET_BASE\n"); in evergreen_packet3_check()
2022 dev_warn_once(p->dev, "bad SET_BASE\n"); in evergreen_packet3_check()
2044 dev_warn_once(p->dev, "bad DRAW_INDIRECT\n"); in evergreen_packet3_check()
2049 dev_warn_once(p->dev, "DRAW_INDIRECT buffer too small %u + %llu > %lu\n", in evergreen_packet3_check()
2056 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2063 dev_warn_once(p->dev, "bad DISPATCH_DIRECT\n"); in evergreen_packet3_check()
2068 dev_warn_once(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2074 dev_warn_once(p->dev, "bad DISPATCH_INDIRECT\n"); in evergreen_packet3_check()
2079 dev_warn_once(p->dev, "bad DISPATCH_INDIRECT\n"); in evergreen_packet3_check()
2085 dev_warn_once(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2091 dev_warn_once(p->dev, "bad WAIT_REG_MEM\n"); in evergreen_packet3_check()
2100 dev_warn_once(p->dev, "bad WAIT_REG_MEM\n"); in evergreen_packet3_check()
2111 dev_warn_once(p->dev, "cannot use PFP on REG wait\n"); in evergreen_packet3_check()
2120 dev_warn_once(p->dev, "bad CP DMA\n"); in evergreen_packet3_check()
2134 dev_warn_once(p->dev, "CP DMA command requires dw count alignment\n"); in evergreen_packet3_check()
2142 dev_warn_once(p->dev, "CP DMA SAS not supported\n"); in evergreen_packet3_check()
2147 dev_warn_once(p->dev, "CP DMA SAIC only supported for registers\n"); in evergreen_packet3_check()
2154 dev_warn_once(p->dev, "bad CP DMA SRC\n"); in evergreen_packet3_check()
2164 dev_warn_once(p->dev, "CP DMA src buffer too small (%llu %lu)\n", in evergreen_packet3_check()
2172 dev_warn_once(p->dev, "bad CP DMA SRC_SEL\n"); in evergreen_packet3_check()
2180 dev_warn_once(p->dev, "CP DMA DAS not supported\n"); in evergreen_packet3_check()
2186 dev_warn_once(p->dev, "CP DMA DAIC only supported for registers\n"); in evergreen_packet3_check()
2192 dev_warn_once(p->dev, "bad CP DMA DST\n"); in evergreen_packet3_check()
2202 dev_warn_once(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", in evergreen_packet3_check()
2210 dev_warn_once(p->dev, "bad CP DMA DST_SEL\n"); in evergreen_packet3_check()
2218 dev_warn_once(p->dev, "bad PFP_SYNC_ME\n"); in evergreen_packet3_check()
2224 dev_warn_once(p->dev, "bad SURFACE_SYNC\n"); in evergreen_packet3_check()
2232 dev_warn_once(p->dev, "bad SURFACE_SYNC\n"); in evergreen_packet3_check()
2235 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2240 dev_warn_once(p->dev, "bad EVENT_WRITE\n"); in evergreen_packet3_check()
2248 dev_warn_once(p->dev, "bad EVENT_WRITE\n"); in evergreen_packet3_check()
2264 dev_warn_once(p->dev, "bad EVENT_WRITE_EOP\n"); in evergreen_packet3_check()
2269 dev_warn_once(p->dev, "bad EVENT_WRITE_EOP\n"); in evergreen_packet3_check()
2286 dev_warn_once(p->dev, "bad EVENT_WRITE_EOS\n"); in evergreen_packet3_check()
2291 dev_warn_once(p->dev, "bad EVENT_WRITE_EOS\n"); in evergreen_packet3_check()
2309 dev_warn_once(p->dev, "bad PACKET3_SET_CONFIG_REG\n"); in evergreen_packet3_check()
2326 dev_warn_once(p->dev, "bad PACKET3_SET_CONTEXT_REG\n"); in evergreen_packet3_check()
2338 if (pkt->count % 8) { in evergreen_packet3_check()
2339 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in evergreen_packet3_check()
2347 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in evergreen_packet3_check()
2350 for (i = 0; i < (pkt->count / 8); i++) { in evergreen_packet3_check()
2355 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2360 dev_warn_once(p->dev, "bad SET_RESOURCE (tex)\n"); in evergreen_packet3_check()
2364 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2372 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2373 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2381 toffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2384 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2385 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2397 dev_warn_once(p->dev, "bad SET_RESOURCE (tex)\n"); in evergreen_packet3_check()
2400 moffset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2404 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()
2407 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2408 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2416 dev_warn_once(p->dev, "bad SET_RESOURCE (vtx)\n"); in evergreen_packet3_check()
2419 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2420 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2423 dev_warn_once(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", in evergreen_packet3_check()
2425 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2429 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2430 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2437 dev_warn_once(p->dev, "bad SET_RESOURCE\n"); in evergreen_packet3_check()
2451 dev_warn_once(p->dev, "bad SET_BOOL_CONST\n"); in evergreen_packet3_check()
2461 dev_warn_once(p->dev, "bad SET_LOOP_CONST\n"); in evergreen_packet3_check()
2471 dev_warn_once(p->dev, "bad SET_CTL_CONST\n"); in evergreen_packet3_check()
2477 dev_warn_once(p->dev, "bad SET_SAMPLER\n"); in evergreen_packet3_check()
2485 dev_warn_once(p->dev, "bad SET_SAMPLER\n"); in evergreen_packet3_check()
2491 dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (invalid count)\n"); in evergreen_packet3_check()
2499 dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); in evergreen_packet3_check()
2505 dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n", in evergreen_packet3_check()
2518 dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); in evergreen_packet3_check()
2524 dev_warn_once(p->dev, "bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n", in evergreen_packet3_check()
2538 dev_warn_once(p->dev, "bad MEM_WRITE (invalid count)\n"); in evergreen_packet3_check()
2543 dev_warn_once(p->dev, "bad MEM_WRITE (missing reloc)\n"); in evergreen_packet3_check()
2549 dev_warn_once(p->dev, "bad MEM_WRITE (address not qwords aligned)\n"); in evergreen_packet3_check()
2552 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2553 dev_warn_once(p->dev, "bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n", in evergreen_packet3_check()
2554 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2564 dev_warn_once(p->dev, "bad COPY_DW (invalid count)\n"); in evergreen_packet3_check()
2572 dev_warn_once(p->dev, "bad COPY_DW (missing src reloc)\n"); in evergreen_packet3_check()
2578 dev_warn_once(p->dev, "bad COPY_DW src bo too small: 0x%llx, 0x%lx\n", in evergreen_packet3_check()
2589 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", in evergreen_packet3_check()
2599 dev_warn_once(p->dev, "bad COPY_DW (missing dst reloc)\n"); in evergreen_packet3_check()
2605 dev_warn_once(p->dev, "bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n", in evergreen_packet3_check()
2616 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", in evergreen_packet3_check()
2628 dev_warn_once(p->dev, "bad SET_APPEND_CNT (invalid count)\n"); in evergreen_packet3_check()
2638 dev_warn_once(p->dev, "forbidden register for append cnt 0x%08x at %d\n", in evergreen_packet3_check()
2649 dev_warn_once(p->dev, "bad SET_APPEND_CNT (missing reloc)\n"); in evergreen_packet3_check()
2662 dev_warn_once(p->dev, "bad SET_APPEND_CNT (unsupported operation)\n"); in evergreen_packet3_check()
2672 dev_warn_once(p->dev, "bad COND_EXEC (invalid count)\n"); in evergreen_packet3_check()
2677 dev_warn_once(p->dev, "bad COND_EXEC (missing reloc)\n"); in evergreen_packet3_check()
2683 dev_warn_once(p->dev, "bad COND_EXEC (address not qwords aligned)\n"); in evergreen_packet3_check()
2686 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2687 dev_warn_once(p->dev, "bad COND_EXEC bo too small: 0x%llx, 0x%lx\n", in evergreen_packet3_check()
2688 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2698 dev_warn_once(p->dev, "bad COND_WRITE (invalid count)\n"); in evergreen_packet3_check()
2706 dev_warn_once(p->dev, "bad COND_WRITE (missing src reloc)\n"); in evergreen_packet3_check()
2711 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2712 dev_warn_once(p->dev, "bad COND_WRITE src bo too small: 0x%llx, 0x%lx\n", in evergreen_packet3_check()
2713 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2723 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", in evergreen_packet3_check()
2733 dev_warn_once(p->dev, "bad COND_WRITE (missing dst reloc)\n"); in evergreen_packet3_check()
2738 if ((offset + 8) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2739 dev_warn_once(p->dev, "bad COND_WRITE dst bo too small: 0x%llx, 0x%lx\n", in evergreen_packet3_check()
2740 offset + 8, radeon_bo_size(reloc->robj)); in evergreen_packet3_check()
2750 dev_warn_once(p->dev, "forbidden register 0x%08x at %d\n", in evergreen_packet3_check()
2759 dev_warn_once(p->dev, "Packet3 opcode %x not supported\n", pkt->opcode); in evergreen_packet3_check()
2799 track->npipes = 8; in evergreen_cs_parse()
2809 track->nbanks = 8; in evergreen_cs_parse()
2816 switch ((tmp & 0xf00) >> 8) { in evergreen_cs_parse()
2859 dev_warn_once(p->dev, "Unknown packet type %d !\n", pkt.type); in evergreen_cs_parse()
2902 dev_warn_once(p->dev, "Can not parse packet at %d after CS end %d !\n", in evergreen_dma_cs_parse()
2916 dev_warn_once(p->dev, "bad DMA_PACKET_WRITE\n"); in evergreen_dma_cs_parse()
2921 case 8: in evergreen_dma_cs_parse()
2923 dst_offset <<= 8; in evergreen_dma_cs_parse()
2925 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2938 dev_warn_once(p->dev, "bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); in evergreen_dma_cs_parse()
2942 dev_warn_once(p->dev, "DMA write buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2950 dev_warn_once(p->dev, "bad DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
2955 dev_warn_once(p->dev, "bad DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
2967 dev_warn_once(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2972 dev_warn_once(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2988 src_offset <<= 8; in evergreen_dma_cs_parse()
2989 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2992 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2994 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2998 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3000 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3003 dst_offset <<= 8; in evergreen_dma_cs_parse()
3004 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3007 dev_warn_once(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3012 dev_warn_once(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3026 dev_warn_once(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3031 dev_warn_once(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3045 dev_warn_once(p->dev, "L2L Partial is cayman only !\n"); in evergreen_dma_cs_parse()
3060 dev_warn_once(p->dev, "bad L2L, dw, broadcast DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
3070 dev_warn_once(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3075 dev_warn_once(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3080 dev_warn_once(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3095 dev_warn_once(p->dev, "bad L2T, frame to fields DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
3100 dev_warn_once(p->dev, "bad L2T, frame to fields DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
3104 dst_offset <<= 8; in evergreen_dma_cs_parse()
3106 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3107 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3110 dev_warn_once(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3115 dev_warn_once(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3120 dev_warn_once(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3124 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3125 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3126 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3134 dev_warn_once(p->dev, "L2T, T2L Partial is cayman only !\n"); in evergreen_dma_cs_parse()
3140 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3143 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3147 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3149 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3157 dev_warn_once(p->dev, "bad L2T, broadcast DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
3162 dev_warn_once(p->dev, "bad L2T, broadcast DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
3166 dst_offset <<= 8; in evergreen_dma_cs_parse()
3168 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3169 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3172 dev_warn_once(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3177 dev_warn_once(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3182 dev_warn_once(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3186 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3187 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3188 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3199 src_offset <<= 8; in evergreen_dma_cs_parse()
3200 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3203 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3205 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3209 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3211 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3214 dst_offset <<= 8; in evergreen_dma_cs_parse()
3215 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3218 dev_warn_once(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3223 dev_warn_once(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3233 dev_warn_once(p->dev, "L2T, T2L Partial is cayman only !\n"); in evergreen_dma_cs_parse()
3236 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3237 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3244 dev_warn_once(p->dev, "bad L2T, broadcast DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
3249 dev_warn_once(p->dev, "bad L2T, broadcast DMA_PACKET_COPY\n"); in evergreen_dma_cs_parse()
3253 dst_offset <<= 8; in evergreen_dma_cs_parse()
3255 dst2_offset <<= 8; in evergreen_dma_cs_parse()
3256 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3259 dev_warn_once(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3264 dev_warn_once(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3269 dev_warn_once(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3273 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3274 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3275 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3280 dev_warn_once(p->dev, "bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); in evergreen_dma_cs_parse()
3287 dev_warn_once(p->dev, "bad DMA_PACKET_CONSTANT_FILL\n"); in evergreen_dma_cs_parse()
3293 dev_warn_once(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3305 dev_warn_once(p->dev, "Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_cs_parse()
3454 dev_warn_once(rdev->dev, "bad SET_BASE"); in evergreen_vm_packet3_check()
3525 dev_warn_once(rdev->dev, "bad PACKET3_SET_CONFIG_REG\n"); in evergreen_vm_packet3_check()
3545 dev_warn_once(rdev->dev, "CP DMA command requires dw count alignment\n"); in evergreen_vm_packet3_check()
3556 dev_warn_once(rdev->dev, "CP DMA Bad SRC register\n"); in evergreen_vm_packet3_check()
3563 dev_warn_once(rdev->dev, "CP DMA Bad SRC register\n"); in evergreen_vm_packet3_check()
3577 dev_warn_once(rdev->dev, "CP DMA Bad DST register\n"); in evergreen_vm_packet3_check()
3584 dev_warn_once(rdev->dev, "CP DMA Bad DST register\n"); in evergreen_vm_packet3_check()
3597 dev_warn_once(rdev->dev, "bad SET_APPEND_CNT (invalid count)\n"); in evergreen_vm_packet3_check()
3607 dev_warn_once(rdev->dev, "forbidden register for append cnt 0x%08x at %d\n", in evergreen_vm_packet3_check()
3632 dev_err(rdev->dev, "Packet0 not allowed!\n"); in evergreen_ib_parse()
3644 dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type); in evergreen_ib_parse()
3679 case 8: in evergreen_dma_ib_parse()
3687 dev_warn_once(rdev->dev, in evergreen_dma_ib_parse()
3688 "bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", in evergreen_dma_ib_parse()
3740 dev_warn_once(rdev->dev, in evergreen_dma_ib_parse()
3753 dev_warn_once(rdev->dev, "Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_ib_parse()