Lines Matching +full:1 +full:x
35 # define DIDT_CTRL_EN (1 << 0)
42 # define SamuBootLevel(x) ((x) << 0) argument
45 # define AcpBootLevel(x) ((x) << 8) argument
48 # define VceBootLevel(x) ((x) << 16) argument
51 # define UvdBootLevel(x) ((x) << 24) argument
56 # define INTERRUPTS_ENABLED (1 << 0)
59 # define Dpm0PgNbPsLo(x) ((x) << 0) argument
62 # define Dpm0PgNbPsHi(x) ((x) << 8) argument
65 # define DpmXNbPsLo(x) ((x) << 16) argument
68 # define DpmXNbPsHi(x) ((x) << 24) argument
73 # define RST_REG (1 << 0)
75 # define CK_DISABLE (1 << 0)
76 # define CKEN (1 << 24)
87 # define BOOT_SEQ_DONE (1 << 7)
90 # define GLOBAL_PWRMGT_EN (1 << 0)
91 # define STATIC_PM_EN (1 << 1)
92 # define THERMAL_PROTECTION_DIS (1 << 2)
93 # define THERMAL_PROTECTION_TYPE (1 << 3)
94 # define SW_SMIO_INDEX(x) ((x) << 6) argument
95 # define SW_SMIO_INDEX_MASK (1 << 6)
97 # define VOLT_PWRMGT_EN (1 << 10)
98 # define GPU_COUNTER_CLK (1 << 15)
99 # define DYN_SPREAD_SPECTRUM_EN (1 << 23)
102 # define GNB_SLOW_MODE(x) ((x) << 0) argument
105 # define GNB_SLOW (1 << 2)
106 # define FORCE_NB_PS1 (1 << 3)
107 # define DPM_ENABLED (1 << 4)
110 # define SCLK_PWRMGT_OFF (1 << 0)
111 # define RESET_BUSY_CNT (1 << 4)
112 # define RESET_SCLK_CNT (1 << 5)
113 # define DYNAMIC_PM_EN (1 << 21)
124 # define SST(x) ((x) << 0) argument
126 # define SSTU(x) ((x) << 16) argument
130 # define DISP_GAP(x) ((x) << 0) argument
132 # define VBI_TIMER_COUNT(x) ((x) << 4) argument
134 # define VBI_TIMER_UNIT(x) ((x) << 20) argument
136 # define DISP_GAP_MCHG(x) ((x) << 24) argument
140 # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)
141 # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1
182 #define DPM_EVENT_SRC(x) ((x) << 0) argument
184 #define DIG_THERM_DPM(x) ((x) << 14) argument
188 #define FDO_PWM_DUTY(x) ((x) << 9) argument
192 #define CI_DIG_THERM_INTH(x) ((x) << 8) argument
195 #define CI_DIG_THERM_INTL(x) ((x) << 16) argument
198 #define THERM_INT_MASK_HIGH (1 << 24)
199 #define THERM_INT_MASK_LOW (1 << 25)
201 #define TEMP_SEL(x) ((x) << 20) argument
205 #define ASIC_MAX_TEMP(x) ((x) << 0) argument
208 #define CTF_TEMP(x) ((x) << 9) argument
213 #define FDO_STATIC_DUTY(x) ((x) << 0) argument
217 #define FMAX_DUTY100(x) ((x) << 0) argument
221 #define TMIN(x) ((x) << 0) argument
224 #define FDO_PWM_MODE(x) ((x) << 11) argument
227 #define TACH_PWM_RESP_RATE(x) ((x) << 25) argument
231 # define EDGE_PER_REV(x) ((x) << 0) argument
234 # define TARGET_PERIOD(x) ((x) << 3) argument
238 # define TACH_PERIOD(x) ((x) << 0) argument
244 # define ECLK_DIR_CNTL_EN (1 << 8)
246 # define ECLK_STATUS (1 << 0)
249 #define SPLL_RESET (1 << 0)
250 #define SPLL_PWRON (1 << 1)
251 #define SPLL_BYPASS_EN (1 << 3)
252 #define SPLL_REF_DIV(x) ((x) << 5) argument
254 #define SPLL_PDIV_A(x) ((x) << 20) argument
258 #define SCLK_MUX_SEL(x) ((x) << 0) argument
261 #define SPLL_FB_DIV(x) ((x) << 0) argument
264 #define SPLL_DITHEN (1 << 28)
268 #define SSEN (1 << 0)
269 #define CLK_S(x) ((x) << 4) argument
273 #define CLK_V(x) ((x) << 0) argument
278 # define MPLL_CLKOUT_SEL(x) ((x) << 8) argument
281 # define XTALIN_DIVIDE (1 << 1)
282 # define BCLK_AS_XCLK (1 << 2)
284 # define FORCE_BIF_REFCLK_EN (1 << 3)
285 # define MUX_TCLK_TO_XCLK (1 << 8)
287 # define CMON_CLK_SEL(x) ((x) << 0) argument
289 # define TMON_CLK_SEL(x) ((x) << 8) argument
292 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) argument
294 # define ZCLK_SEL(x) ((x) << 8) argument
299 #define DIG_THERM_INTH(x) ((x) << 0) argument
302 #define DIG_THERM_INTL(x) ((x) << 8) argument
305 #define THERM_INTH_MASK (1 << 24)
306 #define THERM_INTL_MASK (1 << 25)
310 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) argument
313 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) argument
316 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) argument
320 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) argument
323 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) argument
326 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) argument
331 # define SLV_MEM_LS_EN (1 << 16)
332 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
333 # define MST_MEM_LS_EN (1 << 18)
334 # define REPLAY_MEM_LS_EN (1 << 19)
337 # define LC_REVERSE_RCVR (1 << 0)
338 # define LC_REVERSE_XMIT (1 << 1)
345 # define P_IGNORE_EDB_ERR (1 << 6)
351 # define LC_L0S_INACTIVITY(x) ((x) << 8) argument
354 # define LC_L1_INACTIVITY(x) ((x) << 12) argument
357 # define LC_PMI_TO_L1_DIS (1 << 16)
358 # define LC_ASPM_TO_L1_DIS (1 << 24)
364 # define LC_LINK_WIDTH_X1 1
371 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
372 # define LC_RECONFIG_NOW (1 << 8)
373 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
374 # define LC_RENEGOTIATE_EN (1 << 10)
375 # define LC_SHORT_RECONFIG_EN (1 << 11)
376 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
377 # define LC_UPCONFIGURE_DIS (1 << 13)
378 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) argument
382 # define LC_XMIT_N_FTS(x) ((x) << 0) argument
385 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
388 # define LC_GEN2_EN_STRAP (1 << 0)
389 # define LC_GEN3_EN_STRAP (1 << 1)
390 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
393 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
394 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
395 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
396 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
397 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
400 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
402 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
403 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
404 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
405 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
406 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
409 # define LC_ALLOW_PDWN_IN_L1 (1 << 17)
410 # define LC_ALLOW_PDWN_IN_L23 (1 << 18)
413 # define LC_GO_TO_RECOVERY (1 << 30)
415 # define LC_REDO_EQ (1 << 5)
416 # define LC_SET_QUIESCE (1 << 13)
426 #define AUTO_INCREMENT_IND_0 (1 << 0)
436 #define VGA_MEMORY_DISABLE (1 << 4)
441 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) argument
442 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
445 #define PIPEID(x) ((x) << 0) argument
446 #define MEID(x) ((x) << 2) argument
447 #define VMID(x) ((x) << 4) argument
448 #define QUEUEID(x) ((x) << 8) argument
451 #define SDMA_BUSY (1 << 5)
452 #define SDMA1_BUSY (1 << 6)
454 #define UVD_RQ_PENDING (1 << 1)
455 #define GRBM_RQ_PENDING (1 << 5)
456 #define VMC_BUSY (1 << 8)
457 #define MCB_BUSY (1 << 9)
458 #define MCB_NON_DISPLAY_BUSY (1 << 10)
459 #define MCC_BUSY (1 << 11)
460 #define MCD_BUSY (1 << 12)
461 #define SEM_BUSY (1 << 14)
462 #define IH_BUSY (1 << 17)
463 #define UVD_BUSY (1 << 19)
466 #define SOFT_RESET_BIF (1 << 1)
467 #define SOFT_RESET_R0PLL (1 << 4)
468 #define SOFT_RESET_DC (1 << 5)
469 #define SOFT_RESET_SDMA1 (1 << 6)
470 #define SOFT_RESET_GRBM (1 << 8)
471 #define SOFT_RESET_HDP (1 << 9)
472 #define SOFT_RESET_IH (1 << 10)
473 #define SOFT_RESET_MC (1 << 11)
474 #define SOFT_RESET_ROM (1 << 14)
475 #define SOFT_RESET_SEM (1 << 15)
476 #define SOFT_RESET_VMC (1 << 17)
477 #define SOFT_RESET_SDMA (1 << 20)
478 #define SOFT_RESET_TST (1 << 21)
479 #define SOFT_RESET_REGBB (1 << 22)
480 #define SOFT_RESET_ORB (1 << 23)
481 #define SOFT_RESET_VCE (1 << 24)
488 #define ENABLE_L2_CACHE (1 << 0)
489 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
490 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) argument
491 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) argument
492 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
493 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
494 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) argument
495 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) argument
497 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
498 #define INVALIDATE_L2_CACHE (1 << 1)
499 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) argument
501 #define INVALIDATE_ONLY_PTE_CACHES 1
504 #define BANK_SELECT(x) ((x) << 0) argument
505 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) argument
506 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) argument
507 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
509 #define L2_BUSY (1 << 0)
511 #define ENABLE_CONTEXT (1 << 0)
512 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) argument
513 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
514 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
515 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
516 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
517 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
518 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
519 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
520 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
521 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
522 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
523 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
524 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
525 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) argument
545 * bit 1: pde0
553 #define MEMORY_CLIENT_RW_MASK (1 << 24)
580 #define MC_CG_ENABLE (1 << 18)
581 #define MC_LS_ENABLE (1 << 19)
589 #define BYPASS_VM (1 << 0)
600 #define ENABLE_L1_TLB (1 << 0)
601 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
603 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
607 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
641 #define STATE0(x) ((x) << 0) argument
644 #define STATE1(x) ((x) << 5) argument
647 #define STATE2(x) ((x) << 10) argument
650 #define STATE3(x) ((x) << 15) argument
665 #define RUN_MASK (1 << 0)
670 #define TRAIN_DONE_D0 (1 << 30)
671 #define TRAIN_DONE_D1 (1 << 31)
674 #define MEM_FALL_OUT_CMD (1 << 8)
682 #define MC_SEQ_MISC0_REV_ID_VALUE 1
722 # define DLL_SPEED(x) ((x) << 0) argument
724 # define DLL_READY (1 << 6)
725 # define MC_INT_CNTL (1 << 7)
726 # define MRDCK0_PDNB (1 << 8)
727 # define MRDCK1_PDNB (1 << 9)
728 # define MRDCK0_RESET (1 << 16)
729 # define MRDCK1_RESET (1 << 17)
730 # define DLL_READY_READ (1 << 24)
732 # define MRDCK0_BYPASS (1 << 24)
733 # define MRDCK1_BYPASS (1 << 25)
736 #define BWCTRL(x) ((x) << 20) argument
739 #define VCO_MODE(x) ((x) << 0) argument
741 #define CLKFRAC(x) ((x) << 4) argument
743 #define CLKF(x) ((x) << 16) argument
747 #define YCLK_POST_DIV(x) ((x) << 0) argument
750 #define YCLK_SEL(x) ((x) << 4) argument
751 #define YCLK_SEL_MASK (1 << 4)
754 #define CLKV(x) ((x) << 0) argument
757 #define CLKS(x) ((x) << 0) argument
761 #define CLOCK_GATING_DIS (1 << 23)
768 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
770 #define HDP_LS_ENABLE (1 << 0)
775 #define RENG_EXECUTE_ON_PWR_UP (1 << 0)
777 #define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)
778 #define STCTRL_STUTTER_EN (1 << 16)
786 # define CAC_EN (1 << 31)
802 # define IH_RB_ENABLE (1 << 0)
803 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ argument
804 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
805 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
806 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ argument
807 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
808 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
812 # define RB_OVERFLOW (1 << 0)
817 # define ENABLE_INTR (1 << 0)
818 # define IH_MC_SWAP(x) ((x) << 1) argument
820 # define IH_MC_SWAP_16BIT 1
823 # define RPTR_REARM (1 << 4)
824 # define MC_WRREQ_CREDIT(x) ((x) << 15) argument
825 # define MC_WR_CLEAN_CNT(x) ((x) << 20) argument
826 # define MC_VMID(x) ((x) << 25) argument
829 # define RESET_LNCNT_EN (1 << 0)
834 # define IH_DUMMY_RD_OVERRIDE (1 << 0)
835 # define IH_DUMMY_RD_EN (1 << 1)
836 # define IH_REQ_NONSNOOP_EN (1 << 3)
837 # define GEN_IH_INT_EN (1 << 8)
843 #define FB_READ_EN (1 << 0)
844 #define FB_WRITE_EN (1 << 1)
850 #define CP0 (1 << 0)
851 #define CP1 (1 << 1)
852 #define CP2 (1 << 2)
853 #define CP3 (1 << 3)
854 #define CP4 (1 << 4)
855 #define CP5 (1 << 5)
856 #define CP6 (1 << 6)
857 #define CP7 (1 << 7)
858 #define CP8 (1 << 8)
859 #define CP9 (1 << 9)
860 #define SDMA0 (1 << 10)
861 #define SDMA1 (1 << 11)
865 #define LB_MEMORY_SIZE(x) ((x) << 0) argument
866 #define LB_MEMORY_CONFIG(x) ((x) << 20) argument
869 # define LATENCY_WATERMARK_MASK(x) ((x) << 8) argument
871 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) argument
872 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) argument
876 # define VLINE_OCCURRED (1 << 0)
877 # define VLINE_ACK (1 << 4)
878 # define VLINE_STAT (1 << 12)
879 # define VLINE_INTERRUPT (1 << 16)
880 # define VLINE_INTERRUPT_TYPE (1 << 17)
883 # define VBLANK_OCCURRED (1 << 0)
884 # define VBLANK_ACK (1 << 4)
885 # define VBLANK_STAT (1 << 12)
886 # define VBLANK_INTERRUPT (1 << 16)
887 # define VBLANK_INTERRUPT_TYPE (1 << 17)
891 # define VBLANK_INTERRUPT_MASK (1 << 0)
892 # define VLINE_INTERRUPT_MASK (1 << 4)
893 # define VLINE2_INTERRUPT_MASK (1 << 8)
896 # define LB_D1_VLINE_INTERRUPT (1 << 2)
897 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
898 # define DC_HPD1_INTERRUPT (1 << 17)
899 # define DC_HPD1_RX_INTERRUPT (1 << 18)
900 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
901 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
902 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
903 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
905 # define LB_D2_VLINE_INTERRUPT (1 << 2)
906 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
907 # define DC_HPD2_INTERRUPT (1 << 17)
908 # define DC_HPD2_RX_INTERRUPT (1 << 18)
909 # define DISP_TIMER_INTERRUPT (1 << 24)
911 # define LB_D3_VLINE_INTERRUPT (1 << 2)
912 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
913 # define DC_HPD3_INTERRUPT (1 << 17)
914 # define DC_HPD3_RX_INTERRUPT (1 << 18)
916 # define LB_D4_VLINE_INTERRUPT (1 << 2)
917 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
918 # define DC_HPD4_INTERRUPT (1 << 17)
919 # define DC_HPD4_RX_INTERRUPT (1 << 18)
921 # define LB_D5_VLINE_INTERRUPT (1 << 2)
922 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
923 # define DC_HPD5_INTERRUPT (1 << 17)
924 # define DC_HPD5_RX_INTERRUPT (1 << 18)
926 # define LB_D6_VLINE_INTERRUPT (1 << 2)
927 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
928 # define DC_HPD6_INTERRUPT (1 << 17)
929 # define DC_HPD6_RX_INTERRUPT (1 << 18)
934 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
935 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
938 # define GRPH_PFLIP_INT_MASK (1 << 0)
939 # define GRPH_PFLIP_INT_TYPE (1 << 8)
949 # define DC_HPDx_INT_STATUS (1 << 0)
950 # define DC_HPDx_SENSE (1 << 1)
951 # define DC_HPDx_SENSE_DELAYED (1 << 4)
952 # define DC_HPDx_RX_INT_STATUS (1 << 8)
960 # define DC_HPDx_INT_ACK (1 << 0)
961 # define DC_HPDx_INT_POLARITY (1 << 8)
962 # define DC_HPDx_INT_EN (1 << 16)
963 # define DC_HPDx_RX_INT_ACK (1 << 20)
964 # define DC_HPDx_RX_INT_EN (1 << 24)
972 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) argument
973 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) argument
974 # define DC_HPDx_EN (1 << 28)
977 # define STUTTER_ENABLE (1 << 0)
981 # define FMT_DYNAMIC_EXP_EN (1 << 0)
982 # define FMT_DYNAMIC_EXP_MODE (1 << 4)
983 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
985 # define FMT_PIXEL_ENCODING (1 << 16)
986 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
988 # define FMT_TRUNCATE_EN (1 << 0)
989 # define FMT_TRUNCATE_MODE (1 << 1)
990 # define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ argument
991 # define FMT_SPATIAL_DITHER_EN (1 << 8)
992 # define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9) argument
993 # define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ argument
994 # define FMT_FRAME_RANDOM_ENABLE (1 << 13)
995 # define FMT_RGB_RANDOM_ENABLE (1 << 14)
996 # define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
997 # define FMT_TEMPORAL_DITHER_EN (1 << 16)
998 # define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */ argument
999 # define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21) argument
1000 # define FMT_TEMPORAL_LEVEL (1 << 24)
1001 # define FMT_TEMPORAL_DITHER_RESET (1 << 25)
1002 # define FMT_25FRC_SEL(x) ((x) << 26) argument
1003 # define FMT_50FRC_SEL(x) ((x) << 28) argument
1004 # define FMT_75FRC_SEL(x) ((x) << 30) argument
1006 # define FMT_CLAMP_DATA_EN (1 << 0)
1007 # define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16) argument
1009 # define FMT_CLAMP_8BPC 1
1013 #define GRBM_READ_TIMEOUT(x) ((x) << 0) argument
1017 #define ME0PIPE1_CF_RQ_PENDING (1 << 4)
1018 #define ME0PIPE1_PF_RQ_PENDING (1 << 5)
1019 #define ME1PIPE0_RQ_PENDING (1 << 6)
1020 #define ME1PIPE1_RQ_PENDING (1 << 7)
1021 #define ME1PIPE2_RQ_PENDING (1 << 8)
1022 #define ME1PIPE3_RQ_PENDING (1 << 9)
1023 #define ME2PIPE0_RQ_PENDING (1 << 10)
1024 #define ME2PIPE1_RQ_PENDING (1 << 11)
1025 #define ME2PIPE2_RQ_PENDING (1 << 12)
1026 #define ME2PIPE3_RQ_PENDING (1 << 13)
1027 #define RLC_RQ_PENDING (1 << 14)
1028 #define RLC_BUSY (1 << 24)
1029 #define TC_BUSY (1 << 25)
1030 #define CPF_BUSY (1 << 28)
1031 #define CPC_BUSY (1 << 29)
1032 #define CPG_BUSY (1 << 30)
1036 #define SRBM_RQ_PENDING (1 << 5)
1037 #define ME0PIPE0_CF_RQ_PENDING (1 << 7)
1038 #define ME0PIPE0_PF_RQ_PENDING (1 << 8)
1039 #define GDS_DMA_RQ_PENDING (1 << 9)
1040 #define DB_CLEAN (1 << 12)
1041 #define CB_CLEAN (1 << 13)
1042 #define TA_BUSY (1 << 14)
1043 #define GDS_BUSY (1 << 15)
1044 #define WD_BUSY_NO_DMA (1 << 16)
1045 #define VGT_BUSY (1 << 17)
1046 #define IA_BUSY_NO_DMA (1 << 18)
1047 #define IA_BUSY (1 << 19)
1048 #define SX_BUSY (1 << 20)
1049 #define WD_BUSY (1 << 21)
1050 #define SPI_BUSY (1 << 22)
1051 #define BCI_BUSY (1 << 23)
1052 #define SC_BUSY (1 << 24)
1053 #define PA_BUSY (1 << 25)
1054 #define DB_BUSY (1 << 26)
1055 #define CP_COHERENCY_BUSY (1 << 28)
1056 #define CP_BUSY (1 << 29)
1057 #define CB_BUSY (1 << 30)
1058 #define GUI_ACTIVE (1 << 31)
1063 #define SE_DB_CLEAN (1 << 1)
1064 #define SE_CB_CLEAN (1 << 2)
1065 #define SE_BCI_BUSY (1 << 22)
1066 #define SE_VGT_BUSY (1 << 23)
1067 #define SE_PA_BUSY (1 << 24)
1068 #define SE_TA_BUSY (1 << 25)
1069 #define SE_SX_BUSY (1 << 26)
1070 #define SE_SPI_BUSY (1 << 27)
1071 #define SE_SC_BUSY (1 << 29)
1072 #define SE_DB_BUSY (1 << 30)
1073 #define SE_CB_BUSY (1 << 31)
1076 #define SOFT_RESET_CP (1 << 0) /* All CP blocks */
1077 #define SOFT_RESET_RLC (1 << 2) /* RLC */
1078 #define SOFT_RESET_GFX (1 << 16) /* GFX */
1079 #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
1080 #define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
1081 #define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
1084 # define RDERR_INT_ENABLE (1 << 0)
1085 # define GUI_IDLE_INT_ENABLE (1 << 19)
1095 #define MEC_ME2_HALT (1 << 28)
1096 #define MEC_ME1_HALT (1 << 30)
1099 #define MEC_ME2_HALT (1 << 28)
1100 #define MEC_ME1_HALT (1 << 30)
1109 #define CP_CE_HALT (1 << 24)
1110 #define CP_PFP_HALT (1 << 26)
1111 #define CP_ME_HALT (1 << 28)
1116 #define IDLE_POLL_COUNT(x) ((x) << 16) argument
1120 #define MEQ1_START(x) ((x) << 0) argument
1121 #define MEQ2_START(x) ((x) << 8) argument
1126 #define CACHE_INVALIDATION(x) ((x) << 0) argument
1128 #define TC_ONLY 1
1130 #define AUTO_INVLD_EN(x) ((x) << 6) argument
1132 #define ES_AUTO 1
1144 #define CLIP_VTX_REORDER_ENA (1 << 0)
1145 #define NUM_CLIP_SEQ(x) ((x) << 1) argument
1148 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) argument
1149 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) argument
1152 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) argument
1153 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) argument
1154 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) argument
1155 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) argument
1158 #define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
1159 #define DISABLE_PA_SC_GUIDANCE (1 << 13)
1165 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ argument
1166 #define SHARED_BASE(x) ((x) << 16) /* LDS */ argument
1172 #define PTR32 (1 << 0)
1173 #define ALIGNMENT_MODE(x) ((x) << 2) argument
1175 #define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
1178 #define DEFAULT_MTYPE(x) ((x) << 4) argument
1179 #define APE1_MTYPE(x) ((x) << 7) argument
1189 #define VTX_DONE_DELAY(x) ((x) << 0) argument
1190 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1199 #define BACKEND_DISABLE(x) ((x) << 16) argument
1201 #define NUM_PIPES(x) ((x) << 0) argument
1204 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) argument
1207 #define NUM_SHADER_ENGINES(x) ((x) << 12) argument
1210 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) argument
1213 #define ROW_SIZE(x) ((x) << 28) argument
1218 # define ARRAY_MODE(x) ((x) << 2) argument
1220 # define ARRAY_LINEAR_ALIGNED 1
1225 # define PIPE_CONFIG(x) ((x) << 6) argument
1240 # define TILE_SPLIT(x) ((x) << 11) argument
1242 # define ADDR_SURF_TILE_SPLIT_128B 1
1248 # define MICRO_TILE_MODE_NEW(x) ((x) << 22) argument
1250 # define ADDR_SURF_THIN_MICRO_TILING 1
1253 # define SAMPLE_SPLIT(x) ((x) << 25) argument
1255 # define ADDR_SURF_SAMPLE_SPLIT_2 1
1260 # define BANK_WIDTH(x) ((x) << 0) argument
1262 # define ADDR_SURF_BANK_WIDTH_2 1
1265 # define BANK_HEIGHT(x) ((x) << 2) argument
1267 # define ADDR_SURF_BANK_HEIGHT_2 1
1270 # define MACRO_TILE_ASPECT(x) ((x) << 4) argument
1272 # define ADDR_SURF_MACRO_ASPECT_2 1
1275 # define NUM_BANKS(x) ((x) << 6) argument
1277 # define ADDR_SURF_4_BANK 1
1303 #define RB_BUFSZ(x) ((x) << 0) argument
1304 #define RB_BLKSZ(x) ((x) << 8) argument
1306 #define RB_NO_UPDATE (1 << 27)
1307 #define RB_RPTR_WR_ENA (1 << 31)
1332 # define CNTX_BUSY_INT_ENABLE (1 << 19)
1333 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
1334 # define PRIV_INSTR_INT_ENABLE (1 << 22)
1335 # define PRIV_REG_INT_ENABLE (1 << 23)
1336 # define OPCODE_ERROR_INT_ENABLE (1 << 24)
1337 # define TIME_STAMP_INT_ENABLE (1 << 26)
1338 # define CP_RINGID2_INT_ENABLE (1 << 29)
1339 # define CP_RINGID1_INT_ENABLE (1 << 30)
1340 # define CP_RINGID0_INT_ENABLE (1 << 31)
1343 # define PRIV_INSTR_INT_STAT (1 << 22)
1344 # define PRIV_REG_INT_STAT (1 << 23)
1345 # define TIME_STAMP_INT_STAT (1 << 26)
1346 # define CP_RINGID2_INT_STAT (1 << 29)
1347 # define CP_RINGID1_INT_STAT (1 << 30)
1348 # define CP_RINGID0_INT_STAT (1 << 31)
1351 # define CP_MEM_LS_EN (1 << 0)
1356 #define WPTR_POLL_EN (1 << 31)
1366 # define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
1367 # define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
1368 # define PRIV_REG_INT_ENABLE (1 << 23)
1369 # define TIME_STAMP_INT_ENABLE (1 << 26)
1370 # define GENERIC2_INT_ENABLE (1 << 29)
1371 # define GENERIC1_INT_ENABLE (1 << 30)
1372 # define GENERIC0_INT_ENABLE (1 << 31)
1381 # define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
1382 # define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
1383 # define PRIV_REG_INT_STATUS (1 << 23)
1384 # define TIME_STAMP_INT_STATUS (1 << 26)
1385 # define GENERIC2_INT_STATUS (1 << 29)
1386 # define GENERIC1_INT_STATUS (1 << 30)
1387 # define GENERIC0_INT_STATUS (1 << 31)
1394 # define RLC_ENABLE (1 << 0)
1399 # define RLC_MEM_LS_EN (1 << 0)
1404 # define LOAD_BALANCE_ENABLE (1 << 0)
1421 # define RLC_GPM_BUSY (1 << 0)
1422 # define GFX_POWER_STATUS (1 << 1)
1423 # define GFX_CLOCK_STATUS (1 << 2)
1426 # define GFX_PG_ENABLE (1 << 0)
1427 # define GFX_PG_SRC (1 << 1)
1428 # define DYN_PER_CU_PG_ENABLE (1 << 2)
1429 # define STATIC_PER_CU_PG_ENABLE (1 << 3)
1430 # define DISABLE_GDS_PG (1 << 13)
1431 # define DISABLE_CP_PG (1 << 15)
1432 # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
1433 # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
1437 # define CGCG_EN (1 << 0)
1438 # define CGLS_EN (1 << 1)
1449 # define MAX_PU_CU(x) ((x) << 0) argument
1452 # define AUTO_PG_EN (1 << 0)
1453 # define GRBM_REG_SGIT(x) ((x) << 3) argument
1459 #define BPM_ADDR(x) ((x) << 0) argument
1461 #define CGLS_ENABLE (1 << 16)
1462 #define CGCG_OVERRIDE_0 (1 << 20)
1463 #define MGCG_OVERRIDE_0 (1 << 22)
1464 #define MGCG_OVERRIDE_1 (1 << 23)
1469 # define GC_MASTER_BUSY (1 << 16)
1470 # define TC0_MASTER_BUSY (1 << 17)
1471 # define TC1_MASTER_BUSY (1 << 18)
1478 #define MESSAGE(x) ((x) << 1) argument
1480 #define MSG_ENTER_RLC_SAFE_MODE 1
1487 #define EOP_SIZE(x) ((x) << 0) argument
1500 #define QUANTUM_EN 1U
1501 #define QUANTUM_SCALE_1MS (1U << 4)
1502 #define QUANTUM_DURATION(x) ((x) << 8) argument
1512 #define DOORBELL_OFFSET(x) ((x) << 2) argument
1514 #define DOORBELL_SOURCE (1 << 28)
1515 #define DOORBELL_SCHD_HIT (1 << 29)
1516 #define DOORBELL_EN (1 << 30)
1517 #define DOORBELL_HIT (1 << 31)
1520 #define QUEUE_SIZE(x) ((x) << 0) argument
1522 #define RPTR_BLOCK_SIZE(x) ((x) << 8) argument
1524 #define PQ_VOLATILE (1 << 26)
1525 #define NO_UPDATE_RPTR (1 << 27)
1526 #define UNORD_DISPATCH (1 << 28)
1527 #define ROQ_PQ_IB_FLIP (1 << 29)
1528 #define PRIV_STATE (1 << 30)
1529 #define KMD_QUEUE (1 << 31)
1535 #define IB_ATC_EN (1U << 23)
1539 #define DEQUEUE_REQUEST_DRAIN 1
1543 #define MQD_VMID(x) ((x) << 0) argument
1561 # define RASTER_CONFIG_RB_MAP_1 1
1564 #define PKR_MAP(x) ((x) << 8) argument
1567 # define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1628 #define INSTANCE_INDEX(x) ((x) << 0) argument
1629 #define SH_INDEX(x) ((x) << 8) argument
1630 #define SE_INDEX(x) ((x) << 16) argument
1631 #define SH_BROADCAST_WRITES (1 << 29)
1632 #define INSTANCE_BROADCAST_WRITES (1 << 30)
1633 #define SE_BROADCAST_WRITES (1 << 31)
1654 #define SM_MODE(x) ((x) << 17) argument
1656 #define SM_MODE_ENABLE (1 << 20)
1657 #define CGTS_OVERRIDE (1 << 21)
1658 #define CGTS_LS_OVERRIDE (1 << 22)
1659 #define ON_MONITOR_ADD_EN (1 << 23)
1660 #define ON_MONITOR_ADD(x) ((x) << 24) argument
1674 #define PACKET_TYPE1 1
1695 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1700 #define PACKET3_BASE_INDEX(x) ((x) << 0) argument
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) argument
1730 * 1 - memory (sync - via GRBM)
1736 #define WR_ONE_ADDR (1 << 16)
1737 #define WR_CONFIRM (1 << 20)
1738 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) argument
1740 * 1 - Stream
1742 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) argument
1744 * 1 - pfp
1750 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
1751 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
1756 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) argument
1758 * 1 - <
1765 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) argument
1767 * 1 - mem
1769 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) argument
1771 * 1 - wr_wait_wr_reg
1773 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) argument
1775 * 1 - pfp
1778 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
1779 #define INDIRECT_BUFFER_VALID (1 << 23)
1780 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) argument
1782 * 1 - Stream
1788 # define PACKET3_DEST_BASE_0_ENA (1 << 0)
1789 # define PACKET3_DEST_BASE_1_ENA (1 << 1)
1790 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1791 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1792 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1793 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1794 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1795 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1796 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1797 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1798 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1799 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
1800 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
1801 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
1802 # define PACKET3_DEST_BASE_2_ENA (1 << 19)
1803 # define PACKET3_DEST_BASE_3_ENA (1 << 21)
1804 # define PACKET3_TCL1_ACTION_ENA (1 << 22)
1805 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
1806 # define PACKET3_CB_ACTION_ENA (1 << 25)
1807 # define PACKET3_DB_ACTION_ENA (1 << 26)
1808 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1809 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
1810 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1813 #define EVENT_TYPE(x) ((x) << 0) argument
1814 #define EVENT_INDEX(x) ((x) << 8) argument
1816 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
1824 #define EOP_TCL1_VOL_ACTION_EN (1 << 12)
1825 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
1826 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
1827 #define EOP_TCL1_ACTION_EN (1 << 16)
1828 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */
1829 #define EOP_TCL2_VOLATILE (1 << 24)
1830 #define EOP_CACHE_POLICY(x) ((x) << 25) argument
1832 * 1 - Stream
1835 #define DATA_SEL(x) ((x) << 29) argument
1837 * 1 - send low 32bit data
1842 #define INT_SEL(x) ((x) << 24) argument
1844 * 1 - interrupt only (DATA_SEL = 0)
1847 #define DST_SEL(x) ((x) << 16) argument
1849 * 1 - TC/L2
1857 /* 1. header
1866 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) argument
1868 * 1 - PFP
1870 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) argument
1872 * 1 - Stream
1875 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
1876 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) argument
1878 * 1 - GDS
1881 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) argument
1883 * 1 - Stream
1886 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
1887 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) argument
1889 * 1 - GDS
1893 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
1895 # define PACKET3_DMA_DATA_DIS_WC (1 << 21)
1896 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) argument
1898 * 1 - 8 in 16
1902 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) argument
1904 * 1 - 8 in 16
1908 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
1910 * 1 - register
1912 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
1914 * 1 - register
1916 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
1917 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
1918 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
1961 # define TRAP_ENABLE (1 << 0)
1962 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1963 # define SEM_WAIT_INT_ENABLE (1 << 2)
1964 # define DATA_SWAP_ENABLE (1 << 3)
1965 # define FENCE_SWAP_ENABLE (1 << 4)
1966 # define AUTO_CTXSW_ENABLE (1 << 18)
1967 # define CTXEMPTY_INT_ENABLE (1 << 28)
1975 # define SDMA_IDLE (1 << 0)
1978 # define SDMA_HALT (1 << 0)
1981 # define SDMA_RB_ENABLE (1 << 0)
1982 # define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */ argument
1983 # define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1984 # define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1985 # define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1986 # define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ argument
1995 # define SDMA_IB_ENABLE (1 << 0)
1996 # define SDMA_IB_SWAP_ENABLE (1 << 4)
1997 # define SDMA_SWITCH_INSIDE_IB (1 << 8)
1998 # define SDMA_CMD_VMID(x) ((x) << 16) argument
2008 #define SDMA_OPCODE_COPY 1
2010 # define SDMA_COPY_SUB_OPCODE_TILED 1
2017 # define SDMA_WRITE_SUB_OPCODE_TILED 1
2022 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
2024 * 1 - write 1
2026 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
2028 * 1 - signal
2030 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
2033 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) argument
2035 * 1 - wr_wait_wr_reg
2037 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) argument
2039 * 1 - <
2046 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
2048 * 1 = memory
2052 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) argument
2059 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
2062 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) argument
2086 # define DCM (1 << 0)
2087 # define CG_DT(x) ((x) << 2) argument
2089 # define CLK_OD(x) ((x) << 6) argument
2098 # define DCLK_DIR_CNTL_EN (1 << 8)
2100 # define DCLK_STATUS (1 << 0)
2121 # define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0) argument
2123 # define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4) argument
2124 # define CGC_UENC_WAIT_AWAKE (1 << 18)
2129 # define CLOCK_ON_DELAY(x) ((x) << 0) argument
2131 # define CLOCK_OFF_DELAY(x) ((x) << 4) argument
2134 # define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
2160 #define ATS_ACCESS_MODE_ALWAYS 1