Lines Matching refs:radeon_crtc

8746 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
8802 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
8810  * @radeon_crtc: the selected display controller
8819 				   struct radeon_crtc *radeon_crtc,
8823 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
8832 	if (radeon_crtc->base.enabled && mode) {
8852 	WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
8864 	if (radeon_crtc->base.enabled && mode) {
9240  * @radeon_crtc: the selected display controller
9248 				    struct radeon_crtc *radeon_crtc,
9251 	struct drm_display_mode *mode = &radeon_crtc->base.mode;
9258 	if (radeon_crtc->base.enabled && num_heads && mode) {
9284 		wm_high.vsc = radeon_crtc->vsc;
9286 		if (radeon_crtc->rmx_type != RMX_OFF)
9324 		wm_low.vsc = radeon_crtc->vsc;
9326 		if (radeon_crtc->rmx_type != RMX_OFF)
9346 		radeon_crtc->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
9350 	wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9354 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9355 	WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
9359 	tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9362 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
9363 	WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
9367 	WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
9370 	radeon_crtc->line_time = line_time;
9371 	radeon_crtc->wm_high = latency_watermark_a;
9372 	radeon_crtc->wm_low = latency_watermark_b;