Lines Matching refs:RREG32
169 *val = RREG32(reg);
186 r = RREG32(CIK_DIDT_IND_DATA);
244 (void)RREG32(PCIE_INDEX);
245 r = RREG32(PCIE_DATA);
256 (void)RREG32(PCIE_INDEX);
258 (void)RREG32(PCIE_DATA);
1902 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1920 tmp = RREG32(MC_SEQ_MISC0);
1943 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1948 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
3077 data = RREG32(CC_RB_BACKEND_DISABLE);
3082 data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3170 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
3264 RREG32(MC_SHARED_CHMAP);
3265 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3354 tmp = RREG32(SPI_CONFIG_CNTL);
3362 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3366 tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3370 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3396 tmp = RREG32(HDP_MISC_CNTL);
3400 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3470 tmp = RREG32(scratch);
3815 tmp = RREG32(scratch);
4121 rptr = RREG32(CP_RB0_RPTR);
4129 return RREG32(CP_RB0_WPTR);
4136 (void)RREG32(CP_RB0_WPTR);
4149 rptr = RREG32(CP_HQD_PQ_RPTR);
4168 wptr = RREG32(CP_HQD_PQ_WPTR);
4191 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4195 if (RREG32(CP_HQD_ACTIVE) & 1) {
4198 if (!(RREG32(CP_HQD_ACTIVE) & 1))
4525 tmp = RREG32(CP_CPF_DEBUG);
4547 tmp = RREG32(CP_HPD_EOP_CONTROL);
4610 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4616 RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
4628 if (RREG32(CP_HQD_ACTIVE) & 1) {
4631 if (!(RREG32(CP_HQD_ACTIVE) & 1))
4646 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
4658 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4702 RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
4720 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR);
4796 RREG32(GRBM_STATUS));
4798 RREG32(GRBM_STATUS2));
4800 RREG32(GRBM_STATUS_SE0));
4802 RREG32(GRBM_STATUS_SE1));
4804 RREG32(GRBM_STATUS_SE2));
4806 RREG32(GRBM_STATUS_SE3));
4808 RREG32(SRBM_STATUS));
4810 RREG32(SRBM_STATUS2));
4812 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
4814 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
4815 dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT));
4817 RREG32(CP_STALLED_STAT1));
4819 RREG32(CP_STALLED_STAT2));
4821 RREG32(CP_STALLED_STAT3));
4823 RREG32(CP_CPF_BUSY_STAT));
4825 RREG32(CP_CPF_STALLED_STAT1));
4826 dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));
4827 dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));
4829 RREG32(CP_CPC_STALLED_STAT1));
4830 dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));
4848 tmp = RREG32(GRBM_STATUS);
4861 tmp = RREG32(GRBM_STATUS2);
4866 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
4871 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
4876 tmp = RREG32(SRBM_STATUS2);
4884 tmp = RREG32(SRBM_STATUS);
4935 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4937 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4954 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
4960 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5009 tmp = RREG32(GRBM_SOFT_RESET);
5013 tmp = RREG32(GRBM_SOFT_RESET);
5019 tmp = RREG32(GRBM_SOFT_RESET);
5023 tmp = RREG32(SRBM_SOFT_RESET);
5027 tmp = RREG32(SRBM_SOFT_RESET);
5033 tmp = RREG32(SRBM_SOFT_RESET);
5054 save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
5055 save->gmcon_misc = RREG32(GMCON_MISC);
5056 save->gmcon_misc3 = RREG32(GMCON_MISC3);
5157 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5161 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5189 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
5335 tmp = RREG32(MC_ARB_RAMCFG);
5341 tmp = RREG32(MC_SHARED_CHMAP);
5377 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5378 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5496 u32 tmp = RREG32(CHUB_CONTROL);
5546 rdev->vm_manager.saved_table_addr[i] = RREG32(reg);
5621 u64 tmp = RREG32(MC_VM_FB_OFFSET);
5760 u32 tmp = RREG32(CP_INT_CNTL_RING0);
5773 tmp = RREG32(RLC_LB_CNTL);
5790 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
5800 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
5810 tmp = RREG32(RLC_CNTL);
5819 orig = data = RREG32(RLC_CNTL);
5828 if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
5848 if ((RREG32(RLC_GPM_STAT) & mask) == mask)
5854 if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
5919 tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
5994 orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
6013 RREG32(CB_CGTT_SCLK_CTRL);
6014 RREG32(CB_CGTT_SCLK_CTRL);
6015 RREG32(CB_CGTT_SCLK_CTRL);
6016 RREG32(CB_CGTT_SCLK_CTRL);
6033 orig = data = RREG32(CP_MEM_SLP_CNTL);
6040 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6057 orig = data = RREG32(CGTS_SM_CTRL_REG);
6072 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
6077 data = RREG32(RLC_MEM_SLP_CNTL);
6083 data = RREG32(CP_MEM_SLP_CNTL);
6089 orig = data = RREG32(CGTS_SM_CTRL_REG);
6126 orig = data = RREG32(mc_cg_registers[i]);
6143 orig = data = RREG32(mc_cg_registers[i]);
6162 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
6167 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
6180 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6185 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6190 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6195 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6212 orig = data = RREG32(UVD_CGC_CTRL);
6221 orig = data = RREG32(UVD_CGC_CTRL);
6251 orig = data = RREG32(HDP_HOST_PATH_CNTL);
6267 orig = data = RREG32(HDP_MEM_POWER_LS);
6357 orig = data = RREG32(RLC_PG_CNTL);
6371 orig = data = RREG32(RLC_PG_CNTL);
6384 orig = data = RREG32(RLC_PG_CNTL);
6397 orig = data = RREG32(RLC_PG_CNTL);
6500 orig = data = RREG32(RLC_PG_CNTL);
6505 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6510 orig = data = RREG32(RLC_PG_CNTL);
6515 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6520 data = RREG32(DB_RENDER_CONTROL);
6530 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6531 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
6574 tmp = RREG32(RLC_MAX_PG_CU);
6585 orig = data = RREG32(RLC_PG_CNTL);
6599 orig = data = RREG32(RLC_PG_CNTL);
6632 orig = data = RREG32(RLC_PG_CNTL);
6640 data = RREG32(CP_RB_WPTR_POLL_CNTL);
6648 data = RREG32(RLC_PG_DELAY_2);
6653 data = RREG32(RLC_AUTO_PG_CTRL);
6814 u32 ih_cntl = RREG32(IH_CNTL);
6815 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
6833 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
6834 u32 ih_cntl = RREG32(IH_CNTL);
6859 tmp = RREG32(CP_INT_CNTL_RING0) &
6863 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6865 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6909 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6911 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6913 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6915 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6917 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6919 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6959 interrupt_cntl = RREG32(INTERRUPT_CNTL);
7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
7041 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7042 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7043 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7044 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7045 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7046 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
7048 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
7049 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7053 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7054 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7055 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7057 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7058 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
7271 RREG32(SRBM_STATUS);
7289 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
7290 rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
7291 rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
7292 rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
7293 rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
7294 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
7295 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
7297 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +
7299 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +
7302 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +
7304 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +
7308 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +
7310 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +
7364 tmp = RREG32(DC_HPD1_INT_CONTROL);
7369 tmp = RREG32(DC_HPD2_INT_CONTROL);
7374 tmp = RREG32(DC_HPD3_INT_CONTROL);
7379 tmp = RREG32(DC_HPD4_INT_CONTROL);
7384 tmp = RREG32(DC_HPD5_INT_CONTROL);
7389 tmp = RREG32(DC_HPD6_INT_CONTROL);
7394 tmp = RREG32(DC_HPD1_INT_CONTROL);
7399 tmp = RREG32(DC_HPD2_INT_CONTROL);
7404 tmp = RREG32(DC_HPD3_INT_CONTROL);
7409 tmp = RREG32(DC_HPD4_INT_CONTROL);
7414 tmp = RREG32(DC_HPD5_INT_CONTROL);
7419 tmp = RREG32(DC_HPD6_INT_CONTROL);
7488 wptr = RREG32(IH_RB_WPTR);
7499 tmp = RREG32(IH_RB_CNTL);
7887 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
7896 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
7897 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
7898 mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
8858 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
8891 u32 tmp = RREG32(MC_SHARED_CHMAP);
9350 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9359 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
9419 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
9420 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);