Lines Matching refs:performance_levels
801 if (ps->performance_levels[i].mclk > max_limits->mclk)
802 ps->performance_levels[i].mclk = max_limits->mclk;
803 if (ps->performance_levels[i].sclk > max_limits->sclk)
804 ps->performance_levels[i].sclk = max_limits->sclk;
811 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
812 sclk = ps->performance_levels[0].sclk;
814 mclk = ps->performance_levels[0].mclk;
815 sclk = ps->performance_levels[0].sclk;
825 ps->performance_levels[0].sclk = sclk;
826 ps->performance_levels[0].mclk = mclk;
828 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
829 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
832 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
833 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
835 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
836 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
2551 boot_state->performance_levels[0].sclk) {
2559 boot_state->performance_levels[0].mclk) {
3714 state->performance_levels[0].sclk,
3715 state->performance_levels[high_limit_count].sclk);
3719 state->performance_levels[0].mclk,
3720 state->performance_levels[high_limit_count].mclk);
3723 state->performance_levels[0].pcie_gen,
3724 state->performance_levels[0].pcie_lane,
3725 state->performance_levels[high_limit_count].pcie_gen,
3726 state->performance_levels[high_limit_count].pcie_lane);
3809 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3811 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3850 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3851 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
4753 pcie_speed = state->performance_levels[i].pcie_gen;
5422 struct ci_pl *pl = &ps->performance_levels[index];
5920 pl = &ps->performance_levels[i];
5947 return requested_state->performance_levels[0].sclk;
5949 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5958 return requested_state->performance_levels[0].mclk;
5960 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;