Lines Matching full:pi
169 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
171 return pi; in ci_get_pi()
183 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
193 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
199 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
203 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
207 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
217 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
221 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
223 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
224 pi->caps_cac = false; in ci_initialize_powertune_defaults()
225 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
226 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
227 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
228 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
230 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
231 pi->caps_cac = true; in ci_initialize_powertune_defaults()
233 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
235 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
236 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
237 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
248 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd() local
249 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
250 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
251 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
277 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid() local
278 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
281 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
284 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
285 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
292 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line() local
293 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
295 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
296 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
297 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
298 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
305 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit() local
306 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
310 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
311 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
313 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
320 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8() local
321 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
328 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
329 pi->sram_end); in ci_populate_dw8()
333 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
340 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan() local
347 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
355 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
356 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
357 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
379 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
380 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
387 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd() local
395 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
396 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
403 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table() local
404 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
405 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
416 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
418 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
451 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base() local
455 if (pi->caps_power_containment) { in ci_populate_pm_base()
459 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
487 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
488 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
498 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt() local
501 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
510 if (pi->caps_db_ramping) { in ci_do_enable_didt()
519 if (pi->caps_td_ramping) { in ci_do_enable_didt()
528 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
588 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt() local
591 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
592 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
613 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment() local
618 pi->power_containment_features = 0; in ci_enable_power_containment()
619 if (pi->caps_power_containment) { in ci_enable_power_containment()
620 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
625 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
628 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
633 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
636 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
646 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
653 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
654 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
657 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
660 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
662 pi->power_containment_features = 0; in ci_enable_power_containment()
671 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac() local
675 if (pi->caps_cac) { in ci_enable_smc_cac()
680 pi->cac_enabled = false; in ci_enable_smc_cac()
682 pi->cac_enabled = true; in ci_enable_smc_cac()
684 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
686 pi->cac_enabled = false; in ci_enable_smc_cac()
696 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm() local
699 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
714 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level() local
722 if (pi->caps_power_containment) { in ci_power_control_set_level()
736 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd() local
738 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
741 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
748 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short() local
750 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
769 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules() local
790 pi->battery_state = true; in ci_apply_state_adjust_rules()
792 pi->battery_state = false; in ci_apply_state_adjust_rules()
907 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode() local
910 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
912 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
914 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
915 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
929 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table() local
938 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
991 pi->fan_table_start, in ci_thermal_setup_fan_table()
994 pi->sram_end); in ci_thermal_setup_fan_table()
1006 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control() local
1009 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1028 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1035 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control() local
1039 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1076 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent() local
1081 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1121 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode() local
1124 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1185 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode() local
1188 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1190 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1194 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1196 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1254 struct ci_power_info *pi = ci_get_pi(rdev);
1257 pi->soft_regs_start + reg_offset,
1258 value, pi->sram_end);
1265 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register() local
1268 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1269 value, pi->sram_end); in ci_write_smc_soft_register()
1274 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits() local
1275 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1277 if (pi->caps_fps) { in ci_init_fps_limits()
1290 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t() local
1294 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1295 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1298 pi->dpm_table_start + in ci_update_sclk_t()
1301 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1310 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages() local
1315 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1316 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1324 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1325 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1326 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1336 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1337 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1338 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1341 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1342 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1343 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1352 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources() local
1375 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1391 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source() local
1394 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1395 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1396 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1399 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1400 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1401 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1414 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm() local
1417 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1420 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1421 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1427 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1428 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1434 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1440 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm() local
1444 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1450 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1468 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1474 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1486 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm() local
1511 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1522 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm() local
1525 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1528 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1529 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1535 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1536 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1547 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm() local
1560 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1592 struct ci_power_info *pi = ci_get_pi(rdev);
1604 if (pi->caps_automatic_dc_transition) {
1658 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk() local
1660 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1672 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk() local
1674 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1686 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie() local
1688 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1700 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit() local
1702 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1776 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header() local
1783 &tmp, pi->sram_end); in ci_process_firmware_header()
1787 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1792 &tmp, pi->sram_end); in ci_process_firmware_header()
1796 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1801 &tmp, pi->sram_end); in ci_process_firmware_header()
1805 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1810 &tmp, pi->sram_end); in ci_process_firmware_header()
1814 pi->fan_table_start = tmp; in ci_process_firmware_header()
1819 &tmp, pi->sram_end); in ci_process_firmware_header()
1823 pi->arb_table_start = tmp; in ci_process_firmware_header()
1830 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers() local
1832 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1834 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1836 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1838 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1840 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1842 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1844 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1845 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1846 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1847 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1848 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1849 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1850 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1851 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1852 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1857 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t() local
1859 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1923 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch() local
1926 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1934 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1979 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum() local
1983 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2053 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware() local
2065 return ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2092 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables() local
2095 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2098 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2101 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2104 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2109 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2111 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2113 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2116 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2119 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2122 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2127 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2129 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2131 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2134 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2137 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2140 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2145 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2147 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2177 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table() local
2180 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2183 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2186 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2188 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2201 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table() local
2203 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2206 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2209 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2211 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2223 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table() local
2226 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2229 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2232 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2234 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2266 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value() local
2269 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2272 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2371 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index() local
2375 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2376 &tmp, pi->sram_end); in ci_init_arb_table_index()
2383 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2384 tmp, pi->sram_end); in ci_init_arb_table_index()
2504 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters() local
2511 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2512 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2514 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2515 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2524 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2527 pi->sram_end); in ci_do_program_memory_timing_parameters()
2534 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters() local
2536 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2546 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state() local
2552 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2560 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2585 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level() local
2586 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2599 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2600 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2750 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params() local
2751 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2752 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2753 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2754 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2755 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2756 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2757 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2758 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2759 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2777 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2783 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2835 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level() local
2865 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2875 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2885 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2886 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2887 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2892 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2893 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2896 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2899 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2900 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2903 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2904 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2914 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2948 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level() local
2951 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2952 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2953 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2954 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
2959 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
2960 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2962 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2964 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2986 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
2987 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
2988 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
2989 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3008 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3009 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3011 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3014 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3031 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3033 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3035 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3037 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3039 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3040 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3041 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3049 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3063 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv() local
3064 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3081 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level() local
3088 pi->ulv.supported = false; in ci_populate_ulv_level()
3092 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3106 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3119 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params() local
3121 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3122 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3123 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3124 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3143 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3176 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level() local
3194 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3210 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3234 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels() local
3235 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3236 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3240 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3248 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3249 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3253 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3255 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3258 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3260 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3261 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3266 pi->sram_end); in ci_populate_all_graphic_levels()
3281 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels() local
3282 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3283 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3287 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3297 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3302 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3306 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3307 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3308 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3309 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3312 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3314 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3315 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3318 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3323 pi->sram_end); in ci_populate_all_memory_levels()
3351 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables() local
3353 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3356 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3357 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3358 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3359 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3360 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3361 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3365 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3369 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3370 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3371 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3373 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3374 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3375 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3376 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3377 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3378 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3379 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3380 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3381 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3382 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3383 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3384 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3385 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3386 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3387 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3388 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3389 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3390 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3392 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3399 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables() local
3417 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3420 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3423 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3426 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3429 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3432 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3435 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3438 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3440 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3442 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3444 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3448 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3451 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3453 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3455 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3457 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3462 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3464 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3466 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3468 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3473 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3475 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3477 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3483 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3485 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3487 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3513 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table() local
3514 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3516 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3523 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3534 if (pi->mem_gddr5) in ci_init_smc_table()
3538 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3585 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3586 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3587 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3589 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3590 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3591 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3593 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3594 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3595 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3612 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3614 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3622 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3624 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3648 pi->dpm_table_start + in ci_init_smc_table()
3652 pi->sram_end); in ci_init_smc_table()
3678 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states() local
3679 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3709 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states() local
3721 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3726 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3773 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask() local
3778 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3779 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3782 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3788 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3789 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3792 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3798 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3799 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3802 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3814 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table() local
3816 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3818 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3822 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3830 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3837 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3846 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3850 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3856 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3860 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3863 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3866 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3869 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3872 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3878 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3889 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm() local
3899 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3903 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3905 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3912 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3914 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3915 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3916 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3919 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3922 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3923 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3924 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3927 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3938 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm() local
3948 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3951 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3953 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
3960 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
3971 struct ci_power_info *pi = ci_get_pi(rdev);
3981 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3984 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3986 if (!pi->caps_samu_dpm)
3993 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4002 struct ci_power_info *pi = ci_get_pi(rdev);
4012 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4015 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4017 if (!pi->caps_acp_dpm)
4024 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4035 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm() local
4039 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4041 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4043 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4048 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4074 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm() local
4083 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4086 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4108 struct ci_power_info *pi = ci_get_pi(rdev);
4112 pi->smc_state_table.AcpBootLevel = 0;
4116 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4127 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask() local
4134 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4135 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4136 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4137 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4138 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4139 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4140 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4141 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4142 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4144 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4145 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4165 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level() local
4170 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4171 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4173 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4189 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4190 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4192 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4208 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4209 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4211 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4228 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4229 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4231 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4243 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4244 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4246 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4258 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4259 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4261 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4274 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4295 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers() local
4321 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4328 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4582 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table() local
4584 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4642 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses() local
4645 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4646 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4649 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4650 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4678 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc() local
4681 for (i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4682 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4686 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4689 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4690 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4691 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4697 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc() local
4700 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4702 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4708 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table() local
4711 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4713 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4716 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4719 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4720 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4722 pi->sram_end); in ci_populate_initial_mc_reg_table()
4727 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table() local
4729 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4732 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4734 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4737 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4739 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4741 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4742 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4809 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change() local
4814 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4817 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4819 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4820 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4827 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4837 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4842 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4850 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change() local
4855 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4875 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable() local
4896 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4897 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4900 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4901 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4918 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage() local
4919 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4932 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage() local
4933 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5051 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type() local
5058 pi->mem_gddr5 = true; in ci_get_memory_type()
5060 pi->mem_gddr5 = false; in ci_get_memory_type()
5068 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps() local
5070 pi->current_rps = *rps; in ci_update_current_ps()
5071 pi->current_ps = *new_ps; in ci_update_current_ps()
5072 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5079 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps() local
5081 pi->requested_rps = *rps; in ci_update_requested_ps()
5082 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5083 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5088 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state() local
5094 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5101 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state() local
5102 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5123 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable() local
5129 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5137 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5140 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5142 if (pi->dynamic_ss) in ci_dpm_enable()
5144 if (pi->thermal_protection) in ci_dpm_enable()
5174 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5278 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable() local
5288 if (pi->thermal_protection) in ci_dpm_disable()
5309 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state() local
5310 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5311 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5315 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5344 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5366 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5434 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info() local
5446 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5447 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5450 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5454 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5458 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5459 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5460 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5465 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5466 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5467 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5468 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5473 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5474 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5475 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5476 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5477 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5478 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5479 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5480 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5481 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5484 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5485 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5486 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5487 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5488 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5489 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5490 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5491 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5492 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5648 struct ci_power_info *pi; in ci_dpm_init() local
5653 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5654 if (pi == NULL) in ci_dpm_init()
5656 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5661 pi->sys_pcie_mask = 0; in ci_dpm_init()
5664 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5668 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5671 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; in ci_dpm_init()
5673 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5675 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5676 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5677 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5678 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5680 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5681 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5682 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5683 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5685 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5710 pi->dll_default_on = false; in ci_dpm_init()
5711 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5713 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5714 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5715 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5716 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5717 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5718 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5719 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5720 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5722 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5724 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5725 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5726 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5727 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5732 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5735 pi->caps_sclk_ds = true; in ci_dpm_init()
5737 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5738 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5739 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5740 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5744 pi->caps_fps = false; in ci_dpm_init()
5746 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5748 pi->caps_uvd_dpm = true; in ci_dpm_init()
5749 pi->caps_vce_dpm = true; in ci_dpm_init()
5783 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5784 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5785 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5787 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5788 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5789 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5792 pi->uvd_enabled = false; in ci_dpm_init()
5794 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5843 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5844 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5845 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5847 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5849 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5853 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5855 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5862 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5864 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5869 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5872 pi->pcie_performance_request = in ci_dpm_init()
5875 pi->pcie_performance_request = false; in ci_dpm_init()
5880 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5881 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5882 pi->dynamic_ss = true; in ci_dpm_init()
5884 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5885 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5886 pi->dynamic_ss = true; in ci_dpm_init()
5890 pi->thermal_protection = true; in ci_dpm_init()
5892 pi->thermal_protection = false; in ci_dpm_init()
5894 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5896 pi->uvd_power_gated = false; in ci_dpm_init()
5904 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5912 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5913 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5917 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5957 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk() local
5958 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
5968 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk() local
5969 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()