Lines Matching defs:sclk
772 u32 sclk, mclk;
803 if (ps->performance_levels[i].sclk > max_limits->sclk)
804 ps->performance_levels[i].sclk = max_limits->sclk;
812 sclk = ps->performance_levels[0].sclk;
815 sclk = ps->performance_levels[0].sclk;
819 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
820 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
825 ps->performance_levels[0].sclk = sclk;
828 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
829 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
2337 u32 sclk,
2345 if (sclk < limits->entries[i].sclk) {
2409 u32 sclk, u32 min_sclk_in_sr)
2416 if (sclk < min)
2420 tmp = sclk / (1 << i);
2479 u32 sclk,
2487 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2493 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2551 boot_state->performance_levels[0].sclk) {
3117 SMU7_Discrete_GraphicsLevel *sclk)
3161 sclk->SclkFrequency = engine_clock;
3162 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3163 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3164 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3165 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3166 sclk->SclkDid = (u8)dividers.post_divider;
3714 state->performance_levels[0].sclk,
3715 state->performance_levels[high_limit_count].sclk);
3809 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3817 if (sclk == sclk_table->dpm_levels[i].value)
3824 /* XXX The current code always reprogrammed the sclk levels,
3825 * but we don't currently handle disp sclk requirements
3850 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3859 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
4890 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
5426 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5427 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5452 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5566 u32 sclk, mclk;
5570 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5571 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5574 rdev->pm.dpm.vce_states[i].sclk = sclk;
5885 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5900 u32 sclk = ci_get_average_sclk_freq(rdev);
5905 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5906 sclk, mclk);
5921 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5922 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5929 u32 sclk = ci_get_average_sclk_freq(rdev);
5931 return sclk;
5947 return requested_state->performance_levels[0].sclk;
5949 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;