Lines Matching refs:dp_info
548 static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
551 atombios_dig_transmitter_setup(dp_info->encoder,
553 0, dp_info->train_set[0]); /* sets all lanes at once */
556 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
557 dp_info->train_set, dp_info->dp_lane_count);
560 static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
565 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
577 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
587 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
588 dp_info->dp_clock, dp_info->enc_id, rtp);
592 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
595 static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
597 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
602 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
605 if (dp_info->dpcd[3] & 0x1)
606 drm_dp_dpcd_writeb(dp_info->aux,
609 drm_dp_dpcd_writeb(dp_info->aux,
613 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
616 tmp = dp_info->dp_lane_count;
617 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
619 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
622 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
623 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
626 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
627 atombios_dig_encoder_setup(dp_info->encoder,
630 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
631 dp_info->dp_clock, dp_info->enc_id, 0);
634 drm_dp_dpcd_writeb(dp_info->aux,
641 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
646 drm_dp_dpcd_writeb(dp_info->aux,
651 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
652 atombios_dig_encoder_setup(dp_info->encoder,
655 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
656 dp_info->dp_clock, dp_info->enc_id, 0);
661 static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
667 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
668 memset(dp_info->train_set, 0, 4);
669 radeon_dp_update_vs_emph(dp_info);
675 dp_info->tries = 0;
678 drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);
680 if (drm_dp_dpcd_read_link_status(dp_info->aux,
681 dp_info->link_status) < 0) {
686 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
691 for (i = 0; i < dp_info->dp_lane_count; i++) {
692 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
695 if (i == dp_info->dp_lane_count) {
700 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
701 ++dp_info->tries;
702 if (dp_info->tries == 5) {
707 dp_info->tries = 0;
709 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
712 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
714 radeon_dp_update_vs_emph(dp_info);
721 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
722 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
728 static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
732 if (dp_info->tp3_supported)
733 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
735 radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
738 dp_info->tries = 0;
741 drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
743 if (drm_dp_dpcd_read_link_status(dp_info->aux,
744 dp_info->link_status) < 0) {
749 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
755 if (dp_info->tries > 5) {
761 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
763 radeon_dp_update_vs_emph(dp_info);
764 dp_info->tries++;
772 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
773 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
788 struct radeon_dp_link_train_info dp_info;
809 dp_info.use_dpencoder = true;
813 dp_info.use_dpencoder = false;
816 dp_info.enc_id = 0;
818 dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
820 dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
822 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
824 dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
829 dp_info.tp3_supported = true;
831 dp_info.tp3_supported = false;
833 dp_info.tp3_supported = false;
836 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
837 dp_info.rdev = rdev;
838 dp_info.encoder = encoder;
839 dp_info.connector = connector;
840 dp_info.dp_lane_count = dig_connector->dp_lane_count;
841 dp_info.dp_clock = dig_connector->dp_clock;
842 dp_info.aux = &radeon_connector->ddc_bus->aux;
844 if (radeon_dp_link_train_init(&dp_info))
846 if (radeon_dp_link_train_cr(&dp_info))
848 if (radeon_dp_link_train_ce(&dp_info))
851 if (radeon_dp_link_train_finish(&dp_info))