Lines Matching refs:aux

159 radeon_dp_aux_transfer_atom(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
162 		container_of(aux, struct radeon_i2c_chan, aux);
233 	radeon_connector->ddc_bus->aux.drm_dev = radeon_connector->base.dev;
236 			radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
238 			radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
240 		radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
243 	drm_dp_aux_init(&radeon_connector->ddc_bus->aux);
373 	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
377 	if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
388 	ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
423 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
435 		if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
504 	if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux,
525 		drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
545 	struct drm_dp_aux *aux;
556 	drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
592 	drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
606 		drm_dp_dpcd_writeb(dp_info->aux,
609 		drm_dp_dpcd_writeb(dp_info->aux,
613 		drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
619 	drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
623 	drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
634 	drm_dp_dpcd_writeb(dp_info->aux,
646 	drm_dp_dpcd_writeb(dp_info->aux,
678 		drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);
680 		if (drm_dp_dpcd_read_link_status(dp_info->aux,
741 		drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
743 		if (drm_dp_dpcd_read_link_status(dp_info->aux,
826 	if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
842 	dp_info.aux = &radeon_connector->ddc_bus->aux;