Lines Matching +full:per +full:- +full:lane
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
32 #include "atom-bits.h"
90 struct drm_device *dev = chan->dev;
91 struct radeon_device *rdev = dev->dev_private;
100 mutex_lock(&chan->mutex);
101 mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
103 base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
110 args.v1.ucChannelID = chan->rec.i2c_id;
113 args.v2.ucHPD_ID = chan->rec.hpd;
115 atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
122 r = -ETIMEDOUT;
129 r = -EIO;
136 r = -EIO;
149 mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
150 mutex_unlock(&chan->mutex);
168 if (WARN_ON(msg->size > 16))
169 return -E2BIG;
171 tx_buf[0] = msg->address & 0xff;
172 tx_buf[1] = (msg->address >> 8) & 0xff;
173 tx_buf[2] = (msg->request << 4) |
174 ((msg->address >> 16) & 0xf);
175 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
177 switch (msg->request & ~DP_AUX_I2C_MOT) {
186 if (WARN_ON_ONCE(msg->size > 12))
187 return -E2BIG;
191 tx_size = HEADER_SIZE + msg->size;
192 if (msg->size == 0)
196 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
201 ret = msg->size;
209 if (msg->size == 0)
214 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
217 ret = -EINVAL;
222 msg->reply = ack >> 4;
229 struct drm_device *dev = radeon_connector->base.dev;
230 struct radeon_device *rdev = dev->dev_private;
232 radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
233 radeon_connector->ddc_bus->aux.drm_dev = radeon_connector->base.dev;
236 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_native;
238 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
240 radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer_atom;
243 drm_dp_aux_init(&radeon_connector->ddc_bus->aux);
244 radeon_connector->ddc_bus->has_aux = true;
258 int lane;
260 for (lane = 0; lane < lane_count; lane++) {
261 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
262 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
264 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
265 lane,
285 for (lane = 0; lane < 4; lane++)
286 train_set[lane] = v | p;
289 /* convert bits per color to bits per pixel */
335 return -EINVAL;
352 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
358 struct drm_device *dev = radeon_connector->base.dev;
359 struct radeon_device *rdev = dev->dev_private;
362 radeon_connector->ddc_bus->rec.i2c_id, 0);
367 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
370 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
373 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
377 if (drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
384 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
388 ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_DPCD_REV, msg,
391 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
393 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
394 dig_connector->dpcd);
401 dig_connector->dpcd[0] = 0;
408 struct drm_device *dev = encoder->dev;
409 struct radeon_device *rdev = dev->dev_private;
418 if (!radeon_connector->con_priv)
423 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
433 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
435 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,
452 if (!radeon_connector->con_priv)
454 dig_connector = radeon_connector->con_priv;
456 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
457 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
458 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
459 mode->clock,
460 &dig_connector->dp_lane_count,
461 &dig_connector->dp_clock);
463 dig_connector->dp_clock = 0;
464 dig_connector->dp_lane_count = 0;
477 if ((mode->clock > 340000) &&
481 if (!radeon_connector->con_priv)
483 dig_connector = radeon_connector->con_priv;
485 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd,
486 mode->clock,
502 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
504 if (drm_dp_dpcd_read_link_status(&radeon_connector->ddc_bus->aux,
507 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
518 if (!radeon_connector->con_priv)
521 dig_connector = radeon_connector->con_priv;
524 if (dig_connector->dpcd[0] >= 0x11) {
525 drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,
551 atombios_dig_transmitter_setup(dp_info->encoder,
553 0, dp_info->train_set[0]); /* sets all lanes at once */
556 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
557 dp_info->train_set, dp_info->dp_lane_count);
565 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) {
577 atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
587 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
588 dp_info->dp_clock, dp_info->enc_id, rtp);
592 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
597 struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder);
598 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
602 radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
605 if (dp_info->dpcd[3] & 0x1)
606 drm_dp_dpcd_writeb(dp_info->aux,
609 drm_dp_dpcd_writeb(dp_info->aux,
612 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
613 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
615 /* set the lane count on the sink */
616 tmp = dp_info->dp_lane_count;
617 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
619 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
622 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
623 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
626 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
627 atombios_dig_encoder_setup(dp_info->encoder,
630 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
631 dp_info->dp_clock, dp_info->enc_id, 0);
634 drm_dp_dpcd_writeb(dp_info->aux,
646 drm_dp_dpcd_writeb(dp_info->aux,
651 if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder)
652 atombios_dig_encoder_setup(dp_info->encoder,
655 radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
656 dp_info->dp_clock, dp_info->enc_id, 0);
668 memset(dp_info->train_set, 0, 4);
675 dp_info->tries = 0;
678 drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd);
680 if (drm_dp_dpcd_read_link_status(dp_info->aux,
681 dp_info->link_status) < 0) {
686 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
691 for (i = 0; i < dp_info->dp_lane_count; i++) {
692 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
695 if (i == dp_info->dp_lane_count) {
700 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
701 ++dp_info->tries;
702 if (dp_info->tries == 5) {
707 dp_info->tries = 0;
709 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
712 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
718 return -1;
720 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
721 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
722 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
732 if (dp_info->tp3_supported)
738 dp_info->tries = 0;
741 drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd);
743 if (drm_dp_dpcd_read_link_status(dp_info->aux,
744 dp_info->link_status) < 0) {
749 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
755 if (dp_info->tries > 5) {
761 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
764 dp_info->tries++;
769 return -1;
771 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
772 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
773 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
782 struct drm_device *dev = encoder->dev;
783 struct radeon_device *rdev = dev->dev_private;
792 if (!radeon_encoder->enc_priv)
794 dig = radeon_encoder->enc_priv;
797 if (!radeon_connector->con_priv)
799 dig_connector = radeon_connector->con_priv;
801 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
802 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
811 if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) {
817 if (dig->dig_encoder)
821 if (dig->linkb)
826 if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
836 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
840 dp_info.dp_lane_count = dig_connector->dp_lane_count;
841 dp_info.dp_clock = dig_connector->dp_clock;
842 dp_info.aux = &radeon_connector->ddc_bus->aux;