Lines Matching refs:fb_location
1144 uint64_t fb_location; in dce4_crtc_do_set_base() local
1173 fb_location = radeon_bo_gpu_offset(rbo); in dce4_crtc_do_set_base()
1175 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in dce4_crtc_do_set_base()
1386 upper_32_bits(fb_location)); in dce4_crtc_do_set_base()
1388 upper_32_bits(fb_location)); in dce4_crtc_do_set_base()
1390 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); in dce4_crtc_do_set_base()
1392 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); in dce4_crtc_do_set_base()
1465 uint64_t fb_location; in avivo_crtc_do_set_base() local
1493 fb_location = radeon_bo_gpu_offset(rbo); in avivo_crtc_do_set_base()
1495 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in avivo_crtc_do_set_base()
1601 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1602 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1604 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1605 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1609 (u32) fb_location); in avivo_crtc_do_set_base()
1611 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()