Lines Matching refs:UCHAR
49 #ifndef UCHAR
50 typedef unsigned char UCHAR; typedef
203 UCHAR ucTableFormatRevision; /*Change it when the Parser is not backward compatible */
204 …UCHAR ucTableContentRevision; /*Change it only when the table needs to change but the firmware */
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
229 UCHAR ucExtendedFunctionCode;
230 UCHAR ucReserved;
411 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
412 UCHAR ucReserved; //may expand to return larger Fbdiv later
413 UCHAR ucFbDiv; //return value
414 UCHAR ucPostDiv; //return value
420 …UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engi…
422 UCHAR ucPostDiv; //return post div to be written to register
466 UCHAR ucRefDiv; //Output Parameter
467 UCHAR ucPostDiv; //Output Parameter
468 UCHAR ucCntlFlag; //Output Parameter
469 UCHAR ucReserved;
499 UCHAR ucRefDiv; //Output Parameter
500 UCHAR ucPostDiv; //Output Parameter
503 UCHAR ucCntlFlag; //Output Flags
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
506 UCHAR ucReserved;
525 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
526 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
527 UCHAR ucPllCntlFlag; //Output Flags: control flag
528 UCHAR ucReserved;
546 UCHAR ucDllSpeed; //Output
547 UCHAR ucPostDiv; //Output
549 …UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-Stro…
550 UCHAR ucPllCntlFlag; //Output:
552 UCHAR ucBWCntl;
627 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
628 UCHAR ucPadding[3];
637 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
638 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
639 UCHAR ucPadding[2];
647 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
648 UCHAR ucPadding[3];
658 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
659 UCHAR ucMisc; //Valid only when table revision =1.3 and above
677 …UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as …
678 UCHAR ucAction; // 0: turn off encoder
693 UCHAR ucConfig;
701 UCHAR ucAction; // =0: turn off encoder
703 UCHAR ucEncoderMode;
709 UCHAR ucLaneNum; // how many lanes to enable
710 UCHAR ucReserved[2];
752 UCHAR ucReserved1:2;
753 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
754 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
755 UCHAR ucReserved:1;
756 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
758 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
759 UCHAR ucReserved:1;
760 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
761 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
762 UCHAR ucReserved1:2;
771 UCHAR ucAction;
772 UCHAR ucEncoderMode;
778 UCHAR ucLaneNum; // how many lanes to enable
779 …UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used…
780 UCHAR ucReserved;
819 UCHAR ucReserved1:1;
820 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
821 UCHAR ucReserved:3;
822 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
824 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
825 UCHAR ucReserved:3;
826 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
827 UCHAR ucReserved1:1;
846 UCHAR ucAction;
848 UCHAR ucEncoderMode;
855 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
860 UCHAR ucLaneNum; // how many lanes to enable
861 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
862 UCHAR ucReserved;
872 UCHAR ucReserved1:1;
873 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
874 UCHAR ucReserved:2;
875 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
877 …UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to prev…
878 UCHAR ucReserved:2;
879 …UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as D…
880 UCHAR ucReserved1:1;
903 UCHAR ucConfig;
905 UCHAR ucAction;
907 UCHAR ucEncoderMode;
914 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
919 UCHAR ucLaneNum; // how many lanes to enable
920 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
921 …UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to prev…
944 UCHAR ucLaneSel;
945 UCHAR ucLaneSet;
956 UCHAR ucConfig;
970 UCHAR ucAction; // =0: turn off encoder
972 UCHAR ucReserved[4];
1025 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1028 UCHAR ucReserved:1;
1029 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1030 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/…
1031 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1034 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1035 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1037 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1038 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1039 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1041 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/…
1042 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1043 UCHAR ucReserved:1;
1044 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1085 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1086 UCHAR ucReserved[4];
1092 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1095 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1096 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1097 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1099 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1100 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1102 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1103 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1104 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1106 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1107 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1108 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1124 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1125 UCHAR ucLaneNum;
1126 UCHAR ucReserved[3];
1167 UCHAR ucLaneSel;
1170 UCHAR ucLaneSet;
1173 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1174 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1175 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1177 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1178 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1179 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1188 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1191 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1192 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1193 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1195 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1196 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1198 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1199 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1200 …UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when…
1202 …UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path …
1203 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1204 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1221 UCHAR ucConfig;
1223 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1224 UCHAR ucLaneNum;
1225 UCHAR ucReserved[3];
1257 UCHAR ucReservd1:1;
1258 UCHAR ucHPDSel:3;
1259 UCHAR ucPhyClkSrcId:2;
1260 UCHAR ucCoherentMode:1;
1261 UCHAR ucReserved:1;
1263 UCHAR ucReserved:1;
1264 UCHAR ucCoherentMode:1;
1265 UCHAR ucPhyClkSrcId:2;
1266 UCHAR ucHPDSel:3;
1267 UCHAR ucReservd1:1;
1274 …UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIP…
1275 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1276 UCHAR ucLaneNum; // indicate lane number 1-8
1277 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1278 UCHAR ucDigMode; // indicate DIG mode
1281 UCHAR ucConfig;
1283 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1284 UCHAR ucDPLaneSet;
1285 UCHAR ucReserved;
1286 UCHAR ucReserved1;
1367 …UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE…
1368 UCHAR ucAction; //
1369 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1370 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1371 …UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT …
1372 UCHAR ucReserved;
1410 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1415 UCHAR aucPadding[3]; // padding to DWORD aligned
1451 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1452 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1466 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1467 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1468 UCHAR ucPadding[2];
1481 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1482 UCHAR ucPadding[3];
1491 UCHAR ucH_Replication; // horizontal replication
1492 UCHAR ucV_Replication; // vertical replication
1493 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1494 UCHAR ucPadding;
1503 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1504 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1505 UCHAR ucPadding[2];
1511 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1512 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1513 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1514 UCHAR ucPadding;
1548 UCHAR ucPostDiv; // post divider
1549 UCHAR ucFracFbDiv; // fractional feedback divider
1550 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1551 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1552 UCHAR ucCRTC; // Which CRTC uses this Ppll
1553 UCHAR ucPadding;
1568 UCHAR ucPostDiv; // post divider
1569 UCHAR ucFracFbDiv; // fractional feedback divider
1570 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1571 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1572 UCHAR ucCRTC; // Which CRTC uses this Ppll
1573 …UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device i…
1615 UCHAR ucPostDiv; // post divider
1616 UCHAR ucFracFbDiv; // fractional feedback divider
1617 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1618 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1621 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1622 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1624 …UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC …
1634 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1637 UCHAR ucReserved;
1638 …UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver …
1643 UCHAR ucPostDiv; // post divider.
1644 UCHAR ucRefDiv; // Reference divider
1645 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1646 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1648 UCHAR ucEncoderMode; // Encoder mode:
1649 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1691 UCHAR ucPostDiv; // post divider.
1692 UCHAR ucRefDiv; // Reference divider
1693 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1694 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1696 UCHAR ucEncoderMode; // Encoder mode:
1697 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1728 UCHAR ucStatus;
1729 …UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCI…
1730 UCHAR ucReserved[2];
1744 UCHAR ucTransmitterID;
1745 UCHAR ucEncodeMode;
1748 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
1749 UCHAR ucConfig; //if none DVO, not defined yet
1751 UCHAR ucReserved[3];
1760 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
1761 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1762 …UCHAR ucDispPllConfig; // display pll configure parameter defined as following DIS…
1763 UCHAR ucExtTransmitterID; // external encoder id.
1764 UCHAR ucReserved[2];
1783 …UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other …
1784 …UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other …
1785 UCHAR ucReserved[2];
1802 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1803 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
1804 UCHAR ucPadding[2];
1837 UCHAR ucSlaveAddr; //Read from which slave
1838 UCHAR ucLineNumber; //Read from which HW assisted line
1859 UCHAR ucData; //PS data1
1860 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
1861 UCHAR ucSlaveAddr; //Write to which slave
1862 UCHAR ucLineNumber; //Write from which HW assisted line
1870 UCHAR ucSlaveAddr; //Write to which slave
1871 UCHAR ucLineNumber; //Write from which HW assisted line
1884 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1885 UCHAR ucPwrBehaviorId;
1891 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
1892 UCHAR ucReserved;
1905 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
1906 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1907 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1908 UCHAR ucPadding[3];
1915 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int.…
1916 UCHAR ucSpreadSpectrumStep; //
1917 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
1918 UCHAR ucSpreadSpectrumDelay;
1919 UCHAR ucSpreadSpectrumRange;
1920 UCHAR ucPadding;
1927 …UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int…
1928 UCHAR ucSpreadSpectrumStep; //
1929 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1930 UCHAR ucSpreadSpectrumDelay;
1931 UCHAR ucSpreadSpectrumRange;
1932 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
1938 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1942 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1963 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
1967 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2018 UCHAR ucMisc; // bit0=0: Enable single link
2022 UCHAR ucAction; // 0: turn off encoder
2039 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2040 UCHAR ucAction; // 0: turn off encoder
2042 UCHAR ucTruncate; // bit0=0: Disable truncate
2046 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2050 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2056 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2088 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2089 …UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1…
2090 UCHAR ucPadding[2];
2130 UCHAR ucDVOConfig;
2131 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2132 UCHAR ucReseved[4];
2139 UCHAR ucDVOConfig;
2140 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2141 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
2142 UCHAR ucReseved[3];
2215 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2216 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2217 UCHAR ucVoltageIndex; // An index to tell which voltage level
2218 UCHAR ucReserved;
2223 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2224 …UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power …
2231 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2232 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2269 …UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/…
2270 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2308 …UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/…
2309 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2331 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2332 UCHAR ucAction; // 0: turn off encoder
2403 …UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2…
2404 …UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal…
2405 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2406 UCHAR ucHostPortInfo; // Provides host port configuration information
2416 …UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and vid…
2417 …UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and …
2418 …UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on produ…
2419 …UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM aud…
2420 …UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio…
2421 …UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (…
2422 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2423 …UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical co…
2424 …UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical co…
2425 …UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical co…
2426 …UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical co…
2427 …UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical co…
2519 UCHAR ucASICMaxTemperature;
2520 UCHAR ucPadding[3]; //Don't use them
2535 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2536 UCHAR ucDesign_ID; //Indicate what is the board design
2537 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2553 UCHAR ucASICMaxTemperature;
2554 UCHAR ucMinAllowedBL_Level;
2555 UCHAR ucPadding[2]; //Don't use them
2571 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2572 UCHAR ucDesign_ID; //Indicate what is the board design
2573 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2589 UCHAR ucASICMaxTemperature;
2590 UCHAR ucMinAllowedBL_Level;
2591 UCHAR ucPadding[2]; //Don't use them
2608 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2609 UCHAR ucDesign_ID; //Indicate what is the board design
2610 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2626 UCHAR ucASICMaxTemperature;
2627 UCHAR ucMinAllowedBL_Level;
2646 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2647 UCHAR ucDesign_ID; //Indicate what is the board design
2648 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2665 UCHAR ucReserved1; //Was ucASICMaxTemperature;
2666 UCHAR ucMinAllowedBL_Level;
2686 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2687 UCHAR ucReserved4[3];
2706 UCHAR ucReserved3; //Was ucASICMaxTemperature;
2707 UCHAR ucMinAllowedBL_Level;
2713 UCHAR ucRemoteDisplayConfig;
2714 …UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and us…
2725 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2726 UCHAR ucReserved9[3];
2754 UCHAR ucNumberOfCyclesInPeriodHi;
2755 …UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing des…
2769 UCHAR ucMaxNBVoltage;
2770 UCHAR ucMinNBVoltage;
2771 …UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is re…
2772 …UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCycl…
2773 …UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM…
2774 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
2775 UCHAR ucMaxNBVoltageHigh;
2776 UCHAR ucMinNBVoltageHigh;
2833 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
2834 UCHAR ucUMAChannelNumber;
2835 UCHAR ucDockingPinBit;
2836 UCHAR ucDockingPinPolarity;
3008 …UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal C…
3009 …UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status R…
3016 …UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is rese…
3017 UCHAR ucUMAChannelNumber;
3184 UCHAR bfHW_Capable:1;
3185 UCHAR bfHW_EngineID:3;
3186 UCHAR bfI2C_LineMux:4;
3188 UCHAR bfI2C_LineMux:4;
3189 UCHAR bfHW_EngineID:3;
3190 UCHAR bfHW_Capable:1;
3197 UCHAR ucAccess;
3215 UCHAR ucClkMaskShift;
3216 UCHAR ucClkEnShift;
3217 UCHAR ucClkY_Shift;
3218 UCHAR ucClkA_Shift;
3219 UCHAR ucDataMaskShift;
3220 UCHAR ucDataEnShift;
3221 UCHAR ucDataY_Shift;
3222 UCHAR ucDataA_Shift;
3223 UCHAR ucReserved1;
3224 UCHAR ucReserved2;
3332 UCHAR ucH_Border; // From DFP EDID
3333 UCHAR ucV_Border;
3334 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3335 UCHAR ucPadding[3];
3352 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3353 UCHAR ucOverscanRight; // right
3354 UCHAR ucOverscanLeft; // left
3355 UCHAR ucOverscanBottom; // bottom
3356 UCHAR ucOverscanTop; // top
3357 UCHAR ucReserved;
3383 UCHAR ucInternalModeNumber;
3384 UCHAR ucRefreshRate;
3400 UCHAR ucHBorder;
3401 UCHAR ucVBorder;
3403 UCHAR ucInternalModeNumber;
3404 UCHAR ucRefreshRate;
3425 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3426 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3427 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3431 UCHAR ucPanelDefaultRefreshRate;
3432 UCHAR ucPanelIdentification;
3433 UCHAR ucSS_Id;
3445 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3446 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3447 …UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:88…
3451 UCHAR ucPanelDefaultRefreshRate;
3452 UCHAR ucPanelIdentification;
3453 UCHAR ucSS_Id;
3456 UCHAR ucLCDPanel_SpecialHandlingCap;
3457 …UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include Ext…
3458 UCHAR ucReserved[2];
3508 UCHAR ucLCD_Misc; // Reorganized in V13
3514 UCHAR ucPanelDefaultRefreshRate;
3515 UCHAR ucPanelIdentification;
3516 UCHAR ucSS_Id;
3519 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
3524 …UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, inc…
3527 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
3528 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
3529 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
3530 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
3532 UCHAR ucOffDelay_in4Ms;
3533 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
3534 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
3535 UCHAR ucReserved1;
3537 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
3538 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
3539 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
3540 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
3543 UCHAR uceDPToLVDSRxId;
3544 UCHAR ucLcdReservd;
3591 UCHAR ucRecordType;
3598 UCHAR ucRecordType;
3599 UCHAR ucRTSValue;
3606 UCHAR ucRecordType;
3616 UCHAR ucRecordType;
3617 UCHAR ucFakeEDIDLength;
3618 UCHAR ucFakeEDIDString[]; // This actually has ucFakeEdidLength elements.
3623 UCHAR ucRecordType;
3643 …UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =…
3644 UCHAR ucSS_Step;
3645 UCHAR ucSS_Delay;
3646 UCHAR ucSS_Id;
3647 UCHAR ucRecommendedRef_Div;
3648 UCHAR ucSS_Range; //it was reserved for V11
3704 UCHAR ucTV_SupportedStandard;
3705 UCHAR ucTV_BootUpDefaultStandard;
3706 UCHAR ucExt_TV_ASIC_ID;
3707 UCHAR ucExt_TV_ASIC_SlaveAddr;
3717 UCHAR ucTV_SupportedStandard;
3718 UCHAR ucTV_BootUpDefaultStandard;
3719 UCHAR ucExt_TV_ASIC_ID;
3720 UCHAR ucExt_TV_ASIC_SlaveAddr;
3726 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
3727 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
3728 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3729 …UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change acc…
3880 UCHAR ucGpioPinBitShift;
3881 UCHAR ucGPIO_ID;
3913 UCHAR ucSettings;
3914 UCHAR ucReserved;
3956 UCHAR ucBitShift;
3957 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
3959 UCHAR ucMiscInfo;
3960 UCHAR uc480i;
3961 UCHAR uc480p;
3962 UCHAR uc720p;
3963 UCHAR uc1080i;
3964 UCHAR ucLetterBoxMode;
3965 UCHAR ucReserved[3];
3966 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
3976 UCHAR ucMiscInfo;
3977 UCHAR uc480i;
3978 UCHAR uc480p;
3979 UCHAR uc720p;
3980 UCHAR uc1080i;
3981 UCHAR ucReserved;
3982 UCHAR ucLetterBoxMode;
3983 …UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC t…
4036 UCHAR ucNumOfDispPath;
4037 UCHAR ucVersion;
4038 UCHAR ucPadding[2];
4053 UCHAR ucNumberOfObjects;
4054 UCHAR ucPadding[3];
4060 UCHAR ucNumberOfSrc;
4062 UCHAR ucNumberOfDst;
4098 UCHAR ucDP_Lane3_Source:2;
4099 UCHAR ucDP_Lane2_Source:2;
4100 UCHAR ucDP_Lane1_Source:2;
4101 UCHAR ucDP_Lane0_Source:2;
4103 UCHAR ucDP_Lane0_Source:2;
4104 UCHAR ucDP_Lane1_Source:2;
4105 UCHAR ucDP_Lane2_Source:2;
4106 UCHAR ucDP_Lane3_Source:2;
4118 UCHAR ucDVI_CLK_Source:2;
4119 UCHAR ucDVI_DATA0_Source:2;
4120 UCHAR ucDVI_DATA1_Source:2;
4121 UCHAR ucDVI_DATA2_Source:2;
4123 UCHAR ucDVI_DATA2_Source:2;
4124 UCHAR ucDVI_DATA1_Source:2;
4125 UCHAR ucDVI_DATA0_Source:2;
4126 UCHAR ucDVI_CLK_Source:2;
4135 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4136 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4139 …UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapp…
4143 …UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert…
4158 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4160 …UCHAR ucChecksum; // a simple Checksum of the sum of…
4161 UCHAR uc3DStereoPinId; // use for eDP panel
4162 UCHAR ucRemoteDisplayConfig;
4163 UCHAR uceDPToLVDSRxId;
4164 …UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_L…
4165 UCHAR Reserved[3]; // for potential expansion
4171 UCHAR ucRecordType; //An emun to indicate the record type
4172 UCHAR ucRecordSize; //The size of the whole record in byte
4205 …UCHAR ucI2CAddr; //The slave address, it's 0 when the record is…
4211 …UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table g…
4212 UCHAR ucPlugged_PinState;
4219 UCHAR ucProtectionFlag;
4220 UCHAR ucReserved;
4233 UCHAR ucNumberOfDevice;
4234 UCHAR ucReserved;
4242 UCHAR ucConfigGPIOID;
4243 …UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external …
4244 UCHAR ucFlowinGPIPID;
4245 UCHAR ucExtInGPIPID;
4251 UCHAR ucCTL1GPIO_ID;
4252 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4253 UCHAR ucCTL2GPIO_ID;
4254 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4255 UCHAR ucCTL3GPIO_ID;
4256 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4257 UCHAR ucCTLFPGA_IN_ID;
4258 UCHAR ucPadding[3];
4264 …UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table g…
4265 …UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is c…
4271 UCHAR ucTMSGPIO_ID;
4272 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4273 UCHAR ucTCKGPIO_ID;
4274 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4275 UCHAR ucTDOGPIO_ID;
4276 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4277 UCHAR ucTDIGPIO_ID;
4278 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4279 UCHAR ucPadding[2];
4286 …UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_…
4287 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4293 UCHAR ucFlags; // Future expnadibility
4294 …UCHAR ucNumberOfPins; // Number of GPIO pins used to control the obj…
4326 UCHAR ucPadding[2];
4360 UCHAR ucFlowCntlGpioId;
4361 UCHAR ucSwapCntlGpioId;
4362 UCHAR ucConnectedDvoBundle;
4363 UCHAR ucPadding;
4375 …UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_D…
4376 UCHAR ucReserved;
4383 …UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single …
4384 UCHAR ucMuxControlPin;
4385 UCHAR ucMuxState[2]; //for alligment purpose
4391 UCHAR ucMuxType;
4392 UCHAR ucMuxControlPin;
4393 UCHAR ucMuxState[2]; //for alligment purpose
4403 …UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size ar…
4427 UCHAR ucConnectorType;
4428 UCHAR ucPosition;
4442 UCHAR ucLength;
4443 UCHAR ucWidth;
4444 UCHAR ucConnNum;
4445 UCHAR ucReserved;
4456 UCHAR ucNumOfVoltageEntries;
4457 UCHAR ucBytesPerVoltageEntry;
4458 …UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv…
4459 UCHAR ucDefaultVoltageEntry;
4460 UCHAR ucVoltageControlI2cLine;
4461 UCHAR ucVoltageControlAddress;
4462 UCHAR ucVoltageControlOffset;
4469 …UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is pr…
4477 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4478 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
4479 …UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /Vo…
4480 UCHAR ucReserved;
4481 …UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present …
4492 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
4493 UCHAR ucReserved[3];
4499 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
4500 UCHAR ucVoltageControlI2cLine;
4501 UCHAR ucVoltageControlAddress;
4502 UCHAR ucVoltageControlOffset;
4504 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
4505 UCHAR ucReserved;
4532 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4533 UCHAR ucSize; //Size of Object
4540 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4541 UCHAR ucSize; //Size of Object
4560 UCHAR ucLeakageId;
4561 UCHAR ucReserved;
4566 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4567 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
4597 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
4598 UCHAR ucVoltageControlI2cLine;
4599 UCHAR ucVoltageControlAddress;
4600 UCHAR ucVoltageControlOffset;
4612 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
4613 …UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up t…
4614 UCHAR ucPhaseDelay; // phase delay in unit of micro second
4615 UCHAR ucReserved;
4623 UCHAR ucLeakageCntlId; // default is 0
4624 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
4625 UCHAR ucReserved[2];
4641 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
4642 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
4661 UCHAR ucProfileId;
4662 UCHAR ucReserved;
4683 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table
4686 UCHAR ucElbVDDC_Num;
4690 UCHAR ucElbVDDCI_Num;
4740 UCHAR ucPwrSrcId; // Power source
4741 UCHAR ucPwrSensorType; // GPIO, I2C or none
4742 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
4743 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
4744 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
4745 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
4746 UCHAR ucPwrSensActiveState; // high active or low active
4747 UCHAR ucReserve[3]; // reserve
4754 UCHAR asPwrbehave[16];
4800 UCHAR ucHtcTmpLmt;
4801 UCHAR ucHtcHystLmt;
4810 UCHAR ucMemoryType;
4811 UCHAR ucUMAChannelNumber;
4834 UCHAR ulBoostVid_2bit;
4835 UCHAR EnableBoost;
4838 UCHAR ucLvdsMisc;
4839 UCHAR ucLVDSReserved;
4998 UCHAR ucHtcTmpLmt;
4999 UCHAR ucHtcHystLmt;
5008 UCHAR ucMemoryType;
5009 UCHAR ucUMAChannelNumber;
5010 UCHAR strVBIOSMsg[40];
5032 UCHAR ulBoostVid_2bit;
5033 UCHAR EnableBoost;
5036 UCHAR ucLvdsMisc;
5037 UCHAR ucTravisLVDSVolAdjust;
5038 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5039 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5040 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5041 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5042 UCHAR ucLVDSOffToOnDelay_in4Ms;
5043 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5044 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5045 UCHAR ucMinAllowedBL_Level;
5051 UCHAR ucNBDPMEnable;
5052 UCHAR ucReserved[3];
5053 UCHAR ucDPMState0VclkFid;
5054 UCHAR ucDPMState0DclkFid;
5055 UCHAR ucDPMState1VclkFid;
5056 UCHAR ucDPMState1DclkFid;
5057 UCHAR ucDPMState2VclkFid;
5058 UCHAR ucDPMState2DclkFid;
5059 UCHAR ucDPMState3VclkFid;
5060 UCHAR ucDPMState3DclkFid;
5225 UCHAR ucHtcTmpLmt;
5226 UCHAR ucHtcHystLmt;
5234 UCHAR ucMemoryType;
5235 UCHAR ucUMAChannelNumber;
5236 UCHAR strVBIOSMsg[40];
5257 UCHAR ucLvdsMisc;
5258 UCHAR ucTravisLVDSVolAdjust;
5259 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5260 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5261 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5262 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5263 UCHAR ucLVDSOffToOnDelay_in4Ms;
5264 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5265 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5266 UCHAR ucMinAllowedBL_Level;
5441 …UCHAR ucNunberOfBytes; //Indicates how many b…
5442 …UCHAR ucI2CData[]; //I2C data in bytes, s…
5450 UCHAR ucSSChipID; //SS chip being used
5451 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
5452 UCHAR ucNumOfI2CDataRecords; //number of data block
5474 UCHAR ucClockIndication; //Indicate which clock source needs SS
5475 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
5476 UCHAR ucReserved[2];
5500 UCHAR ucClockIndication; //Indicate which clock source needs SS
5501 …UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS …
5502 UCHAR ucReserved[2];
5531 UCHAR ucClockIndication; //Indicate which clock source needs SS
5532 …UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS …
5533 UCHAR ucReserved[2];
6004 UCHAR ucAction; //not define yet
6005 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
6006 UCHAR ucFbDiv; //FB value
6007 UCHAR ucPostDiv; //Post div
6018 UCHAR ucGPIO_ID; //return value, read from GPIO pins
6019 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
6020 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
6021 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
6026 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
6027 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
6028 UCHAR ucTVStandard; //
6029 UCHAR ucPadding[1];
6042 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
6043 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
6044 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
6045 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
6058 UCHAR ucSurface; // Surface 1 or 2
6059 UCHAR ucPadding[3];
6066 UCHAR ucSurface; // Surface 1 or 2
6067 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
6068 UCHAR ucPadding[2];
6075 UCHAR ucSurface; // Surface 1 or 2
6076 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
6085 UCHAR ucColorDepth;
6086 UCHAR ucPixelFormat;
6087 UCHAR ucSurface; // Surface 1 or 2
6088 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
6089 UCHAR ucModeType;
6090 UCHAR ucReserved;
6130 UCHAR ucLutId;
6131 UCHAR ucAction;
6145 UCHAR ucInterruptId;
6146 UCHAR ucServiceId;
6147 UCHAR ucStatus;
6148 UCHAR ucReserved;
6171 UCHAR IOAccessSequence[256];
6206 UCHAR ucVMode_Num; //Video mode number
6207 UCHAR ucTV_Mode_Num; //Internal TV mode number
6225 UCHAR ucTV_Mode_Num;
6257 UCHAR ucMemoryType;
6258 UCHAR ucMemoryVendor;
6259 UCHAR ucAdjMCId;
6260 UCHAR ucDynClkId;
6290 …UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BL…
6375 UCHAR ucRevision;
6376 UCHAR ucChecksum;
6377 UCHAR ucReserved1;
6378 UCHAR ucReserved2;
6396 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or p…
6397 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6398 …UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory …
6399 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6400 UCHAR ucRow; // Number of Row,in power of 2;
6401 UCHAR ucColumn; // Number of Column,in power of 2;
6402 UCHAR ucBank; // Nunber of Bank;
6403 UCHAR ucRank; // Number of Rank, in power of 2
6404 UCHAR ucChannelNum; // Number of channel;
6405 …UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7…
6406 …UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID l…
6407 …UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID l…
6408 UCHAR ucReserved[2];
6423 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or p…
6424 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6425 …UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory …
6426 …UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x…
6427 UCHAR ucRow; // Number of Row,in power of 2;
6428 UCHAR ucColumn; // Number of Column,in power of 2;
6429 UCHAR ucBank; // Nunber of Bank;
6430 UCHAR ucRank; // Number of Rank, in power of 2
6431 UCHAR ucChannelNum; // Number of channel;
6432 …UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7…
6433 …UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID l…
6434 …UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID l…
6435 UCHAR ucRefreshRateFactor;
6436 UCHAR ucReserved[3];
6451 UCHAR ucCL; // CAS latency
6452 UCHAR ucWL; // WRITE Latency
6453 UCHAR uctRAS; // tRAS
6454 UCHAR uctRC; // tRC
6455 UCHAR uctRFC; // tRFC
6456 UCHAR uctRCDR; // tRCDR
6457 UCHAR uctRCDW; // tRCDW
6458 UCHAR uctRP; // tRP
6459 UCHAR uctRRD; // tRRD
6460 UCHAR uctWR; // tWR
6461 UCHAR uctWTR; // tWTR
6462 UCHAR uctPDIX; // tPDIX
6463 UCHAR uctFAW; // tFAW
6464 UCHAR uctAOND; // tAOND
6468 …UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 In…
6469 UCHAR ucReserved;
6481 UCHAR ucCL; // CAS latency
6482 UCHAR ucWL; // WRITE Latency
6483 UCHAR uctRAS; // tRAS
6484 UCHAR uctRC; // tRC
6485 UCHAR uctRFC; // tRFC
6486 UCHAR uctRCDR; // tRCDR
6487 UCHAR uctRCDW; // tRCDW
6488 UCHAR uctRP; // tRP
6489 UCHAR uctRRD; // tRRD
6490 UCHAR uctWR; // tWR
6491 UCHAR uctWTR; // tWTR
6492 UCHAR uctPDIX; // tPDIX
6493 UCHAR uctFAW; // tFAW
6494 UCHAR uctAOND; // tAOND
6495 …UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 In…
6497 UCHAR uctCCDL; //
6498 UCHAR uctCRCRL; //
6499 UCHAR uctCRCWL; //
6500 UCHAR uctCKE; //
6501 UCHAR uctCKRSE; //
6502 UCHAR uctCKRSX; //
6503 UCHAR uctFAW32; //
6504 UCHAR ucMR5lo; //
6505 UCHAR ucMR5hi; //
6506 UCHAR ucTerminator;
6514 UCHAR ucCL; // CAS latency
6515 UCHAR ucWL; // WRITE Latency
6516 UCHAR uctRAS; // tRAS
6517 UCHAR uctRC; // tRC
6518 UCHAR uctRFC; // tRFC
6519 UCHAR uctRCDR; // tRCDR
6520 UCHAR uctRCDW; // tRCDW
6521 UCHAR uctRP; // tRP
6522 UCHAR uctRRD; // tRRD
6523 UCHAR uctWR; // tWR
6524 UCHAR uctWTR; // tWTR
6525 UCHAR uctPDIX; // tPDIX
6526 UCHAR uctFAW; // tFAW
6527 UCHAR uctAOND; // tAOND
6528 …UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 In…
6530 UCHAR uctCCDL; //
6531 UCHAR uctCRCRL; //
6532 UCHAR uctCRCWL; //
6533 UCHAR uctCKE; //
6534 UCHAR uctCKRSE; //
6535 UCHAR uctCKRSX; //
6536 UCHAR uctFAW32; //
6537 UCHAR ucMR4lo; //
6538 UCHAR ucMR4hi; //
6539 UCHAR ucMR5lo; //
6540 UCHAR ucMR5hi; //
6541 UCHAR ucTerminator;
6542 UCHAR ucReserved;
6556 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0…
6557 …UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory …
6558 UCHAR ucRow; // Number of Row,in power of 2;
6559 UCHAR ucColumn; // Number of Column,in power of 2;
6560 UCHAR ucBank; // Nunber of Bank;
6561 UCHAR ucRank; // Number of Rank, in power of 2
6562 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
6563 …UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extende…
6564 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
6565 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6566 UCHAR ucPreamble; //[7:4] Write Preamble, [3:0] Read Preamble
6567 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
6578 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or p…
6579 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
6580 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
6581 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
6582 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calcula…
6583 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6601 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to…
6602 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
6603 UCHAR ucChannelNum; // Number of channels present in this module config
6604 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6605 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6606 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6607 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlen…
6608 UCHAR ucVREFI; // board dependent parameter
6609 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
6610 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6611 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
6613 UCHAR ucReserved[3];
6624 …UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table …
6625 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6626 UCHAR ucReserved2[2];
6643 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to…
6644 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
6645 UCHAR ucChannelNum; // Number of channels present in this module config
6646 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6647 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6648 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6649 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlen…
6650 UCHAR ucVREFI; // board dependent parameter
6651 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
6652 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6653 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
6655 UCHAR ucReserved[3];
6660 …UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table …
6661 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6662 …UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detecti…
6663 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6674 …UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to…
6675 …UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR…
6676 UCHAR ucChannelNum; // Number of channels present in this module config
6677 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
6678 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6679 UCHAR ucFlag; // To enable/disable functionalities based on memory type
6680 …UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlen…
6681 UCHAR ucVREFI; // board dependent parameter
6682 …UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used …
6683 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6684 …UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, u…
6686 UCHAR ucReserved[3];
6691 …UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table …
6692 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6693 …UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detecti…
6694 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6705 UCHAR ucExtMemoryID; // Current memory module ID
6706 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
6707 UCHAR ucChannelNum; // Number of mem. channels supported in this module
6708 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
6709 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
6710 …UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE…
6711 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
6712 UCHAR ucVREFI; // Not used.
6713 …UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NP…
6714 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
6715 …UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE …
6717 UCHAR ucReserved;
6721 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
6722 …UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
6723 …UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, h…
6724 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
6731 UCHAR ucNumOfVRAMModule;
6741 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
6742 UCHAR ucNumOfVRAMModule;
6756 …UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Da…
6758 UCHAR ucReservde[4];
6759 UCHAR ucNumOfVRAMModule;
6772 …UCHAR ucNumOfVRAMModule; // indicate number of V…
6773 …UCHAR ucMemoryClkPatchTblVer; // version of memory AC…
6774 …UCHAR ucVramModuleVer; // indicate ATOM_VRAM_M…
6775 UCHAR ucReserved;
6783 UCHAR aVID_PinsShift[9]; //8 bit strap maximum+terminator
6790 UCHAR ucTrainingLoop;
6791 UCHAR ucReserved[3];
6798 UCHAR ucControl;
6799 UCHAR ucData;
6800 UCHAR ucSatus;
6801 UCHAR ucTemp;
6809 UCHAR ucAct;
6810 UCHAR ucData;
6856 UCHAR VbeSignature[4];
6859 UCHAR Capabilities[4];
6883 UCHAR Reserved[222];
6884 UCHAR OemData[256];
6892 UCHAR RedBPP;
6893 UCHAR GreenBPP;
6894 UCHAR BlueBPP;
6895 UCHAR ReservedBPP;
6898 UCHAR Reserved[14];
6905 UCHAR WinAAttributes; // db ? ; window A attributes
6906 UCHAR WinBAttributes; // db ? ; window B attributes
6917 UCHAR XCharSize; // db ? ; character cell width in pixels
6918 UCHAR YCharSize; // db ? ; character cell height in pixels
6919 UCHAR NumberOfPlanes; // db ? ; number of memory planes
6920 UCHAR BitsPerPixel; // db ? ; bits per pixel
6921 UCHAR NumberOfBanks; // db ? ; number of banks
6922 UCHAR MemoryModel; // db ? ; memory model type
6923 UCHAR BankSize; // db ? ; bank size in KB
6924 UCHAR NumberOfImagePages;// db ? ; number of images
6925 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
6928 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
6929 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
6930 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
6931 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
6932 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
6933 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
6934 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
6935 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
6936 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
6945 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
6946 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
6947 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
6948 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
6949 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
6950 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
6951 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
6952 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
6953 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
6954 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
6956 UCHAR Reserved; // db 190 dup (0)
7012 UCHAR ucTransmitterCmdTblId;
7013 UCHAR ucConfig;
7014 UCHAR ucEncoderID; //available 1st encoder ( default )
7015 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
7016 UCHAR uc2ndEncoderID;
7017 UCHAR ucReserved;
7032 UCHAR ucEncoderID;
7033 UCHAR ucEncoderConfig;
7058 UCHAR ucPpllId;
7059 UCHAR ucPpllAttribute;
7072 UCHAR ucTransmitterCmdTblId;
7073 UCHAR ucConfig;
7074 UCHAR ucEncoderID; // available 1st encoder ( default )
7075 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
7076 UCHAR uc2ndEncoderID;
7077 UCHAR ucReserved;
7087 UCHAR ucDCERevision;
7088 UCHAR ucMaxDispEngineNum;
7089 UCHAR ucMaxActiveDispEngineNum;
7090 UCHAR ucMaxPPLLNum;
7091 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
7092 UCHAR ucDispCaps;
7093 UCHAR ucReserved[2];
7119 UCHAR ucChannelID;
7122 UCHAR ucReplyStatus;
7123 UCHAR ucDelay;
7125 UCHAR ucDataOutLen;
7126 UCHAR ucReserved;
7134 UCHAR ucChannelID;
7137 UCHAR ucReplyStatus;
7138 UCHAR ucDelay;
7140 UCHAR ucDataOutLen;
7141 …UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, …
7153 UCHAR ucConfig; // for DP training command
7154 UCHAR ucI2cId; // use for GET_SINK_TYPE command
7156 UCHAR ucAction;
7157 UCHAR ucStatus;
7158 UCHAR ucLaneNum;
7159 UCHAR ucReserved[2];
7187 UCHAR ucAuxId;
7188 UCHAR ucAction;
7189 UCHAR ucSinkType; // Iput and Output parameters.
7190 …UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_…
7191 UCHAR ucReserved[2];
7222 UCHAR ucI2CSpeed;
7225 UCHAR ucRegIndex;
7226 UCHAR ucStatus;
7229 UCHAR ucFlag;
7230 UCHAR ucTransBytes;
7231 UCHAR ucSlaveAddr;
7232 UCHAR ucLineNumber;
7247 UCHAR ucCmd; // Input: To tell which action to take
7248 UCHAR ucReserved[3];
7254 UCHAR ucReturnCode; // Output: Return value base on action was taken
7255 UCHAR ucReserved[3];
7277 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
7278 UCHAR ucReserved[3];
7318 UCHAR ucStartBit;
7319 UCHAR ucEndBit;
7324 UCHAR ucEncodeMode;
7325 UCHAR ucPhySel;
7341 UCHAR ucCondition2;
7358 UCHAR ucEncodeMode;
7359 UCHAR ucPhySel;
7365 UCHAR ucEncodeMode;
7366 UCHAR ucPhySel;
7372 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM
7373 UCHAR ucReserved; //reserved
7374 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array
7375 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
7423 UCHAR ucDAC1_BG_Adjustment;
7424 UCHAR ucDAC1_DAC_Adjustment;
7427 UCHAR ucDAC2_CRT2_BG_Adjustment;
7428 UCHAR ucDAC2_CRT2_DAC_Adjustment;
7431 …UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7432 UCHAR ucDAC2_NTSC_BG_Adjustment;
7433 UCHAR ucDAC2_NTSC_DAC_Adjustment;
7436 …UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7437 UCHAR ucDAC2_CV_BG_Adjustment;
7438 UCHAR ucDAC2_CV_DAC_Adjustment;
7441 …UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active L…
7442 UCHAR ucDAC2_PAL_BG_Adjustment;
7443 UCHAR ucDAC2_PAL_DAC_Adjustment;
7474 UCHAR bfConnectorType:4;
7475 UCHAR bfAssociatedDAC:4;
7477 UCHAR bfAssociatedDAC:4;
7478 UCHAR bfConnectorType:4;
7485 UCHAR ucAccess;
7506 UCHAR ucIntSrcBitmap;
7532 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
7533 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
7534 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
7535 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
7551 UCHAR ucTVStandard; //Same as TV standards defined above,
7552 UCHAR ucPadding[1];
7557 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
7558 UCHAR ucPadding[1];
7572 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
7573 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
7597 UCHAR ucXtransimitterID;
7598 …UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,…
7599 …UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's poss…
7601 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
7602 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
7607 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
7608 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
7609 UCHAR ucPadding[2];
7677 UCHAR ucVoltageDropIndex; // index to GPIO table
7678 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7679 UCHAR ucMinTemperature;
7680 UCHAR ucMaxTemperature;
7681 UCHAR ucNumPciELanes; // number of PCIE lanes
7692 UCHAR ucVoltageDropIndex; // index to GPIO table
7693 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7694 UCHAR ucMinTemperature;
7695 UCHAR ucMaxTemperature;
7696 UCHAR ucNumPciELanes; // number of PCIE lanes
7707 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
7708 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
7709 UCHAR ucMinTemperature;
7710 UCHAR ucMaxTemperature;
7711 UCHAR ucNumPciELanes; // number of PCIE lanes
7712 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
7733 UCHAR ucOverdriveThermalController;
7734 UCHAR ucOverdriveI2cLine;
7735 UCHAR ucOverdriveIntBitmap;
7736 UCHAR ucOverdriveControllerAddress;
7737 UCHAR ucSizeOfPowerModeEntry;
7738 UCHAR ucNumOfPowerModeEntries;
7745 UCHAR ucOverdriveThermalController;
7746 UCHAR ucOverdriveI2cLine;
7747 UCHAR ucOverdriveIntBitmap;
7748 UCHAR ucOverdriveControllerAddress;
7749 UCHAR ucSizeOfPowerModeEntry;
7750 UCHAR ucNumOfPowerModeEntries;
7757 UCHAR ucOverdriveThermalController;
7758 UCHAR ucOverdriveI2cLine;
7759 UCHAR ucOverdriveIntBitmap;
7760 UCHAR ucOverdriveControllerAddress;
7761 UCHAR ucSizeOfPowerModeEntry;
7762 UCHAR ucNumOfPowerModeEntries;
7921 UCHAR Revision;
7922 UCHAR Checksum;
7923 UCHAR OemId[6];
7924 UCHAR OemTableId[8]; //UINT64 OemTableId;
7945 UCHAR TableUUID[16]; //0x24
7966 UCHAR VbiosContent[];
7971 UCHAR Lib1Content[1];